1 /* 2 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _HSE_RTC, 60 _CSI_KER, 61 _PLL1_P, 62 _PLL1_Q, 63 _PLL1_R, 64 _PLL2_P, 65 _PLL2_Q, 66 _PLL2_R, 67 _PLL3_P, 68 _PLL3_Q, 69 _PLL3_R, 70 _PLL4_P, 71 _PLL4_Q, 72 _PLL4_R, 73 _ACLK, 74 _PCLK1, 75 _PCLK2, 76 _PCLK3, 77 _PCLK4, 78 _PCLK5, 79 _HCLK6, 80 _HCLK2, 81 _CK_PER, 82 _CK_MPU, 83 _CK_MCU, 84 _USB_PHY_48, 85 _PARENT_NB, 86 _UNKNOWN_ID = 0xff, 87 }; 88 89 /* Lists only the parent clock we are interested in */ 90 enum stm32mp1_parent_sel { 91 _I2C12_SEL, 92 _I2C35_SEL, 93 _STGEN_SEL, 94 _I2C46_SEL, 95 _SPI6_SEL, 96 _UART1_SEL, 97 _RNG1_SEL, 98 _UART6_SEL, 99 _UART24_SEL, 100 _UART35_SEL, 101 _UART78_SEL, 102 _SDMMC12_SEL, 103 _SDMMC3_SEL, 104 _QSPI_SEL, 105 _FMC_SEL, 106 _AXIS_SEL, 107 _MCUS_SEL, 108 _USBPHY_SEL, 109 _USBO_SEL, 110 _MPU_SEL, 111 _CKPER_SEL, 112 _RTC_SEL, 113 _PARENT_SEL_NB, 114 _UNKNOWN_SEL = 0xff, 115 }; 116 117 /* State the parent clock ID straight related to a clock */ 118 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 119 [_HSE] = CK_HSE, 120 [_HSI] = CK_HSI, 121 [_CSI] = CK_CSI, 122 [_LSE] = CK_LSE, 123 [_LSI] = CK_LSI, 124 [_I2S_CKIN] = _UNKNOWN_ID, 125 [_USB_PHY_48] = _UNKNOWN_ID, 126 [_HSI_KER] = CK_HSI, 127 [_HSE_KER] = CK_HSE, 128 [_HSE_KER_DIV2] = CK_HSE_DIV2, 129 [_HSE_RTC] = _UNKNOWN_ID, 130 [_CSI_KER] = CK_CSI, 131 [_PLL1_P] = PLL1_P, 132 [_PLL1_Q] = PLL1_Q, 133 [_PLL1_R] = PLL1_R, 134 [_PLL2_P] = PLL2_P, 135 [_PLL2_Q] = PLL2_Q, 136 [_PLL2_R] = PLL2_R, 137 [_PLL3_P] = PLL3_P, 138 [_PLL3_Q] = PLL3_Q, 139 [_PLL3_R] = PLL3_R, 140 [_PLL4_P] = PLL4_P, 141 [_PLL4_Q] = PLL4_Q, 142 [_PLL4_R] = PLL4_R, 143 [_ACLK] = CK_AXI, 144 [_PCLK1] = CK_AXI, 145 [_PCLK2] = CK_AXI, 146 [_PCLK3] = CK_AXI, 147 [_PCLK4] = CK_AXI, 148 [_PCLK5] = CK_AXI, 149 [_CK_PER] = CK_PER, 150 [_CK_MPU] = CK_MPU, 151 [_CK_MCU] = CK_MCU, 152 }; 153 154 static unsigned int clock_id2parent_id(unsigned long id) 155 { 156 unsigned int n; 157 158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 159 if (parent_id_clock_id[n] == id) { 160 return n; 161 } 162 } 163 164 return _UNKNOWN_ID; 165 } 166 167 enum stm32mp1_pll_id { 168 _PLL1, 169 _PLL2, 170 _PLL3, 171 _PLL4, 172 _PLL_NB 173 }; 174 175 enum stm32mp1_div_id { 176 _DIV_P, 177 _DIV_Q, 178 _DIV_R, 179 _DIV_NB, 180 }; 181 182 enum stm32mp1_clksrc_id { 183 CLKSRC_MPU, 184 CLKSRC_AXI, 185 CLKSRC_MCU, 186 CLKSRC_PLL12, 187 CLKSRC_PLL3, 188 CLKSRC_PLL4, 189 CLKSRC_RTC, 190 CLKSRC_MCO1, 191 CLKSRC_MCO2, 192 CLKSRC_NB 193 }; 194 195 enum stm32mp1_clkdiv_id { 196 CLKDIV_MPU, 197 CLKDIV_AXI, 198 CLKDIV_MCU, 199 CLKDIV_APB1, 200 CLKDIV_APB2, 201 CLKDIV_APB3, 202 CLKDIV_APB4, 203 CLKDIV_APB5, 204 CLKDIV_RTC, 205 CLKDIV_MCO1, 206 CLKDIV_MCO2, 207 CLKDIV_NB 208 }; 209 210 enum stm32mp1_pllcfg { 211 PLLCFG_M, 212 PLLCFG_N, 213 PLLCFG_P, 214 PLLCFG_Q, 215 PLLCFG_R, 216 PLLCFG_O, 217 PLLCFG_NB 218 }; 219 220 enum stm32mp1_pllcsg { 221 PLLCSG_MOD_PER, 222 PLLCSG_INC_STEP, 223 PLLCSG_SSCG_MODE, 224 PLLCSG_NB 225 }; 226 227 enum stm32mp1_plltype { 228 PLL_800, 229 PLL_1600, 230 PLL_TYPE_NB 231 }; 232 233 struct stm32mp1_pll { 234 uint8_t refclk_min; 235 uint8_t refclk_max; 236 uint8_t divn_max; 237 }; 238 239 struct stm32mp1_clk_gate { 240 uint16_t offset; 241 uint8_t bit; 242 uint8_t index; 243 uint8_t set_clr; 244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 245 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 246 }; 247 248 struct stm32mp1_clk_sel { 249 uint16_t offset; 250 uint8_t src; 251 uint8_t msk; 252 uint8_t nb_parent; 253 const uint8_t *parent; 254 }; 255 256 #define REFCLK_SIZE 4 257 struct stm32mp1_clk_pll { 258 enum stm32mp1_plltype plltype; 259 uint16_t rckxselr; 260 uint16_t pllxcfgr1; 261 uint16_t pllxcfgr2; 262 uint16_t pllxfracr; 263 uint16_t pllxcr; 264 uint16_t pllxcsgr; 265 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 266 }; 267 268 /* Clocks with selectable source and non set/clr register access */ 269 #define _CLK_SELEC(off, b, idx, s) \ 270 { \ 271 .offset = (off), \ 272 .bit = (b), \ 273 .index = (idx), \ 274 .set_clr = 0, \ 275 .sel = (s), \ 276 .fixed = _UNKNOWN_ID, \ 277 } 278 279 /* Clocks with fixed source and non set/clr register access */ 280 #define _CLK_FIXED(off, b, idx, f) \ 281 { \ 282 .offset = (off), \ 283 .bit = (b), \ 284 .index = (idx), \ 285 .set_clr = 0, \ 286 .sel = _UNKNOWN_SEL, \ 287 .fixed = (f), \ 288 } 289 290 /* Clocks with selectable source and set/clr register access */ 291 #define _CLK_SC_SELEC(off, b, idx, s) \ 292 { \ 293 .offset = (off), \ 294 .bit = (b), \ 295 .index = (idx), \ 296 .set_clr = 1, \ 297 .sel = (s), \ 298 .fixed = _UNKNOWN_ID, \ 299 } 300 301 /* Clocks with fixed source and set/clr register access */ 302 #define _CLK_SC_FIXED(off, b, idx, f) \ 303 { \ 304 .offset = (off), \ 305 .bit = (b), \ 306 .index = (idx), \ 307 .set_clr = 1, \ 308 .sel = _UNKNOWN_SEL, \ 309 .fixed = (f), \ 310 } 311 312 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 313 [_ ## _label ## _SEL] = { \ 314 .offset = _rcc_selr, \ 315 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 316 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 317 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 318 .parent = (_parents), \ 319 .nb_parent = ARRAY_SIZE(_parents) \ 320 } 321 322 #define _CLK_PLL(idx, type, off1, off2, off3, \ 323 off4, off5, off6, \ 324 p1, p2, p3, p4) \ 325 [(idx)] = { \ 326 .plltype = (type), \ 327 .rckxselr = (off1), \ 328 .pllxcfgr1 = (off2), \ 329 .pllxcfgr2 = (off3), \ 330 .pllxfracr = (off4), \ 331 .pllxcr = (off5), \ 332 .pllxcsgr = (off6), \ 333 .refclk[0] = (p1), \ 334 .refclk[1] = (p2), \ 335 .refclk[2] = (p3), \ 336 .refclk[3] = (p4), \ 337 } 338 339 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 340 341 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 342 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 343 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 344 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 345 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 346 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 347 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 348 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 349 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 350 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 351 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 352 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 353 354 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 363 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 364 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 365 366 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 367 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 368 369 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 370 371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 372 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 373 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 374 375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 377 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 378 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 383 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 384 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 385 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 386 387 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 388 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 389 390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 399 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 400 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 401 402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 403 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 405 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 406 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 407 408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 411 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 412 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 413 414 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), 415 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 416 }; 417 418 static const uint8_t i2c12_parents[] = { 419 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 420 }; 421 422 static const uint8_t i2c35_parents[] = { 423 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 424 }; 425 426 static const uint8_t stgen_parents[] = { 427 _HSI_KER, _HSE_KER 428 }; 429 430 static const uint8_t i2c46_parents[] = { 431 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 432 }; 433 434 static const uint8_t spi6_parents[] = { 435 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 436 }; 437 438 static const uint8_t usart1_parents[] = { 439 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 440 }; 441 442 static const uint8_t rng1_parents[] = { 443 _CSI, _PLL4_R, _LSE, _LSI 444 }; 445 446 static const uint8_t uart6_parents[] = { 447 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 448 }; 449 450 static const uint8_t uart234578_parents[] = { 451 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 452 }; 453 454 static const uint8_t sdmmc12_parents[] = { 455 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 456 }; 457 458 static const uint8_t sdmmc3_parents[] = { 459 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 460 }; 461 462 static const uint8_t qspi_parents[] = { 463 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 464 }; 465 466 static const uint8_t fmc_parents[] = { 467 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 468 }; 469 470 static const uint8_t axiss_parents[] = { 471 _HSI, _HSE, _PLL2_P 472 }; 473 474 static const uint8_t mcuss_parents[] = { 475 _HSI, _HSE, _CSI, _PLL3_P 476 }; 477 478 static const uint8_t usbphy_parents[] = { 479 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 480 }; 481 482 static const uint8_t usbo_parents[] = { 483 _PLL4_R, _USB_PHY_48 484 }; 485 486 static const uint8_t mpu_parents[] = { 487 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 488 }; 489 490 static const uint8_t per_parents[] = { 491 _HSI, _HSE, _CSI, 492 }; 493 494 static const uint8_t rtc_parents[] = { 495 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 496 }; 497 498 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 499 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 500 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 501 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 502 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 503 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 504 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 505 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 506 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 507 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 508 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 509 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 510 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 511 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 512 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 513 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 514 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 515 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 516 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 517 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 518 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 519 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 520 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 521 }; 522 523 /* Define characteristic of PLL according type */ 524 #define DIVN_MIN 24 525 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 526 [PLL_800] = { 527 .refclk_min = 4, 528 .refclk_max = 16, 529 .divn_max = 99, 530 }, 531 [PLL_1600] = { 532 .refclk_min = 8, 533 .refclk_max = 16, 534 .divn_max = 199, 535 }, 536 }; 537 538 /* PLLNCFGR2 register divider by output */ 539 static const uint8_t pllncfgr2[_DIV_NB] = { 540 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 541 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 542 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 543 }; 544 545 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 546 _CLK_PLL(_PLL1, PLL_1600, 547 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 548 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 549 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 550 _CLK_PLL(_PLL2, PLL_1600, 551 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 552 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 553 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 554 _CLK_PLL(_PLL3, PLL_800, 555 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 556 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 557 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 558 _CLK_PLL(_PLL4, PLL_800, 559 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 560 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 561 _HSI, _HSE, _CSI, _I2S_CKIN), 562 }; 563 564 /* Prescaler table lookups for clock computation */ 565 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 566 static const uint8_t stm32mp1_mcu_div[16] = { 567 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 568 }; 569 570 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 571 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 572 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 573 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 574 0, 1, 2, 3, 4, 4, 4, 4 575 }; 576 577 /* div = /1 /2 /3 /4 */ 578 static const uint8_t stm32mp1_axi_div[8] = { 579 1, 2, 3, 4, 4, 4, 4, 4 580 }; 581 582 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 583 [_HSI] = "HSI", 584 [_HSE] = "HSE", 585 [_CSI] = "CSI", 586 [_LSI] = "LSI", 587 [_LSE] = "LSE", 588 [_I2S_CKIN] = "I2S_CKIN", 589 [_HSI_KER] = "HSI_KER", 590 [_HSE_KER] = "HSE_KER", 591 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 592 [_HSE_RTC] = "HSE_RTC", 593 [_CSI_KER] = "CSI_KER", 594 [_PLL1_P] = "PLL1_P", 595 [_PLL1_Q] = "PLL1_Q", 596 [_PLL1_R] = "PLL1_R", 597 [_PLL2_P] = "PLL2_P", 598 [_PLL2_Q] = "PLL2_Q", 599 [_PLL2_R] = "PLL2_R", 600 [_PLL3_P] = "PLL3_P", 601 [_PLL3_Q] = "PLL3_Q", 602 [_PLL3_R] = "PLL3_R", 603 [_PLL4_P] = "PLL4_P", 604 [_PLL4_Q] = "PLL4_Q", 605 [_PLL4_R] = "PLL4_R", 606 [_ACLK] = "ACLK", 607 [_PCLK1] = "PCLK1", 608 [_PCLK2] = "PCLK2", 609 [_PCLK3] = "PCLK3", 610 [_PCLK4] = "PCLK4", 611 [_PCLK5] = "PCLK5", 612 [_HCLK6] = "KCLK6", 613 [_HCLK2] = "HCLK2", 614 [_CK_PER] = "CK_PER", 615 [_CK_MPU] = "CK_MPU", 616 [_CK_MCU] = "CK_MCU", 617 [_USB_PHY_48] = "USB_PHY_48", 618 }; 619 620 /* RCC clock device driver private */ 621 static unsigned long stm32mp1_osc[NB_OSC]; 622 static struct spinlock reg_lock; 623 static unsigned int gate_refcounts[NB_GATES]; 624 static struct spinlock refcount_lock; 625 626 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 627 { 628 return &stm32mp1_clk_gate[idx]; 629 } 630 631 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 632 { 633 return &stm32mp1_clk_sel[idx]; 634 } 635 636 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 637 { 638 return &stm32mp1_clk_pll[idx]; 639 } 640 641 static void stm32mp1_clk_lock(struct spinlock *lock) 642 { 643 if (stm32mp_lock_available()) { 644 /* Assume interrupts are masked */ 645 spin_lock(lock); 646 } 647 } 648 649 static void stm32mp1_clk_unlock(struct spinlock *lock) 650 { 651 if (stm32mp_lock_available()) { 652 spin_unlock(lock); 653 } 654 } 655 656 bool stm32mp1_rcc_is_secure(void) 657 { 658 uintptr_t rcc_base = stm32mp_rcc_base(); 659 uint32_t mask = RCC_TZCR_TZEN; 660 661 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 662 } 663 664 bool stm32mp1_rcc_is_mckprot(void) 665 { 666 uintptr_t rcc_base = stm32mp_rcc_base(); 667 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 668 669 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 670 } 671 672 void stm32mp1_clk_rcc_regs_lock(void) 673 { 674 stm32mp1_clk_lock(®_lock); 675 } 676 677 void stm32mp1_clk_rcc_regs_unlock(void) 678 { 679 stm32mp1_clk_unlock(®_lock); 680 } 681 682 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 683 { 684 if (idx >= NB_OSC) { 685 return 0; 686 } 687 688 return stm32mp1_osc[idx]; 689 } 690 691 static int stm32mp1_clk_get_gated_id(unsigned long id) 692 { 693 unsigned int i; 694 695 for (i = 0U; i < NB_GATES; i++) { 696 if (gate_ref(i)->index == id) { 697 return i; 698 } 699 } 700 701 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 702 703 return -EINVAL; 704 } 705 706 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 707 { 708 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 709 } 710 711 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 712 { 713 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 714 } 715 716 static int stm32mp1_clk_get_parent(unsigned long id) 717 { 718 const struct stm32mp1_clk_sel *sel; 719 uint32_t p_sel; 720 int i; 721 enum stm32mp1_parent_id p; 722 enum stm32mp1_parent_sel s; 723 uintptr_t rcc_base = stm32mp_rcc_base(); 724 725 /* Few non gateable clock have a static parent ID, find them */ 726 i = (int)clock_id2parent_id(id); 727 if (i != _UNKNOWN_ID) { 728 return i; 729 } 730 731 i = stm32mp1_clk_get_gated_id(id); 732 if (i < 0) { 733 panic(); 734 } 735 736 p = stm32mp1_clk_get_fixed_parent(i); 737 if (p < _PARENT_NB) { 738 return (int)p; 739 } 740 741 s = stm32mp1_clk_get_sel(i); 742 if (s == _UNKNOWN_SEL) { 743 return -EINVAL; 744 } 745 if (s >= _PARENT_SEL_NB) { 746 panic(); 747 } 748 749 sel = clk_sel_ref(s); 750 p_sel = (mmio_read_32(rcc_base + sel->offset) & 751 (sel->msk << sel->src)) >> sel->src; 752 if (p_sel < sel->nb_parent) { 753 return (int)sel->parent[p_sel]; 754 } 755 756 return -EINVAL; 757 } 758 759 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 760 { 761 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 762 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 763 764 return stm32mp1_clk_get_fixed(pll->refclk[src]); 765 } 766 767 /* 768 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 769 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 770 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 771 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 772 */ 773 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 774 { 775 unsigned long refclk, fvco; 776 uint32_t cfgr1, fracr, divm, divn; 777 uintptr_t rcc_base = stm32mp_rcc_base(); 778 779 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 780 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 781 782 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 783 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 784 785 refclk = stm32mp1_pll_get_fref(pll); 786 787 /* 788 * With FRACV : 789 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 790 * Without FRACV 791 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 792 */ 793 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 794 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 795 RCC_PLLNFRACR_FRACV_SHIFT; 796 unsigned long long numerator, denominator; 797 798 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 799 numerator = refclk * numerator; 800 denominator = ((unsigned long long)divm + 1U) << 13; 801 fvco = (unsigned long)(numerator / denominator); 802 } else { 803 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 804 } 805 806 return fvco; 807 } 808 809 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 810 enum stm32mp1_div_id div_id) 811 { 812 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 813 unsigned long dfout; 814 uint32_t cfgr2, divy; 815 816 if (div_id >= _DIV_NB) { 817 return 0; 818 } 819 820 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 821 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 822 823 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 824 825 return dfout; 826 } 827 828 static unsigned long get_clock_rate(int p) 829 { 830 uint32_t reg, clkdiv; 831 unsigned long clock = 0; 832 uintptr_t rcc_base = stm32mp_rcc_base(); 833 834 switch (p) { 835 case _CK_MPU: 836 /* MPU sub system */ 837 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 838 switch (reg & RCC_SELR_SRC_MASK) { 839 case RCC_MPCKSELR_HSI: 840 clock = stm32mp1_clk_get_fixed(_HSI); 841 break; 842 case RCC_MPCKSELR_HSE: 843 clock = stm32mp1_clk_get_fixed(_HSE); 844 break; 845 case RCC_MPCKSELR_PLL: 846 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 847 break; 848 case RCC_MPCKSELR_PLL_MPUDIV: 849 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 850 851 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 852 clkdiv = reg & RCC_MPUDIV_MASK; 853 clock >>= stm32mp1_mpu_div[clkdiv]; 854 break; 855 default: 856 break; 857 } 858 break; 859 /* AXI sub system */ 860 case _ACLK: 861 case _HCLK2: 862 case _HCLK6: 863 case _PCLK4: 864 case _PCLK5: 865 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 866 switch (reg & RCC_SELR_SRC_MASK) { 867 case RCC_ASSCKSELR_HSI: 868 clock = stm32mp1_clk_get_fixed(_HSI); 869 break; 870 case RCC_ASSCKSELR_HSE: 871 clock = stm32mp1_clk_get_fixed(_HSE); 872 break; 873 case RCC_ASSCKSELR_PLL: 874 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 875 break; 876 default: 877 break; 878 } 879 880 /* System clock divider */ 881 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 882 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 883 884 switch (p) { 885 case _PCLK4: 886 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 887 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 888 break; 889 case _PCLK5: 890 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 891 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 892 break; 893 default: 894 break; 895 } 896 break; 897 /* MCU sub system */ 898 case _CK_MCU: 899 case _PCLK1: 900 case _PCLK2: 901 case _PCLK3: 902 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 903 switch (reg & RCC_SELR_SRC_MASK) { 904 case RCC_MSSCKSELR_HSI: 905 clock = stm32mp1_clk_get_fixed(_HSI); 906 break; 907 case RCC_MSSCKSELR_HSE: 908 clock = stm32mp1_clk_get_fixed(_HSE); 909 break; 910 case RCC_MSSCKSELR_CSI: 911 clock = stm32mp1_clk_get_fixed(_CSI); 912 break; 913 case RCC_MSSCKSELR_PLL: 914 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 915 break; 916 default: 917 break; 918 } 919 920 /* MCU clock divider */ 921 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 922 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 923 924 switch (p) { 925 case _PCLK1: 926 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 927 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 928 break; 929 case _PCLK2: 930 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 931 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 932 break; 933 case _PCLK3: 934 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 935 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 936 break; 937 case _CK_MCU: 938 default: 939 break; 940 } 941 break; 942 case _CK_PER: 943 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 944 switch (reg & RCC_SELR_SRC_MASK) { 945 case RCC_CPERCKSELR_HSI: 946 clock = stm32mp1_clk_get_fixed(_HSI); 947 break; 948 case RCC_CPERCKSELR_HSE: 949 clock = stm32mp1_clk_get_fixed(_HSE); 950 break; 951 case RCC_CPERCKSELR_CSI: 952 clock = stm32mp1_clk_get_fixed(_CSI); 953 break; 954 default: 955 break; 956 } 957 break; 958 case _HSI: 959 case _HSI_KER: 960 clock = stm32mp1_clk_get_fixed(_HSI); 961 break; 962 case _CSI: 963 case _CSI_KER: 964 clock = stm32mp1_clk_get_fixed(_CSI); 965 break; 966 case _HSE: 967 case _HSE_KER: 968 clock = stm32mp1_clk_get_fixed(_HSE); 969 break; 970 case _HSE_KER_DIV2: 971 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 972 break; 973 case _HSE_RTC: 974 clock = stm32mp1_clk_get_fixed(_HSE); 975 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 976 break; 977 case _LSI: 978 clock = stm32mp1_clk_get_fixed(_LSI); 979 break; 980 case _LSE: 981 clock = stm32mp1_clk_get_fixed(_LSE); 982 break; 983 /* PLL */ 984 case _PLL1_P: 985 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 986 break; 987 case _PLL1_Q: 988 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 989 break; 990 case _PLL1_R: 991 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 992 break; 993 case _PLL2_P: 994 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 995 break; 996 case _PLL2_Q: 997 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 998 break; 999 case _PLL2_R: 1000 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1001 break; 1002 case _PLL3_P: 1003 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1004 break; 1005 case _PLL3_Q: 1006 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1007 break; 1008 case _PLL3_R: 1009 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1010 break; 1011 case _PLL4_P: 1012 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1013 break; 1014 case _PLL4_Q: 1015 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1016 break; 1017 case _PLL4_R: 1018 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1019 break; 1020 /* Other */ 1021 case _USB_PHY_48: 1022 clock = USB_PHY_48_MHZ; 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 return clock; 1029 } 1030 1031 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1032 { 1033 uintptr_t rcc_base = stm32mp_rcc_base(); 1034 1035 VERBOSE("Enable clock %u\n", gate->index); 1036 1037 if (gate->set_clr != 0U) { 1038 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1039 } else { 1040 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1041 } 1042 } 1043 1044 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1045 { 1046 uintptr_t rcc_base = stm32mp_rcc_base(); 1047 1048 VERBOSE("Disable clock %u\n", gate->index); 1049 1050 if (gate->set_clr != 0U) { 1051 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1052 BIT(gate->bit)); 1053 } else { 1054 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1055 } 1056 } 1057 1058 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1059 { 1060 uintptr_t rcc_base = stm32mp_rcc_base(); 1061 1062 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1063 } 1064 1065 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1066 { 1067 int i = stm32mp1_clk_get_gated_id(id); 1068 1069 if (i < 0) { 1070 panic(); 1071 } 1072 1073 return gate_refcounts[i]; 1074 } 1075 1076 /* Oscillators and PLLs are not gated at runtime */ 1077 static bool clock_is_always_on(unsigned long id) 1078 { 1079 switch (id) { 1080 case CK_HSE: 1081 case CK_CSI: 1082 case CK_LSI: 1083 case CK_LSE: 1084 case CK_HSI: 1085 case CK_HSE_DIV2: 1086 case PLL1_Q: 1087 case PLL1_R: 1088 case PLL2_P: 1089 case PLL2_Q: 1090 case PLL2_R: 1091 case PLL3_P: 1092 case PLL3_Q: 1093 case PLL3_R: 1094 return true; 1095 default: 1096 return false; 1097 } 1098 } 1099 1100 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1101 { 1102 const struct stm32mp1_clk_gate *gate; 1103 int i; 1104 unsigned int *refcnt; 1105 1106 if (clock_is_always_on(id)) { 1107 return; 1108 } 1109 1110 i = stm32mp1_clk_get_gated_id(id); 1111 if (i < 0) { 1112 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 1113 panic(); 1114 } 1115 1116 gate = gate_ref(i); 1117 refcnt = &gate_refcounts[i]; 1118 1119 stm32mp1_clk_lock(&refcount_lock); 1120 1121 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1122 __clk_enable(gate); 1123 } 1124 1125 stm32mp1_clk_unlock(&refcount_lock); 1126 } 1127 1128 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1129 { 1130 const struct stm32mp1_clk_gate *gate; 1131 int i; 1132 unsigned int *refcnt; 1133 1134 if (clock_is_always_on(id)) { 1135 return; 1136 } 1137 1138 i = stm32mp1_clk_get_gated_id(id); 1139 if (i < 0) { 1140 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1141 panic(); 1142 } 1143 1144 gate = gate_ref(i); 1145 refcnt = &gate_refcounts[i]; 1146 1147 stm32mp1_clk_lock(&refcount_lock); 1148 1149 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1150 __clk_disable(gate); 1151 } 1152 1153 stm32mp1_clk_unlock(&refcount_lock); 1154 } 1155 1156 void stm32mp_clk_enable(unsigned long id) 1157 { 1158 __stm32mp1_clk_enable(id, true); 1159 } 1160 1161 void stm32mp_clk_disable(unsigned long id) 1162 { 1163 __stm32mp1_clk_disable(id, true); 1164 } 1165 1166 bool stm32mp_clk_is_enabled(unsigned long id) 1167 { 1168 int i; 1169 1170 if (clock_is_always_on(id)) { 1171 return true; 1172 } 1173 1174 i = stm32mp1_clk_get_gated_id(id); 1175 if (i < 0) { 1176 panic(); 1177 } 1178 1179 return __clk_is_enabled(gate_ref(i)); 1180 } 1181 1182 unsigned long stm32mp_clk_get_rate(unsigned long id) 1183 { 1184 int p = stm32mp1_clk_get_parent(id); 1185 1186 if (p < 0) { 1187 return 0; 1188 } 1189 1190 return get_clock_rate(p); 1191 } 1192 1193 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1194 { 1195 uintptr_t address = stm32mp_rcc_base() + offset; 1196 1197 if (enable) { 1198 mmio_setbits_32(address, mask_on); 1199 } else { 1200 mmio_clrbits_32(address, mask_on); 1201 } 1202 } 1203 1204 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1205 { 1206 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1207 uintptr_t address = stm32mp_rcc_base() + offset; 1208 1209 mmio_write_32(address, mask_on); 1210 } 1211 1212 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1213 { 1214 uint64_t timeout; 1215 uint32_t mask_test; 1216 uintptr_t address = stm32mp_rcc_base() + offset; 1217 1218 if (enable) { 1219 mask_test = mask_rdy; 1220 } else { 1221 mask_test = 0; 1222 } 1223 1224 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1225 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1226 if (timeout_elapsed(timeout)) { 1227 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1228 mask_rdy, address, enable, mmio_read_32(address)); 1229 return -ETIMEDOUT; 1230 } 1231 } 1232 1233 return 0; 1234 } 1235 1236 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1237 { 1238 uint32_t value; 1239 uintptr_t rcc_base = stm32mp_rcc_base(); 1240 1241 if (digbyp) { 1242 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1243 } 1244 1245 if (bypass || digbyp) { 1246 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1247 } 1248 1249 /* 1250 * Warning: not recommended to switch directly from "high drive" 1251 * to "medium low drive", and vice-versa. 1252 */ 1253 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1254 RCC_BDCR_LSEDRV_SHIFT; 1255 1256 while (value != lsedrv) { 1257 if (value > lsedrv) { 1258 value--; 1259 } else { 1260 value++; 1261 } 1262 1263 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1264 RCC_BDCR_LSEDRV_MASK, 1265 value << RCC_BDCR_LSEDRV_SHIFT); 1266 } 1267 1268 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1269 } 1270 1271 static void stm32mp1_lse_wait(void) 1272 { 1273 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1274 VERBOSE("%s: failed\n", __func__); 1275 } 1276 } 1277 1278 static void stm32mp1_lsi_set(bool enable) 1279 { 1280 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1281 1282 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1283 VERBOSE("%s: failed\n", __func__); 1284 } 1285 } 1286 1287 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1288 { 1289 uintptr_t rcc_base = stm32mp_rcc_base(); 1290 1291 if (digbyp) { 1292 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1293 } 1294 1295 if (bypass || digbyp) { 1296 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1297 } 1298 1299 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1300 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1301 VERBOSE("%s: failed\n", __func__); 1302 } 1303 1304 if (css) { 1305 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1306 } 1307 } 1308 1309 static void stm32mp1_csi_set(bool enable) 1310 { 1311 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1312 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1313 VERBOSE("%s: failed\n", __func__); 1314 } 1315 } 1316 1317 static void stm32mp1_hsi_set(bool enable) 1318 { 1319 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1320 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1321 VERBOSE("%s: failed\n", __func__); 1322 } 1323 } 1324 1325 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1326 { 1327 uint64_t timeout; 1328 uintptr_t rcc_base = stm32mp_rcc_base(); 1329 uintptr_t address = rcc_base + RCC_OCRDYR; 1330 1331 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1332 RCC_HSICFGR_HSIDIV_MASK, 1333 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1334 1335 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1336 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1337 if (timeout_elapsed(timeout)) { 1338 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1339 address, mmio_read_32(address)); 1340 return -ETIMEDOUT; 1341 } 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int stm32mp1_hsidiv(unsigned long hsifreq) 1348 { 1349 uint8_t hsidiv; 1350 uint32_t hsidivfreq = MAX_HSI_HZ; 1351 1352 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1353 if (hsidivfreq == hsifreq) { 1354 break; 1355 } 1356 1357 hsidivfreq /= 2U; 1358 } 1359 1360 if (hsidiv == 4U) { 1361 ERROR("Invalid clk-hsi frequency\n"); 1362 return -1; 1363 } 1364 1365 if (hsidiv != 0U) { 1366 return stm32mp1_set_hsidiv(hsidiv); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1373 unsigned int clksrc, 1374 uint32_t *pllcfg, int plloff) 1375 { 1376 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1377 uintptr_t rcc_base = stm32mp_rcc_base(); 1378 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1379 enum stm32mp1_plltype type = pll->plltype; 1380 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1381 unsigned long refclk; 1382 uint32_t ifrge = 0U; 1383 uint32_t src, value, fracv = 0; 1384 void *fdt; 1385 1386 /* Check PLL output */ 1387 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1388 return false; 1389 } 1390 1391 /* Check current clksrc */ 1392 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1393 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1394 return false; 1395 } 1396 1397 /* Check Div */ 1398 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1399 1400 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1401 (pllcfg[PLLCFG_M] + 1U); 1402 1403 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1404 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1405 return false; 1406 } 1407 1408 if ((type == PLL_800) && (refclk >= 8000000U)) { 1409 ifrge = 1U; 1410 } 1411 1412 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1413 RCC_PLLNCFGR1_DIVN_MASK; 1414 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1415 RCC_PLLNCFGR1_DIVM_MASK; 1416 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1417 RCC_PLLNCFGR1_IFRGE_MASK; 1418 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1419 return false; 1420 } 1421 1422 /* Fractional configuration */ 1423 if (fdt_get_address(&fdt) == 1) { 1424 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1425 } 1426 1427 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1428 value |= RCC_PLLNFRACR_FRACLE; 1429 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1430 return false; 1431 } 1432 1433 /* Output config */ 1434 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1435 RCC_PLLNCFGR2_DIVP_MASK; 1436 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1437 RCC_PLLNCFGR2_DIVQ_MASK; 1438 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1439 RCC_PLLNCFGR2_DIVR_MASK; 1440 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1441 return false; 1442 } 1443 1444 return true; 1445 } 1446 1447 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1448 { 1449 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1450 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1451 1452 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1453 mmio_clrsetbits_32(pllxcr, 1454 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1455 RCC_PLLNCR_DIVREN, 1456 RCC_PLLNCR_PLLON); 1457 } 1458 1459 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1460 { 1461 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1462 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1463 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1464 1465 /* Wait PLL lock */ 1466 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1467 if (timeout_elapsed(timeout)) { 1468 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1469 pll_id, pllxcr, mmio_read_32(pllxcr)); 1470 return -ETIMEDOUT; 1471 } 1472 } 1473 1474 /* Start the requested output */ 1475 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1476 1477 return 0; 1478 } 1479 1480 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1481 { 1482 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1483 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1484 uint64_t timeout; 1485 1486 /* Stop all output */ 1487 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1488 RCC_PLLNCR_DIVREN); 1489 1490 /* Stop PLL */ 1491 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1492 1493 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1494 /* Wait PLL stopped */ 1495 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1496 if (timeout_elapsed(timeout)) { 1497 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1498 pll_id, pllxcr, mmio_read_32(pllxcr)); 1499 return -ETIMEDOUT; 1500 } 1501 } 1502 1503 return 0; 1504 } 1505 1506 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1507 uint32_t *pllcfg) 1508 { 1509 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1510 uintptr_t rcc_base = stm32mp_rcc_base(); 1511 uint32_t value; 1512 1513 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1514 RCC_PLLNCFGR2_DIVP_MASK; 1515 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1516 RCC_PLLNCFGR2_DIVQ_MASK; 1517 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1518 RCC_PLLNCFGR2_DIVR_MASK; 1519 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1520 } 1521 1522 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1523 uint32_t *pllcfg, uint32_t fracv) 1524 { 1525 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1526 uintptr_t rcc_base = stm32mp_rcc_base(); 1527 enum stm32mp1_plltype type = pll->plltype; 1528 unsigned long refclk; 1529 uint32_t ifrge = 0; 1530 uint32_t src, value; 1531 1532 src = mmio_read_32(rcc_base + pll->rckxselr) & 1533 RCC_SELR_REFCLK_SRC_MASK; 1534 1535 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1536 (pllcfg[PLLCFG_M] + 1U); 1537 1538 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1539 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1540 return -EINVAL; 1541 } 1542 1543 if ((type == PLL_800) && (refclk >= 8000000U)) { 1544 ifrge = 1U; 1545 } 1546 1547 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1548 RCC_PLLNCFGR1_DIVN_MASK; 1549 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1550 RCC_PLLNCFGR1_DIVM_MASK; 1551 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1552 RCC_PLLNCFGR1_IFRGE_MASK; 1553 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1554 1555 /* Fractional configuration */ 1556 value = 0; 1557 mmio_write_32(rcc_base + pll->pllxfracr, value); 1558 1559 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1560 mmio_write_32(rcc_base + pll->pllxfracr, value); 1561 1562 value |= RCC_PLLNFRACR_FRACLE; 1563 mmio_write_32(rcc_base + pll->pllxfracr, value); 1564 1565 stm32mp1_pll_config_output(pll_id, pllcfg); 1566 1567 return 0; 1568 } 1569 1570 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1571 { 1572 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1573 uint32_t pllxcsg = 0; 1574 1575 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1576 RCC_PLLNCSGR_MOD_PER_MASK; 1577 1578 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1579 RCC_PLLNCSGR_INC_STEP_MASK; 1580 1581 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1582 RCC_PLLNCSGR_SSCG_MODE_MASK; 1583 1584 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1585 1586 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1587 RCC_PLLNCR_SSCG_CTRL); 1588 } 1589 1590 static int stm32mp1_set_clksrc(unsigned int clksrc) 1591 { 1592 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1593 uint64_t timeout; 1594 1595 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1596 clksrc & RCC_SELR_SRC_MASK); 1597 1598 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1599 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1600 if (timeout_elapsed(timeout)) { 1601 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1602 clksrc_address, mmio_read_32(clksrc_address)); 1603 return -ETIMEDOUT; 1604 } 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1611 { 1612 uint64_t timeout; 1613 1614 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1615 clkdiv & RCC_DIVR_DIV_MASK); 1616 1617 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1618 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1619 if (timeout_elapsed(timeout)) { 1620 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1621 clkdiv, address, mmio_read_32(address)); 1622 return -ETIMEDOUT; 1623 } 1624 } 1625 1626 return 0; 1627 } 1628 1629 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1630 { 1631 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1632 1633 /* 1634 * Binding clksrc : 1635 * bit15-4 offset 1636 * bit3: disable 1637 * bit2-0: MCOSEL[2:0] 1638 */ 1639 if ((clksrc & 0x8U) != 0U) { 1640 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1641 } else { 1642 mmio_clrsetbits_32(clksrc_address, 1643 RCC_MCOCFG_MCOSRC_MASK, 1644 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1645 mmio_clrsetbits_32(clksrc_address, 1646 RCC_MCOCFG_MCODIV_MASK, 1647 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1648 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1649 } 1650 } 1651 1652 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1653 { 1654 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1655 1656 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1657 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1658 mmio_clrsetbits_32(address, 1659 RCC_BDCR_RTCSRC_MASK, 1660 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1661 1662 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1663 } 1664 1665 if (lse_css) { 1666 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1667 } 1668 } 1669 1670 static void stm32mp1_stgen_config(void) 1671 { 1672 uint32_t cntfid0; 1673 unsigned long rate; 1674 unsigned long long counter; 1675 1676 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1677 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1678 1679 if (cntfid0 == rate) { 1680 return; 1681 } 1682 1683 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1684 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1685 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1686 counter = (counter * rate / cntfid0); 1687 1688 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1689 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1690 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1691 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1692 1693 write_cntfrq((u_register_t)rate); 1694 1695 /* Need to update timer with new frequency */ 1696 generic_delay_timer_init(); 1697 } 1698 1699 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1700 { 1701 unsigned long long cnt; 1702 1703 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1704 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1705 1706 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1707 1708 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1709 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1710 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1711 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1712 } 1713 1714 static void stm32mp1_pkcs_config(uint32_t pkcs) 1715 { 1716 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1717 uint32_t value = pkcs & 0xFU; 1718 uint32_t mask = 0xFU; 1719 1720 if ((pkcs & BIT(31)) != 0U) { 1721 mask <<= 4; 1722 value <<= 4; 1723 } 1724 1725 mmio_clrsetbits_32(address, mask, value); 1726 } 1727 1728 int stm32mp1_clk_init(void) 1729 { 1730 uintptr_t rcc_base = stm32mp_rcc_base(); 1731 unsigned int clksrc[CLKSRC_NB]; 1732 unsigned int clkdiv[CLKDIV_NB]; 1733 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1734 int plloff[_PLL_NB]; 1735 int ret, len; 1736 enum stm32mp1_pll_id i; 1737 bool lse_css = false; 1738 bool pll3_preserve = false; 1739 bool pll4_preserve = false; 1740 bool pll4_bootrom = false; 1741 const fdt32_t *pkcs_cell; 1742 void *fdt; 1743 1744 if (fdt_get_address(&fdt) == 0) { 1745 return -FDT_ERR_NOTFOUND; 1746 } 1747 1748 /* Check status field to disable security */ 1749 if (!fdt_get_rcc_secure_status()) { 1750 mmio_write_32(rcc_base + RCC_TZCR, 0); 1751 } 1752 1753 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1754 clksrc); 1755 if (ret < 0) { 1756 return -FDT_ERR_NOTFOUND; 1757 } 1758 1759 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1760 clkdiv); 1761 if (ret < 0) { 1762 return -FDT_ERR_NOTFOUND; 1763 } 1764 1765 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1766 char name[12]; 1767 1768 snprintf(name, sizeof(name), "st,pll@%d", i); 1769 plloff[i] = fdt_rcc_subnode_offset(name); 1770 1771 if (!fdt_check_node(plloff[i])) { 1772 continue; 1773 } 1774 1775 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1776 (int)PLLCFG_NB, pllcfg[i]); 1777 if (ret < 0) { 1778 return -FDT_ERR_NOTFOUND; 1779 } 1780 } 1781 1782 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1783 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1784 1785 /* 1786 * Switch ON oscillator found in device-tree. 1787 * Note: HSI already ON after BootROM stage. 1788 */ 1789 if (stm32mp1_osc[_LSI] != 0U) { 1790 stm32mp1_lsi_set(true); 1791 } 1792 if (stm32mp1_osc[_LSE] != 0U) { 1793 bool bypass, digbyp; 1794 uint32_t lsedrv; 1795 1796 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1797 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1798 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1799 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1800 LSEDRV_MEDIUM_HIGH); 1801 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1802 } 1803 if (stm32mp1_osc[_HSE] != 0U) { 1804 bool bypass, digbyp, css; 1805 1806 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1807 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1808 css = fdt_osc_read_bool(_HSE, "st,css"); 1809 stm32mp1_hse_enable(bypass, digbyp, css); 1810 } 1811 /* 1812 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1813 * => switch on CSI even if node is not present in device tree 1814 */ 1815 stm32mp1_csi_set(true); 1816 1817 /* Come back to HSI */ 1818 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1819 if (ret != 0) { 1820 return ret; 1821 } 1822 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1823 if (ret != 0) { 1824 return ret; 1825 } 1826 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1827 if (ret != 0) { 1828 return ret; 1829 } 1830 1831 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1832 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1833 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1834 clksrc[CLKSRC_PLL3], 1835 pllcfg[_PLL3], 1836 plloff[_PLL3]); 1837 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1838 clksrc[CLKSRC_PLL4], 1839 pllcfg[_PLL4], 1840 plloff[_PLL4]); 1841 } 1842 1843 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1844 if (((i == _PLL3) && pll3_preserve) || 1845 ((i == _PLL4) && pll4_preserve)) { 1846 continue; 1847 } 1848 1849 ret = stm32mp1_pll_stop(i); 1850 if (ret != 0) { 1851 return ret; 1852 } 1853 } 1854 1855 /* Configure HSIDIV */ 1856 if (stm32mp1_osc[_HSI] != 0U) { 1857 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1858 if (ret != 0) { 1859 return ret; 1860 } 1861 stm32mp1_stgen_config(); 1862 } 1863 1864 /* Select DIV */ 1865 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1866 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1867 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1868 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1869 if (ret != 0) { 1870 return ret; 1871 } 1872 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1873 if (ret != 0) { 1874 return ret; 1875 } 1876 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1877 if (ret != 0) { 1878 return ret; 1879 } 1880 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1881 if (ret != 0) { 1882 return ret; 1883 } 1884 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1885 if (ret != 0) { 1886 return ret; 1887 } 1888 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1889 if (ret != 0) { 1890 return ret; 1891 } 1892 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1893 if (ret != 0) { 1894 return ret; 1895 } 1896 1897 /* No ready bit for RTC */ 1898 mmio_write_32(rcc_base + RCC_RTCDIVR, 1899 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1900 1901 /* Configure PLLs source */ 1902 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1903 if (ret != 0) { 1904 return ret; 1905 } 1906 1907 if (!pll3_preserve) { 1908 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1909 if (ret != 0) { 1910 return ret; 1911 } 1912 } 1913 1914 if (!pll4_preserve) { 1915 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1916 if (ret != 0) { 1917 return ret; 1918 } 1919 } 1920 1921 /* Configure and start PLLs */ 1922 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1923 uint32_t fracv; 1924 uint32_t csg[PLLCSG_NB]; 1925 1926 if (((i == _PLL3) && pll3_preserve) || 1927 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1928 continue; 1929 } 1930 1931 if (!fdt_check_node(plloff[i])) { 1932 continue; 1933 } 1934 1935 if ((i == _PLL4) && pll4_bootrom) { 1936 /* Set output divider if not done by the Bootrom */ 1937 stm32mp1_pll_config_output(i, pllcfg[i]); 1938 continue; 1939 } 1940 1941 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1942 1943 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1944 if (ret != 0) { 1945 return ret; 1946 } 1947 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 1948 (uint32_t)PLLCSG_NB, csg); 1949 if (ret == 0) { 1950 stm32mp1_pll_csg(i, csg); 1951 } else if (ret != -FDT_ERR_NOTFOUND) { 1952 return ret; 1953 } 1954 1955 stm32mp1_pll_start(i); 1956 } 1957 /* Wait and start PLLs ouptut when ready */ 1958 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1959 if (!fdt_check_node(plloff[i])) { 1960 continue; 1961 } 1962 1963 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1964 if (ret != 0) { 1965 return ret; 1966 } 1967 } 1968 /* Wait LSE ready before to use it */ 1969 if (stm32mp1_osc[_LSE] != 0U) { 1970 stm32mp1_lse_wait(); 1971 } 1972 1973 /* Configure with expected clock source */ 1974 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1975 if (ret != 0) { 1976 return ret; 1977 } 1978 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1979 if (ret != 0) { 1980 return ret; 1981 } 1982 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1983 if (ret != 0) { 1984 return ret; 1985 } 1986 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1987 1988 /* Configure PKCK */ 1989 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1990 if (pkcs_cell != NULL) { 1991 bool ckper_disabled = false; 1992 uint32_t j; 1993 1994 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1995 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1996 1997 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1998 ckper_disabled = true; 1999 continue; 2000 } 2001 stm32mp1_pkcs_config(pkcs); 2002 } 2003 2004 /* 2005 * CKPER is source for some peripheral clocks 2006 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2007 * only if previous clock is still ON 2008 * => deactivated CKPER only after switching clock 2009 */ 2010 if (ckper_disabled) { 2011 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2012 } 2013 } 2014 2015 /* Switch OFF HSI if not found in device-tree */ 2016 if (stm32mp1_osc[_HSI] == 0U) { 2017 stm32mp1_hsi_set(false); 2018 } 2019 stm32mp1_stgen_config(); 2020 2021 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2022 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2023 RCC_DDRITFCR_DDRCKMOD_MASK, 2024 RCC_DDRITFCR_DDRCKMOD_SSR << 2025 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2026 2027 return 0; 2028 } 2029 2030 static void stm32mp1_osc_clk_init(const char *name, 2031 enum stm32mp_osc_id index) 2032 { 2033 uint32_t frequency; 2034 2035 if (fdt_osc_read_freq(name, &frequency) == 0) { 2036 stm32mp1_osc[index] = frequency; 2037 } 2038 } 2039 2040 static void stm32mp1_osc_init(void) 2041 { 2042 enum stm32mp_osc_id i; 2043 2044 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2045 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2046 } 2047 } 2048 2049 #ifdef STM32MP_SHARED_RESOURCES 2050 /* 2051 * Get the parent ID of the target parent clock, for tagging as secure 2052 * shared clock dependencies. 2053 */ 2054 static int get_parent_id_parent(unsigned int parent_id) 2055 { 2056 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2057 enum stm32mp1_pll_id pll_id; 2058 uint32_t p_sel; 2059 uintptr_t rcc_base = stm32mp_rcc_base(); 2060 2061 switch (parent_id) { 2062 case _ACLK: 2063 case _PCLK4: 2064 case _PCLK5: 2065 s = _AXIS_SEL; 2066 break; 2067 case _PLL1_P: 2068 case _PLL1_Q: 2069 case _PLL1_R: 2070 pll_id = _PLL1; 2071 break; 2072 case _PLL2_P: 2073 case _PLL2_Q: 2074 case _PLL2_R: 2075 pll_id = _PLL2; 2076 break; 2077 case _PLL3_P: 2078 case _PLL3_Q: 2079 case _PLL3_R: 2080 pll_id = _PLL3; 2081 break; 2082 case _PLL4_P: 2083 case _PLL4_Q: 2084 case _PLL4_R: 2085 pll_id = _PLL4; 2086 break; 2087 case _PCLK1: 2088 case _PCLK2: 2089 case _HCLK2: 2090 case _HCLK6: 2091 case _CK_PER: 2092 case _CK_MPU: 2093 case _CK_MCU: 2094 case _USB_PHY_48: 2095 /* We do not expect to access these */ 2096 panic(); 2097 break; 2098 default: 2099 /* Other parents have no parent */ 2100 return -1; 2101 } 2102 2103 if (s != _UNKNOWN_SEL) { 2104 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2105 2106 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2107 sel->msk; 2108 2109 if (p_sel < sel->nb_parent) { 2110 return (int)sel->parent[p_sel]; 2111 } 2112 } else { 2113 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2114 2115 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2116 RCC_SELR_REFCLK_SRC_MASK; 2117 2118 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2119 return (int)pll->refclk[p_sel]; 2120 } 2121 } 2122 2123 VERBOSE("No parent selected for %s\n", 2124 stm32mp1_clk_parent_name[parent_id]); 2125 2126 return -1; 2127 } 2128 2129 static void secure_parent_clocks(unsigned long parent_id) 2130 { 2131 int grandparent_id; 2132 2133 switch (parent_id) { 2134 case _PLL3_P: 2135 case _PLL3_Q: 2136 case _PLL3_R: 2137 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2138 break; 2139 2140 /* These clocks are always secure when RCC is secure */ 2141 case _ACLK: 2142 case _HCLK2: 2143 case _HCLK6: 2144 case _PCLK4: 2145 case _PCLK5: 2146 case _PLL1_P: 2147 case _PLL1_Q: 2148 case _PLL1_R: 2149 case _PLL2_P: 2150 case _PLL2_Q: 2151 case _PLL2_R: 2152 case _HSI: 2153 case _HSI_KER: 2154 case _LSI: 2155 case _CSI: 2156 case _CSI_KER: 2157 case _HSE: 2158 case _HSE_KER: 2159 case _HSE_KER_DIV2: 2160 case _HSE_RTC: 2161 case _LSE: 2162 break; 2163 2164 default: 2165 VERBOSE("Cannot secure parent clock %s\n", 2166 stm32mp1_clk_parent_name[parent_id]); 2167 panic(); 2168 } 2169 2170 grandparent_id = get_parent_id_parent(parent_id); 2171 if (grandparent_id >= 0) { 2172 secure_parent_clocks(grandparent_id); 2173 } 2174 } 2175 2176 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2177 { 2178 int parent_id; 2179 2180 if (!stm32mp1_rcc_is_secure()) { 2181 return; 2182 } 2183 2184 switch (clock_id) { 2185 case PLL1: 2186 case PLL2: 2187 /* PLL1/PLL2 are always secure: nothing to do */ 2188 break; 2189 case PLL3: 2190 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2191 break; 2192 case PLL4: 2193 ERROR("PLL4 cannot be secured\n"); 2194 panic(); 2195 break; 2196 default: 2197 /* Others are expected gateable clock */ 2198 parent_id = stm32mp1_clk_get_parent(clock_id); 2199 if (parent_id < 0) { 2200 INFO("No parent found for clock %lu\n", clock_id); 2201 } else { 2202 secure_parent_clocks(parent_id); 2203 } 2204 break; 2205 } 2206 } 2207 #endif /* STM32MP_SHARED_RESOURCES */ 2208 2209 static void sync_earlyboot_clocks_state(void) 2210 { 2211 unsigned int idx; 2212 const unsigned long secure_enable[] = { 2213 AXIDCG, 2214 BSEC, 2215 DDRC1, DDRC1LP, 2216 DDRC2, DDRC2LP, 2217 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2218 DDRPHYC, DDRPHYCLP, 2219 RTCAPB, 2220 TZC1, TZC2, 2221 TZPC, 2222 STGEN_K, 2223 }; 2224 2225 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2226 stm32mp_clk_enable(secure_enable[idx]); 2227 } 2228 } 2229 2230 int stm32mp1_clk_probe(void) 2231 { 2232 stm32mp1_osc_init(); 2233 2234 sync_earlyboot_clocks_state(); 2235 2236 return 0; 2237 } 2238