1 /* 2 * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _PER_SEL, 111 _RTC_SEL, 112 _PARENT_SEL_NB, 113 _UNKNOWN_SEL = 0xff, 114 }; 115 116 /* State the parent clock ID straight related to a clock */ 117 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 118 [_HSE] = CK_HSE, 119 [_HSI] = CK_HSI, 120 [_CSI] = CK_CSI, 121 [_LSE] = CK_LSE, 122 [_LSI] = CK_LSI, 123 [_I2S_CKIN] = _UNKNOWN_ID, 124 [_USB_PHY_48] = _UNKNOWN_ID, 125 [_HSI_KER] = CK_HSI, 126 [_HSE_KER] = CK_HSE, 127 [_HSE_KER_DIV2] = CK_HSE_DIV2, 128 [_CSI_KER] = CK_CSI, 129 [_PLL1_P] = PLL1_P, 130 [_PLL1_Q] = PLL1_Q, 131 [_PLL1_R] = PLL1_R, 132 [_PLL2_P] = PLL2_P, 133 [_PLL2_Q] = PLL2_Q, 134 [_PLL2_R] = PLL2_R, 135 [_PLL3_P] = PLL3_P, 136 [_PLL3_Q] = PLL3_Q, 137 [_PLL3_R] = PLL3_R, 138 [_PLL4_P] = PLL4_P, 139 [_PLL4_Q] = PLL4_Q, 140 [_PLL4_R] = PLL4_R, 141 [_ACLK] = CK_AXI, 142 [_PCLK1] = CK_AXI, 143 [_PCLK2] = CK_AXI, 144 [_PCLK3] = CK_AXI, 145 [_PCLK4] = CK_AXI, 146 [_PCLK5] = CK_AXI, 147 [_CK_PER] = CK_PER, 148 [_CK_MPU] = CK_MPU, 149 [_CK_MCU] = CK_MCU, 150 }; 151 152 static unsigned int clock_id2parent_id(unsigned long id) 153 { 154 unsigned int n; 155 156 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 157 if (parent_id_clock_id[n] == id) { 158 return n; 159 } 160 } 161 162 return _UNKNOWN_ID; 163 } 164 165 enum stm32mp1_pll_id { 166 _PLL1, 167 _PLL2, 168 _PLL3, 169 _PLL4, 170 _PLL_NB 171 }; 172 173 enum stm32mp1_div_id { 174 _DIV_P, 175 _DIV_Q, 176 _DIV_R, 177 _DIV_NB, 178 }; 179 180 enum stm32mp1_clksrc_id { 181 CLKSRC_MPU, 182 CLKSRC_AXI, 183 CLKSRC_MCU, 184 CLKSRC_PLL12, 185 CLKSRC_PLL3, 186 CLKSRC_PLL4, 187 CLKSRC_RTC, 188 CLKSRC_MCO1, 189 CLKSRC_MCO2, 190 CLKSRC_NB 191 }; 192 193 enum stm32mp1_clkdiv_id { 194 CLKDIV_MPU, 195 CLKDIV_AXI, 196 CLKDIV_MCU, 197 CLKDIV_APB1, 198 CLKDIV_APB2, 199 CLKDIV_APB3, 200 CLKDIV_APB4, 201 CLKDIV_APB5, 202 CLKDIV_RTC, 203 CLKDIV_MCO1, 204 CLKDIV_MCO2, 205 CLKDIV_NB 206 }; 207 208 enum stm32mp1_pllcfg { 209 PLLCFG_M, 210 PLLCFG_N, 211 PLLCFG_P, 212 PLLCFG_Q, 213 PLLCFG_R, 214 PLLCFG_O, 215 PLLCFG_NB 216 }; 217 218 enum stm32mp1_pllcsg { 219 PLLCSG_MOD_PER, 220 PLLCSG_INC_STEP, 221 PLLCSG_SSCG_MODE, 222 PLLCSG_NB 223 }; 224 225 enum stm32mp1_plltype { 226 PLL_800, 227 PLL_1600, 228 PLL_TYPE_NB 229 }; 230 231 struct stm32mp1_pll { 232 uint8_t refclk_min; 233 uint8_t refclk_max; 234 uint8_t divn_max; 235 }; 236 237 struct stm32mp1_clk_gate { 238 uint16_t offset; 239 uint8_t bit; 240 uint8_t index; 241 uint8_t set_clr; 242 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 243 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 244 }; 245 246 struct stm32mp1_clk_sel { 247 uint16_t offset; 248 uint8_t src; 249 uint8_t msk; 250 uint8_t nb_parent; 251 const uint8_t *parent; 252 }; 253 254 #define REFCLK_SIZE 4 255 struct stm32mp1_clk_pll { 256 enum stm32mp1_plltype plltype; 257 uint16_t rckxselr; 258 uint16_t pllxcfgr1; 259 uint16_t pllxcfgr2; 260 uint16_t pllxfracr; 261 uint16_t pllxcr; 262 uint16_t pllxcsgr; 263 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 264 }; 265 266 /* Clocks with selectable source and non set/clr register access */ 267 #define _CLK_SELEC(off, b, idx, s) \ 268 { \ 269 .offset = (off), \ 270 .bit = (b), \ 271 .index = (idx), \ 272 .set_clr = 0, \ 273 .sel = (s), \ 274 .fixed = _UNKNOWN_ID, \ 275 } 276 277 /* Clocks with fixed source and non set/clr register access */ 278 #define _CLK_FIXED(off, b, idx, f) \ 279 { \ 280 .offset = (off), \ 281 .bit = (b), \ 282 .index = (idx), \ 283 .set_clr = 0, \ 284 .sel = _UNKNOWN_SEL, \ 285 .fixed = (f), \ 286 } 287 288 /* Clocks with selectable source and set/clr register access */ 289 #define _CLK_SC_SELEC(off, b, idx, s) \ 290 { \ 291 .offset = (off), \ 292 .bit = (b), \ 293 .index = (idx), \ 294 .set_clr = 1, \ 295 .sel = (s), \ 296 .fixed = _UNKNOWN_ID, \ 297 } 298 299 /* Clocks with fixed source and set/clr register access */ 300 #define _CLK_SC_FIXED(off, b, idx, f) \ 301 { \ 302 .offset = (off), \ 303 .bit = (b), \ 304 .index = (idx), \ 305 .set_clr = 1, \ 306 .sel = _UNKNOWN_SEL, \ 307 .fixed = (f), \ 308 } 309 310 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 311 [_ ## _label ## _SEL] = { \ 312 .offset = _rcc_selr, \ 313 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 314 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 315 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 316 .parent = (_parents), \ 317 .nb_parent = ARRAY_SIZE(_parents) \ 318 } 319 320 #define _CLK_PLL(idx, type, off1, off2, off3, \ 321 off4, off5, off6, \ 322 p1, p2, p3, p4) \ 323 [(idx)] = { \ 324 .plltype = (type), \ 325 .rckxselr = (off1), \ 326 .pllxcfgr1 = (off2), \ 327 .pllxcfgr2 = (off3), \ 328 .pllxfracr = (off4), \ 329 .pllxcr = (off5), \ 330 .pllxcsgr = (off6), \ 331 .refclk[0] = (p1), \ 332 .refclk[1] = (p2), \ 333 .refclk[2] = (p3), \ 334 .refclk[3] = (p4), \ 335 } 336 337 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 338 339 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 340 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 341 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 342 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 343 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 344 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 345 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 346 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 347 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 348 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 349 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 350 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 351 352 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 353 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 354 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 363 364 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 365 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 366 367 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 368 369 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 370 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 372 373 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 374 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 377 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 378 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 383 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 384 385 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 386 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 387 388 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 389 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 399 400 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 401 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 403 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 405 406 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 407 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 411 412 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), 413 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 414 }; 415 416 static const uint8_t i2c12_parents[] = { 417 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 418 }; 419 420 static const uint8_t i2c35_parents[] = { 421 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 422 }; 423 424 static const uint8_t stgen_parents[] = { 425 _HSI_KER, _HSE_KER 426 }; 427 428 static const uint8_t i2c46_parents[] = { 429 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 430 }; 431 432 static const uint8_t spi6_parents[] = { 433 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 434 }; 435 436 static const uint8_t usart1_parents[] = { 437 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 438 }; 439 440 static const uint8_t rng1_parents[] = { 441 _CSI, _PLL4_R, _LSE, _LSI 442 }; 443 444 static const uint8_t uart6_parents[] = { 445 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 446 }; 447 448 static const uint8_t uart234578_parents[] = { 449 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 450 }; 451 452 static const uint8_t sdmmc12_parents[] = { 453 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 454 }; 455 456 static const uint8_t sdmmc3_parents[] = { 457 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 458 }; 459 460 static const uint8_t qspi_parents[] = { 461 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 462 }; 463 464 static const uint8_t fmc_parents[] = { 465 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 466 }; 467 468 static const uint8_t ass_parents[] = { 469 _HSI, _HSE, _PLL2 470 }; 471 472 static const uint8_t mss_parents[] = { 473 _HSI, _HSE, _CSI, _PLL3 474 }; 475 476 static const uint8_t usbphy_parents[] = { 477 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 478 }; 479 480 static const uint8_t usbo_parents[] = { 481 _PLL4_R, _USB_PHY_48 482 }; 483 484 static const uint8_t mpu_parents[] = { 485 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 486 }; 487 488 static const uint8_t per_parents[] = { 489 _HSI, _HSE, _CSI, 490 }; 491 492 static const uint8_t rtc_parents[] = { 493 _UNKNOWN_ID, _LSE, _LSI, _HSE 494 }; 495 496 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 497 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 498 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 499 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 500 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 501 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 502 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 503 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 504 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 505 _CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents), 506 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 507 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 508 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 509 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 510 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 511 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 512 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 513 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 514 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 515 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 516 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 517 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 518 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 519 }; 520 521 /* Define characteristic of PLL according type */ 522 #define DIVN_MIN 24 523 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 524 [PLL_800] = { 525 .refclk_min = 4, 526 .refclk_max = 16, 527 .divn_max = 99, 528 }, 529 [PLL_1600] = { 530 .refclk_min = 8, 531 .refclk_max = 16, 532 .divn_max = 199, 533 }, 534 }; 535 536 /* PLLNCFGR2 register divider by output */ 537 static const uint8_t pllncfgr2[_DIV_NB] = { 538 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 539 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 540 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 541 }; 542 543 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 544 _CLK_PLL(_PLL1, PLL_1600, 545 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 546 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 547 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 548 _CLK_PLL(_PLL2, PLL_1600, 549 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 550 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 551 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 552 _CLK_PLL(_PLL3, PLL_800, 553 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 554 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 555 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 556 _CLK_PLL(_PLL4, PLL_800, 557 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 558 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 559 _HSI, _HSE, _CSI, _I2S_CKIN), 560 }; 561 562 /* Prescaler table lookups for clock computation */ 563 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 564 static const uint8_t stm32mp1_mcu_div[16] = { 565 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 566 }; 567 568 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 569 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 570 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 571 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 572 0, 1, 2, 3, 4, 4, 4, 4 573 }; 574 575 /* div = /1 /2 /3 /4 */ 576 static const uint8_t stm32mp1_axi_div[8] = { 577 1, 2, 3, 4, 4, 4, 4, 4 578 }; 579 580 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 581 [_HSI] = "HSI", 582 [_HSE] = "HSE", 583 [_CSI] = "CSI", 584 [_LSI] = "LSI", 585 [_LSE] = "LSE", 586 [_I2S_CKIN] = "I2S_CKIN", 587 [_HSI_KER] = "HSI_KER", 588 [_HSE_KER] = "HSE_KER", 589 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 590 [_CSI_KER] = "CSI_KER", 591 [_PLL1_P] = "PLL1_P", 592 [_PLL1_Q] = "PLL1_Q", 593 [_PLL1_R] = "PLL1_R", 594 [_PLL2_P] = "PLL2_P", 595 [_PLL2_Q] = "PLL2_Q", 596 [_PLL2_R] = "PLL2_R", 597 [_PLL3_P] = "PLL3_P", 598 [_PLL3_Q] = "PLL3_Q", 599 [_PLL3_R] = "PLL3_R", 600 [_PLL4_P] = "PLL4_P", 601 [_PLL4_Q] = "PLL4_Q", 602 [_PLL4_R] = "PLL4_R", 603 [_ACLK] = "ACLK", 604 [_PCLK1] = "PCLK1", 605 [_PCLK2] = "PCLK2", 606 [_PCLK3] = "PCLK3", 607 [_PCLK4] = "PCLK4", 608 [_PCLK5] = "PCLK5", 609 [_HCLK6] = "KCLK6", 610 [_HCLK2] = "HCLK2", 611 [_CK_PER] = "CK_PER", 612 [_CK_MPU] = "CK_MPU", 613 [_CK_MCU] = "CK_MCU", 614 [_USB_PHY_48] = "USB_PHY_48", 615 }; 616 617 /* RCC clock device driver private */ 618 static unsigned long stm32mp1_osc[NB_OSC]; 619 static struct spinlock reg_lock; 620 static unsigned int gate_refcounts[NB_GATES]; 621 static struct spinlock refcount_lock; 622 623 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 624 { 625 return &stm32mp1_clk_gate[idx]; 626 } 627 628 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 629 { 630 return &stm32mp1_clk_sel[idx]; 631 } 632 633 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 634 { 635 return &stm32mp1_clk_pll[idx]; 636 } 637 638 static void stm32mp1_clk_lock(struct spinlock *lock) 639 { 640 if (stm32mp_lock_available()) { 641 /* Assume interrupts are masked */ 642 spin_lock(lock); 643 } 644 } 645 646 static void stm32mp1_clk_unlock(struct spinlock *lock) 647 { 648 if (stm32mp_lock_available()) { 649 spin_unlock(lock); 650 } 651 } 652 653 bool stm32mp1_rcc_is_secure(void) 654 { 655 uintptr_t rcc_base = stm32mp_rcc_base(); 656 uint32_t mask = RCC_TZCR_TZEN; 657 658 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 659 } 660 661 bool stm32mp1_rcc_is_mckprot(void) 662 { 663 uintptr_t rcc_base = stm32mp_rcc_base(); 664 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 665 666 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 667 } 668 669 void stm32mp1_clk_rcc_regs_lock(void) 670 { 671 stm32mp1_clk_lock(®_lock); 672 } 673 674 void stm32mp1_clk_rcc_regs_unlock(void) 675 { 676 stm32mp1_clk_unlock(®_lock); 677 } 678 679 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 680 { 681 if (idx >= NB_OSC) { 682 return 0; 683 } 684 685 return stm32mp1_osc[idx]; 686 } 687 688 static int stm32mp1_clk_get_gated_id(unsigned long id) 689 { 690 unsigned int i; 691 692 for (i = 0U; i < NB_GATES; i++) { 693 if (gate_ref(i)->index == id) { 694 return i; 695 } 696 } 697 698 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 699 700 return -EINVAL; 701 } 702 703 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 704 { 705 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 706 } 707 708 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 709 { 710 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 711 } 712 713 static int stm32mp1_clk_get_parent(unsigned long id) 714 { 715 const struct stm32mp1_clk_sel *sel; 716 uint32_t p_sel; 717 int i; 718 enum stm32mp1_parent_id p; 719 enum stm32mp1_parent_sel s; 720 uintptr_t rcc_base = stm32mp_rcc_base(); 721 722 /* Few non gateable clock have a static parent ID, find them */ 723 i = (int)clock_id2parent_id(id); 724 if (i != _UNKNOWN_ID) { 725 return i; 726 } 727 728 i = stm32mp1_clk_get_gated_id(id); 729 if (i < 0) { 730 panic(); 731 } 732 733 p = stm32mp1_clk_get_fixed_parent(i); 734 if (p < _PARENT_NB) { 735 return (int)p; 736 } 737 738 s = stm32mp1_clk_get_sel(i); 739 if (s == _UNKNOWN_SEL) { 740 return -EINVAL; 741 } 742 if (s >= _PARENT_SEL_NB) { 743 panic(); 744 } 745 746 sel = clk_sel_ref(s); 747 p_sel = (mmio_read_32(rcc_base + sel->offset) & 748 (sel->msk << sel->src)) >> sel->src; 749 if (p_sel < sel->nb_parent) { 750 return (int)sel->parent[p_sel]; 751 } 752 753 return -EINVAL; 754 } 755 756 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 757 { 758 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 759 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 760 761 return stm32mp1_clk_get_fixed(pll->refclk[src]); 762 } 763 764 /* 765 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 766 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 767 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 768 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 769 */ 770 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 771 { 772 unsigned long refclk, fvco; 773 uint32_t cfgr1, fracr, divm, divn; 774 uintptr_t rcc_base = stm32mp_rcc_base(); 775 776 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 777 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 778 779 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 780 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 781 782 refclk = stm32mp1_pll_get_fref(pll); 783 784 /* 785 * With FRACV : 786 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 787 * Without FRACV 788 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 789 */ 790 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 791 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 792 RCC_PLLNFRACR_FRACV_SHIFT; 793 unsigned long long numerator, denominator; 794 795 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 796 numerator = refclk * numerator; 797 denominator = ((unsigned long long)divm + 1U) << 13; 798 fvco = (unsigned long)(numerator / denominator); 799 } else { 800 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 801 } 802 803 return fvco; 804 } 805 806 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 807 enum stm32mp1_div_id div_id) 808 { 809 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 810 unsigned long dfout; 811 uint32_t cfgr2, divy; 812 813 if (div_id >= _DIV_NB) { 814 return 0; 815 } 816 817 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 818 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 819 820 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 821 822 return dfout; 823 } 824 825 static unsigned long get_clock_rate(int p) 826 { 827 uint32_t reg, clkdiv; 828 unsigned long clock = 0; 829 uintptr_t rcc_base = stm32mp_rcc_base(); 830 831 switch (p) { 832 case _CK_MPU: 833 /* MPU sub system */ 834 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 835 switch (reg & RCC_SELR_SRC_MASK) { 836 case RCC_MPCKSELR_HSI: 837 clock = stm32mp1_clk_get_fixed(_HSI); 838 break; 839 case RCC_MPCKSELR_HSE: 840 clock = stm32mp1_clk_get_fixed(_HSE); 841 break; 842 case RCC_MPCKSELR_PLL: 843 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 844 break; 845 case RCC_MPCKSELR_PLL_MPUDIV: 846 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 847 848 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 849 clkdiv = reg & RCC_MPUDIV_MASK; 850 if (clkdiv != 0U) { 851 clock /= stm32mp1_mpu_div[clkdiv]; 852 } 853 break; 854 default: 855 break; 856 } 857 break; 858 /* AXI sub system */ 859 case _ACLK: 860 case _HCLK2: 861 case _HCLK6: 862 case _PCLK4: 863 case _PCLK5: 864 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 865 switch (reg & RCC_SELR_SRC_MASK) { 866 case RCC_ASSCKSELR_HSI: 867 clock = stm32mp1_clk_get_fixed(_HSI); 868 break; 869 case RCC_ASSCKSELR_HSE: 870 clock = stm32mp1_clk_get_fixed(_HSE); 871 break; 872 case RCC_ASSCKSELR_PLL: 873 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 874 break; 875 default: 876 break; 877 } 878 879 /* System clock divider */ 880 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 881 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 882 883 switch (p) { 884 case _PCLK4: 885 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 886 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 887 break; 888 case _PCLK5: 889 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 890 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 891 break; 892 default: 893 break; 894 } 895 break; 896 /* MCU sub system */ 897 case _CK_MCU: 898 case _PCLK1: 899 case _PCLK2: 900 case _PCLK3: 901 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 902 switch (reg & RCC_SELR_SRC_MASK) { 903 case RCC_MSSCKSELR_HSI: 904 clock = stm32mp1_clk_get_fixed(_HSI); 905 break; 906 case RCC_MSSCKSELR_HSE: 907 clock = stm32mp1_clk_get_fixed(_HSE); 908 break; 909 case RCC_MSSCKSELR_CSI: 910 clock = stm32mp1_clk_get_fixed(_CSI); 911 break; 912 case RCC_MSSCKSELR_PLL: 913 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 914 break; 915 default: 916 break; 917 } 918 919 /* MCU clock divider */ 920 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 921 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 922 923 switch (p) { 924 case _PCLK1: 925 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 926 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 927 break; 928 case _PCLK2: 929 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 930 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 931 break; 932 case _PCLK3: 933 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 934 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 935 break; 936 case _CK_MCU: 937 default: 938 break; 939 } 940 break; 941 case _CK_PER: 942 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 943 switch (reg & RCC_SELR_SRC_MASK) { 944 case RCC_CPERCKSELR_HSI: 945 clock = stm32mp1_clk_get_fixed(_HSI); 946 break; 947 case RCC_CPERCKSELR_HSE: 948 clock = stm32mp1_clk_get_fixed(_HSE); 949 break; 950 case RCC_CPERCKSELR_CSI: 951 clock = stm32mp1_clk_get_fixed(_CSI); 952 break; 953 default: 954 break; 955 } 956 break; 957 case _HSI: 958 case _HSI_KER: 959 clock = stm32mp1_clk_get_fixed(_HSI); 960 break; 961 case _CSI: 962 case _CSI_KER: 963 clock = stm32mp1_clk_get_fixed(_CSI); 964 break; 965 case _HSE: 966 case _HSE_KER: 967 clock = stm32mp1_clk_get_fixed(_HSE); 968 break; 969 case _HSE_KER_DIV2: 970 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 971 break; 972 case _LSI: 973 clock = stm32mp1_clk_get_fixed(_LSI); 974 break; 975 case _LSE: 976 clock = stm32mp1_clk_get_fixed(_LSE); 977 break; 978 /* PLL */ 979 case _PLL1_P: 980 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 981 break; 982 case _PLL1_Q: 983 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 984 break; 985 case _PLL1_R: 986 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 987 break; 988 case _PLL2_P: 989 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 990 break; 991 case _PLL2_Q: 992 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 993 break; 994 case _PLL2_R: 995 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 996 break; 997 case _PLL3_P: 998 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 999 break; 1000 case _PLL3_Q: 1001 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1002 break; 1003 case _PLL3_R: 1004 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1005 break; 1006 case _PLL4_P: 1007 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1008 break; 1009 case _PLL4_Q: 1010 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1011 break; 1012 case _PLL4_R: 1013 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1014 break; 1015 /* Other */ 1016 case _USB_PHY_48: 1017 clock = USB_PHY_48_MHZ; 1018 break; 1019 default: 1020 break; 1021 } 1022 1023 return clock; 1024 } 1025 1026 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1027 { 1028 uintptr_t rcc_base = stm32mp_rcc_base(); 1029 1030 VERBOSE("Enable clock %u\n", gate->index); 1031 1032 if (gate->set_clr != 0U) { 1033 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1034 } else { 1035 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1036 } 1037 } 1038 1039 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1040 { 1041 uintptr_t rcc_base = stm32mp_rcc_base(); 1042 1043 VERBOSE("Disable clock %u\n", gate->index); 1044 1045 if (gate->set_clr != 0U) { 1046 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1047 BIT(gate->bit)); 1048 } else { 1049 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1050 } 1051 } 1052 1053 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1054 { 1055 uintptr_t rcc_base = stm32mp_rcc_base(); 1056 1057 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1058 } 1059 1060 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1061 { 1062 int i = stm32mp1_clk_get_gated_id(id); 1063 1064 if (i < 0) { 1065 panic(); 1066 } 1067 1068 return gate_refcounts[i]; 1069 } 1070 1071 /* Oscillators and PLLs are not gated at runtime */ 1072 static bool clock_is_always_on(unsigned long id) 1073 { 1074 switch (id) { 1075 case CK_HSE: 1076 case CK_CSI: 1077 case CK_LSI: 1078 case CK_LSE: 1079 case CK_HSI: 1080 case CK_HSE_DIV2: 1081 case PLL1_Q: 1082 case PLL1_R: 1083 case PLL2_P: 1084 case PLL2_Q: 1085 case PLL2_R: 1086 case PLL3_P: 1087 case PLL3_Q: 1088 case PLL3_R: 1089 return true; 1090 default: 1091 return false; 1092 } 1093 } 1094 1095 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1096 { 1097 const struct stm32mp1_clk_gate *gate; 1098 int i; 1099 unsigned int *refcnt; 1100 1101 if (clock_is_always_on(id)) { 1102 return; 1103 } 1104 1105 i = stm32mp1_clk_get_gated_id(id); 1106 if (i < 0) { 1107 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 1108 panic(); 1109 } 1110 1111 gate = gate_ref(i); 1112 refcnt = &gate_refcounts[i]; 1113 1114 stm32mp1_clk_lock(&refcount_lock); 1115 1116 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1117 __clk_enable(gate); 1118 } 1119 1120 stm32mp1_clk_unlock(&refcount_lock); 1121 } 1122 1123 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1124 { 1125 const struct stm32mp1_clk_gate *gate; 1126 int i; 1127 unsigned int *refcnt; 1128 1129 if (clock_is_always_on(id)) { 1130 return; 1131 } 1132 1133 i = stm32mp1_clk_get_gated_id(id); 1134 if (i < 0) { 1135 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1136 panic(); 1137 } 1138 1139 gate = gate_ref(i); 1140 refcnt = &gate_refcounts[i]; 1141 1142 stm32mp1_clk_lock(&refcount_lock); 1143 1144 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1145 __clk_disable(gate); 1146 } 1147 1148 stm32mp1_clk_unlock(&refcount_lock); 1149 } 1150 1151 void stm32mp_clk_enable(unsigned long id) 1152 { 1153 __stm32mp1_clk_enable(id, true); 1154 } 1155 1156 void stm32mp_clk_disable(unsigned long id) 1157 { 1158 __stm32mp1_clk_disable(id, true); 1159 } 1160 1161 bool stm32mp_clk_is_enabled(unsigned long id) 1162 { 1163 int i; 1164 1165 if (clock_is_always_on(id)) { 1166 return true; 1167 } 1168 1169 i = stm32mp1_clk_get_gated_id(id); 1170 if (i < 0) { 1171 panic(); 1172 } 1173 1174 return __clk_is_enabled(gate_ref(i)); 1175 } 1176 1177 unsigned long stm32mp_clk_get_rate(unsigned long id) 1178 { 1179 int p = stm32mp1_clk_get_parent(id); 1180 1181 if (p < 0) { 1182 return 0; 1183 } 1184 1185 return get_clock_rate(p); 1186 } 1187 1188 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1189 { 1190 uintptr_t address = stm32mp_rcc_base() + offset; 1191 1192 if (enable) { 1193 mmio_setbits_32(address, mask_on); 1194 } else { 1195 mmio_clrbits_32(address, mask_on); 1196 } 1197 } 1198 1199 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1200 { 1201 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1202 uintptr_t address = stm32mp_rcc_base() + offset; 1203 1204 mmio_write_32(address, mask_on); 1205 } 1206 1207 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1208 { 1209 uint64_t timeout; 1210 uint32_t mask_test; 1211 uintptr_t address = stm32mp_rcc_base() + offset; 1212 1213 if (enable) { 1214 mask_test = mask_rdy; 1215 } else { 1216 mask_test = 0; 1217 } 1218 1219 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1220 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1221 if (timeout_elapsed(timeout)) { 1222 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1223 mask_rdy, address, enable, mmio_read_32(address)); 1224 return -ETIMEDOUT; 1225 } 1226 } 1227 1228 return 0; 1229 } 1230 1231 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1232 { 1233 uint32_t value; 1234 uintptr_t rcc_base = stm32mp_rcc_base(); 1235 1236 if (digbyp) { 1237 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1238 } 1239 1240 if (bypass || digbyp) { 1241 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1242 } 1243 1244 /* 1245 * Warning: not recommended to switch directly from "high drive" 1246 * to "medium low drive", and vice-versa. 1247 */ 1248 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1249 RCC_BDCR_LSEDRV_SHIFT; 1250 1251 while (value != lsedrv) { 1252 if (value > lsedrv) { 1253 value--; 1254 } else { 1255 value++; 1256 } 1257 1258 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1259 RCC_BDCR_LSEDRV_MASK, 1260 value << RCC_BDCR_LSEDRV_SHIFT); 1261 } 1262 1263 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1264 } 1265 1266 static void stm32mp1_lse_wait(void) 1267 { 1268 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1269 VERBOSE("%s: failed\n", __func__); 1270 } 1271 } 1272 1273 static void stm32mp1_lsi_set(bool enable) 1274 { 1275 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1276 1277 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1278 VERBOSE("%s: failed\n", __func__); 1279 } 1280 } 1281 1282 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1283 { 1284 uintptr_t rcc_base = stm32mp_rcc_base(); 1285 1286 if (digbyp) { 1287 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1288 } 1289 1290 if (bypass || digbyp) { 1291 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1292 } 1293 1294 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1295 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1296 VERBOSE("%s: failed\n", __func__); 1297 } 1298 1299 if (css) { 1300 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1301 } 1302 } 1303 1304 static void stm32mp1_csi_set(bool enable) 1305 { 1306 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1307 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1308 VERBOSE("%s: failed\n", __func__); 1309 } 1310 } 1311 1312 static void stm32mp1_hsi_set(bool enable) 1313 { 1314 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1315 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1316 VERBOSE("%s: failed\n", __func__); 1317 } 1318 } 1319 1320 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1321 { 1322 uint64_t timeout; 1323 uintptr_t rcc_base = stm32mp_rcc_base(); 1324 uintptr_t address = rcc_base + RCC_OCRDYR; 1325 1326 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1327 RCC_HSICFGR_HSIDIV_MASK, 1328 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1329 1330 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1331 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1332 if (timeout_elapsed(timeout)) { 1333 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1334 address, mmio_read_32(address)); 1335 return -ETIMEDOUT; 1336 } 1337 } 1338 1339 return 0; 1340 } 1341 1342 static int stm32mp1_hsidiv(unsigned long hsifreq) 1343 { 1344 uint8_t hsidiv; 1345 uint32_t hsidivfreq = MAX_HSI_HZ; 1346 1347 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1348 if (hsidivfreq == hsifreq) { 1349 break; 1350 } 1351 1352 hsidivfreq /= 2U; 1353 } 1354 1355 if (hsidiv == 4U) { 1356 ERROR("Invalid clk-hsi frequency\n"); 1357 return -1; 1358 } 1359 1360 if (hsidiv != 0U) { 1361 return stm32mp1_set_hsidiv(hsidiv); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1368 unsigned int clksrc, 1369 uint32_t *pllcfg, int plloff) 1370 { 1371 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1372 uintptr_t rcc_base = stm32mp_rcc_base(); 1373 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1374 enum stm32mp1_plltype type = pll->plltype; 1375 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1376 unsigned long refclk; 1377 uint32_t ifrge = 0U; 1378 uint32_t src, value, fracv = 0; 1379 void *fdt; 1380 1381 /* Check PLL output */ 1382 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1383 return false; 1384 } 1385 1386 /* Check current clksrc */ 1387 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1388 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1389 return false; 1390 } 1391 1392 /* Check Div */ 1393 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1394 1395 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1396 (pllcfg[PLLCFG_M] + 1U); 1397 1398 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1399 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1400 return false; 1401 } 1402 1403 if ((type == PLL_800) && (refclk >= 8000000U)) { 1404 ifrge = 1U; 1405 } 1406 1407 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1408 RCC_PLLNCFGR1_DIVN_MASK; 1409 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1410 RCC_PLLNCFGR1_DIVM_MASK; 1411 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1412 RCC_PLLNCFGR1_IFRGE_MASK; 1413 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1414 return false; 1415 } 1416 1417 /* Fractional configuration */ 1418 if (fdt_get_address(&fdt) == 1) { 1419 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1420 } 1421 1422 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1423 value |= RCC_PLLNFRACR_FRACLE; 1424 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1425 return false; 1426 } 1427 1428 /* Output config */ 1429 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1430 RCC_PLLNCFGR2_DIVP_MASK; 1431 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1432 RCC_PLLNCFGR2_DIVQ_MASK; 1433 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1434 RCC_PLLNCFGR2_DIVR_MASK; 1435 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1436 return false; 1437 } 1438 1439 return true; 1440 } 1441 1442 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1443 { 1444 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1445 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1446 1447 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1448 mmio_clrsetbits_32(pllxcr, 1449 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1450 RCC_PLLNCR_DIVREN, 1451 RCC_PLLNCR_PLLON); 1452 } 1453 1454 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1455 { 1456 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1457 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1458 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1459 1460 /* Wait PLL lock */ 1461 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1462 if (timeout_elapsed(timeout)) { 1463 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1464 pll_id, pllxcr, mmio_read_32(pllxcr)); 1465 return -ETIMEDOUT; 1466 } 1467 } 1468 1469 /* Start the requested output */ 1470 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1471 1472 return 0; 1473 } 1474 1475 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1476 { 1477 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1478 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1479 uint64_t timeout; 1480 1481 /* Stop all output */ 1482 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1483 RCC_PLLNCR_DIVREN); 1484 1485 /* Stop PLL */ 1486 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1487 1488 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1489 /* Wait PLL stopped */ 1490 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1491 if (timeout_elapsed(timeout)) { 1492 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1493 pll_id, pllxcr, mmio_read_32(pllxcr)); 1494 return -ETIMEDOUT; 1495 } 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1502 uint32_t *pllcfg) 1503 { 1504 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1505 uintptr_t rcc_base = stm32mp_rcc_base(); 1506 uint32_t value; 1507 1508 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1509 RCC_PLLNCFGR2_DIVP_MASK; 1510 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1511 RCC_PLLNCFGR2_DIVQ_MASK; 1512 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1513 RCC_PLLNCFGR2_DIVR_MASK; 1514 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1515 } 1516 1517 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1518 uint32_t *pllcfg, uint32_t fracv) 1519 { 1520 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1521 uintptr_t rcc_base = stm32mp_rcc_base(); 1522 enum stm32mp1_plltype type = pll->plltype; 1523 unsigned long refclk; 1524 uint32_t ifrge = 0; 1525 uint32_t src, value; 1526 1527 src = mmio_read_32(rcc_base + pll->rckxselr) & 1528 RCC_SELR_REFCLK_SRC_MASK; 1529 1530 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1531 (pllcfg[PLLCFG_M] + 1U); 1532 1533 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1534 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1535 return -EINVAL; 1536 } 1537 1538 if ((type == PLL_800) && (refclk >= 8000000U)) { 1539 ifrge = 1U; 1540 } 1541 1542 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1543 RCC_PLLNCFGR1_DIVN_MASK; 1544 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1545 RCC_PLLNCFGR1_DIVM_MASK; 1546 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1547 RCC_PLLNCFGR1_IFRGE_MASK; 1548 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1549 1550 /* Fractional configuration */ 1551 value = 0; 1552 mmio_write_32(rcc_base + pll->pllxfracr, value); 1553 1554 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1555 mmio_write_32(rcc_base + pll->pllxfracr, value); 1556 1557 value |= RCC_PLLNFRACR_FRACLE; 1558 mmio_write_32(rcc_base + pll->pllxfracr, value); 1559 1560 stm32mp1_pll_config_output(pll_id, pllcfg); 1561 1562 return 0; 1563 } 1564 1565 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1566 { 1567 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1568 uint32_t pllxcsg = 0; 1569 1570 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1571 RCC_PLLNCSGR_MOD_PER_MASK; 1572 1573 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1574 RCC_PLLNCSGR_INC_STEP_MASK; 1575 1576 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1577 RCC_PLLNCSGR_SSCG_MODE_MASK; 1578 1579 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1580 1581 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1582 RCC_PLLNCR_SSCG_CTRL); 1583 } 1584 1585 static int stm32mp1_set_clksrc(unsigned int clksrc) 1586 { 1587 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1588 uint64_t timeout; 1589 1590 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1591 clksrc & RCC_SELR_SRC_MASK); 1592 1593 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1594 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1595 if (timeout_elapsed(timeout)) { 1596 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1597 clksrc_address, mmio_read_32(clksrc_address)); 1598 return -ETIMEDOUT; 1599 } 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1606 { 1607 uint64_t timeout; 1608 1609 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1610 clkdiv & RCC_DIVR_DIV_MASK); 1611 1612 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1613 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1614 if (timeout_elapsed(timeout)) { 1615 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1616 clkdiv, address, mmio_read_32(address)); 1617 return -ETIMEDOUT; 1618 } 1619 } 1620 1621 return 0; 1622 } 1623 1624 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1625 { 1626 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1627 1628 /* 1629 * Binding clksrc : 1630 * bit15-4 offset 1631 * bit3: disable 1632 * bit2-0: MCOSEL[2:0] 1633 */ 1634 if ((clksrc & 0x8U) != 0U) { 1635 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1636 } else { 1637 mmio_clrsetbits_32(clksrc_address, 1638 RCC_MCOCFG_MCOSRC_MASK, 1639 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1640 mmio_clrsetbits_32(clksrc_address, 1641 RCC_MCOCFG_MCODIV_MASK, 1642 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1643 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1644 } 1645 } 1646 1647 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1648 { 1649 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1650 1651 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1652 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1653 mmio_clrsetbits_32(address, 1654 RCC_BDCR_RTCSRC_MASK, 1655 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1656 1657 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1658 } 1659 1660 if (lse_css) { 1661 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1662 } 1663 } 1664 1665 static void stm32mp1_stgen_config(void) 1666 { 1667 uint32_t cntfid0; 1668 unsigned long rate; 1669 unsigned long long counter; 1670 1671 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1672 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1673 1674 if (cntfid0 == rate) { 1675 return; 1676 } 1677 1678 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1679 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1680 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1681 counter = (counter * rate / cntfid0); 1682 1683 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1684 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1685 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1686 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1687 1688 write_cntfrq((u_register_t)rate); 1689 1690 /* Need to update timer with new frequency */ 1691 generic_delay_timer_init(); 1692 } 1693 1694 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1695 { 1696 unsigned long long cnt; 1697 1698 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1699 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1700 1701 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1702 1703 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1704 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1705 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1706 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1707 } 1708 1709 static void stm32mp1_pkcs_config(uint32_t pkcs) 1710 { 1711 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1712 uint32_t value = pkcs & 0xFU; 1713 uint32_t mask = 0xFU; 1714 1715 if ((pkcs & BIT(31)) != 0U) { 1716 mask <<= 4; 1717 value <<= 4; 1718 } 1719 1720 mmio_clrsetbits_32(address, mask, value); 1721 } 1722 1723 int stm32mp1_clk_init(void) 1724 { 1725 uintptr_t rcc_base = stm32mp_rcc_base(); 1726 unsigned int clksrc[CLKSRC_NB]; 1727 unsigned int clkdiv[CLKDIV_NB]; 1728 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1729 int plloff[_PLL_NB]; 1730 int ret, len; 1731 enum stm32mp1_pll_id i; 1732 bool lse_css = false; 1733 bool pll3_preserve = false; 1734 bool pll4_preserve = false; 1735 bool pll4_bootrom = false; 1736 const fdt32_t *pkcs_cell; 1737 void *fdt; 1738 1739 if (fdt_get_address(&fdt) == 0) { 1740 return false; 1741 } 1742 1743 /* Check status field to disable security */ 1744 if (!fdt_get_rcc_secure_status()) { 1745 mmio_write_32(rcc_base + RCC_TZCR, 0); 1746 } 1747 1748 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1749 clksrc); 1750 if (ret < 0) { 1751 return -FDT_ERR_NOTFOUND; 1752 } 1753 1754 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1755 clkdiv); 1756 if (ret < 0) { 1757 return -FDT_ERR_NOTFOUND; 1758 } 1759 1760 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1761 char name[12]; 1762 1763 snprintf(name, sizeof(name), "st,pll@%d", i); 1764 plloff[i] = fdt_rcc_subnode_offset(name); 1765 1766 if (!fdt_check_node(plloff[i])) { 1767 continue; 1768 } 1769 1770 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1771 (int)PLLCFG_NB, pllcfg[i]); 1772 if (ret < 0) { 1773 return -FDT_ERR_NOTFOUND; 1774 } 1775 } 1776 1777 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1778 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1779 1780 /* 1781 * Switch ON oscillator found in device-tree. 1782 * Note: HSI already ON after BootROM stage. 1783 */ 1784 if (stm32mp1_osc[_LSI] != 0U) { 1785 stm32mp1_lsi_set(true); 1786 } 1787 if (stm32mp1_osc[_LSE] != 0U) { 1788 bool bypass, digbyp; 1789 uint32_t lsedrv; 1790 1791 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1792 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1793 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1794 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1795 LSEDRV_MEDIUM_HIGH); 1796 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1797 } 1798 if (stm32mp1_osc[_HSE] != 0U) { 1799 bool bypass, digbyp, css; 1800 1801 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1802 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1803 css = fdt_osc_read_bool(_HSE, "st,css"); 1804 stm32mp1_hse_enable(bypass, digbyp, css); 1805 } 1806 /* 1807 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1808 * => switch on CSI even if node is not present in device tree 1809 */ 1810 stm32mp1_csi_set(true); 1811 1812 /* Come back to HSI */ 1813 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1814 if (ret != 0) { 1815 return ret; 1816 } 1817 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1818 if (ret != 0) { 1819 return ret; 1820 } 1821 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1822 if (ret != 0) { 1823 return ret; 1824 } 1825 1826 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1827 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1828 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1829 clksrc[CLKSRC_PLL3], 1830 pllcfg[_PLL3], 1831 plloff[_PLL3]); 1832 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1833 clksrc[CLKSRC_PLL4], 1834 pllcfg[_PLL4], 1835 plloff[_PLL4]); 1836 } 1837 1838 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1839 if (((i == _PLL3) && pll3_preserve) || 1840 ((i == _PLL4) && pll4_preserve)) { 1841 continue; 1842 } 1843 1844 ret = stm32mp1_pll_stop(i); 1845 if (ret != 0) { 1846 return ret; 1847 } 1848 } 1849 1850 /* Configure HSIDIV */ 1851 if (stm32mp1_osc[_HSI] != 0U) { 1852 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1853 if (ret != 0) { 1854 return ret; 1855 } 1856 stm32mp1_stgen_config(); 1857 } 1858 1859 /* Select DIV */ 1860 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1861 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1862 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1863 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1864 if (ret != 0) { 1865 return ret; 1866 } 1867 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1868 if (ret != 0) { 1869 return ret; 1870 } 1871 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1872 if (ret != 0) { 1873 return ret; 1874 } 1875 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1876 if (ret != 0) { 1877 return ret; 1878 } 1879 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1880 if (ret != 0) { 1881 return ret; 1882 } 1883 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1884 if (ret != 0) { 1885 return ret; 1886 } 1887 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1888 if (ret != 0) { 1889 return ret; 1890 } 1891 1892 /* No ready bit for RTC */ 1893 mmio_write_32(rcc_base + RCC_RTCDIVR, 1894 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1895 1896 /* Configure PLLs source */ 1897 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1898 if (ret != 0) { 1899 return ret; 1900 } 1901 1902 if (!pll3_preserve) { 1903 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1904 if (ret != 0) { 1905 return ret; 1906 } 1907 } 1908 1909 if (!pll4_preserve) { 1910 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1911 if (ret != 0) { 1912 return ret; 1913 } 1914 } 1915 1916 /* Configure and start PLLs */ 1917 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1918 uint32_t fracv; 1919 uint32_t csg[PLLCSG_NB]; 1920 1921 if (((i == _PLL3) && pll3_preserve) || 1922 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1923 continue; 1924 } 1925 1926 if (!fdt_check_node(plloff[i])) { 1927 continue; 1928 } 1929 1930 if ((i == _PLL4) && pll4_bootrom) { 1931 /* Set output divider if not done by the Bootrom */ 1932 stm32mp1_pll_config_output(i, pllcfg[i]); 1933 continue; 1934 } 1935 1936 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1937 1938 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1939 if (ret != 0) { 1940 return ret; 1941 } 1942 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 1943 (uint32_t)PLLCSG_NB, csg); 1944 if (ret == 0) { 1945 stm32mp1_pll_csg(i, csg); 1946 } else if (ret != -FDT_ERR_NOTFOUND) { 1947 return ret; 1948 } 1949 1950 stm32mp1_pll_start(i); 1951 } 1952 /* Wait and start PLLs ouptut when ready */ 1953 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1954 if (!fdt_check_node(plloff[i])) { 1955 continue; 1956 } 1957 1958 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1959 if (ret != 0) { 1960 return ret; 1961 } 1962 } 1963 /* Wait LSE ready before to use it */ 1964 if (stm32mp1_osc[_LSE] != 0U) { 1965 stm32mp1_lse_wait(); 1966 } 1967 1968 /* Configure with expected clock source */ 1969 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1970 if (ret != 0) { 1971 return ret; 1972 } 1973 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1974 if (ret != 0) { 1975 return ret; 1976 } 1977 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1978 if (ret != 0) { 1979 return ret; 1980 } 1981 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1982 1983 /* Configure PKCK */ 1984 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1985 if (pkcs_cell != NULL) { 1986 bool ckper_disabled = false; 1987 uint32_t j; 1988 1989 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1990 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1991 1992 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1993 ckper_disabled = true; 1994 continue; 1995 } 1996 stm32mp1_pkcs_config(pkcs); 1997 } 1998 1999 /* 2000 * CKPER is source for some peripheral clocks 2001 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2002 * only if previous clock is still ON 2003 * => deactivated CKPER only after switching clock 2004 */ 2005 if (ckper_disabled) { 2006 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2007 } 2008 } 2009 2010 /* Switch OFF HSI if not found in device-tree */ 2011 if (stm32mp1_osc[_HSI] == 0U) { 2012 stm32mp1_hsi_set(false); 2013 } 2014 stm32mp1_stgen_config(); 2015 2016 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2017 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2018 RCC_DDRITFCR_DDRCKMOD_MASK, 2019 RCC_DDRITFCR_DDRCKMOD_SSR << 2020 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2021 2022 return 0; 2023 } 2024 2025 static void stm32mp1_osc_clk_init(const char *name, 2026 enum stm32mp_osc_id index) 2027 { 2028 uint32_t frequency; 2029 2030 if (fdt_osc_read_freq(name, &frequency) == 0) { 2031 stm32mp1_osc[index] = frequency; 2032 } 2033 } 2034 2035 static void stm32mp1_osc_init(void) 2036 { 2037 enum stm32mp_osc_id i; 2038 2039 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2040 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2041 } 2042 } 2043 2044 #ifdef STM32MP_SHARED_RESOURCES 2045 /* 2046 * Get the parent ID of the target parent clock, for tagging as secure 2047 * shared clock dependencies. 2048 */ 2049 static int get_parent_id_parent(unsigned int parent_id) 2050 { 2051 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2052 enum stm32mp1_pll_id pll_id; 2053 uint32_t p_sel; 2054 uintptr_t rcc_base = stm32mp_rcc_base(); 2055 2056 switch (parent_id) { 2057 case _ACLK: 2058 case _PCLK4: 2059 case _PCLK5: 2060 s = _AXIS_SEL; 2061 break; 2062 case _PLL1_P: 2063 case _PLL1_Q: 2064 case _PLL1_R: 2065 pll_id = _PLL1; 2066 break; 2067 case _PLL2_P: 2068 case _PLL2_Q: 2069 case _PLL2_R: 2070 pll_id = _PLL2; 2071 break; 2072 case _PLL3_P: 2073 case _PLL3_Q: 2074 case _PLL3_R: 2075 pll_id = _PLL3; 2076 break; 2077 case _PLL4_P: 2078 case _PLL4_Q: 2079 case _PLL4_R: 2080 pll_id = _PLL4; 2081 break; 2082 case _PCLK1: 2083 case _PCLK2: 2084 case _HCLK2: 2085 case _HCLK6: 2086 case _CK_PER: 2087 case _CK_MPU: 2088 case _CK_MCU: 2089 case _USB_PHY_48: 2090 /* We do not expect to access these */ 2091 panic(); 2092 break; 2093 default: 2094 /* Other parents have no parent */ 2095 return -1; 2096 } 2097 2098 if (s != _UNKNOWN_SEL) { 2099 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2100 2101 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2102 sel->msk; 2103 2104 if (p_sel < sel->nb_parent) { 2105 return (int)sel->parent[p_sel]; 2106 } 2107 } else { 2108 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2109 2110 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2111 RCC_SELR_REFCLK_SRC_MASK; 2112 2113 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2114 return (int)pll->refclk[p_sel]; 2115 } 2116 } 2117 2118 VERBOSE("No parent selected for %s\n", 2119 stm32mp1_clk_parent_name[parent_id]); 2120 2121 return -1; 2122 } 2123 2124 static void secure_parent_clocks(unsigned long parent_id) 2125 { 2126 int grandparent_id; 2127 2128 switch (parent_id) { 2129 case _PLL3_P: 2130 case _PLL3_Q: 2131 case _PLL3_R: 2132 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2133 break; 2134 2135 /* These clocks are always secure when RCC is secure */ 2136 case _ACLK: 2137 case _HCLK2: 2138 case _HCLK6: 2139 case _PCLK4: 2140 case _PCLK5: 2141 case _PLL1_P: 2142 case _PLL1_Q: 2143 case _PLL1_R: 2144 case _PLL2_P: 2145 case _PLL2_Q: 2146 case _PLL2_R: 2147 case _HSI: 2148 case _HSI_KER: 2149 case _LSI: 2150 case _CSI: 2151 case _CSI_KER: 2152 case _HSE: 2153 case _HSE_KER: 2154 case _HSE_KER_DIV2: 2155 case _LSE: 2156 break; 2157 2158 default: 2159 VERBOSE("Cannot secure parent clock %s\n", 2160 stm32mp1_clk_parent_name[parent_id]); 2161 panic(); 2162 } 2163 2164 grandparent_id = get_parent_id_parent(parent_id); 2165 if (grandparent_id >= 0) { 2166 secure_parent_clocks(grandparent_id); 2167 } 2168 } 2169 2170 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2171 { 2172 int parent_id; 2173 2174 if (!stm32mp1_rcc_is_secure()) { 2175 return; 2176 } 2177 2178 switch (clock_id) { 2179 case PLL1: 2180 case PLL2: 2181 /* PLL1/PLL2 are always secure: nothing to do */ 2182 break; 2183 case PLL3: 2184 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2185 break; 2186 case PLL4: 2187 ERROR("PLL4 cannot be secured\n"); 2188 panic(); 2189 break; 2190 default: 2191 /* Others are expected gateable clock */ 2192 parent_id = stm32mp1_clk_get_parent(clock_id); 2193 if (parent_id < 0) { 2194 INFO("No parent found for clock %lu\n", clock_id); 2195 } else { 2196 secure_parent_clocks(parent_id); 2197 } 2198 break; 2199 } 2200 } 2201 #endif /* STM32MP_SHARED_RESOURCES */ 2202 2203 static void sync_earlyboot_clocks_state(void) 2204 { 2205 unsigned int idx; 2206 const unsigned long secure_enable[] = { 2207 AXIDCG, 2208 BSEC, 2209 DDRC1, DDRC1LP, 2210 DDRC2, DDRC2LP, 2211 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2212 DDRPHYC, DDRPHYCLP, 2213 TZC1, TZC2, 2214 TZPC, 2215 STGEN_K, 2216 }; 2217 2218 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2219 stm32mp_clk_enable(secure_enable[idx]); 2220 } 2221 2222 if (!stm32mp_is_single_core()) { 2223 stm32mp1_clk_enable_secure(RTCAPB); 2224 } 2225 } 2226 2227 int stm32mp1_clk_probe(void) 2228 { 2229 stm32mp1_osc_init(); 2230 2231 sync_earlyboot_clocks_state(); 2232 2233 return 0; 2234 } 2235