1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <drivers/delay_timer.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/st/stm32mp_clkfunc.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_rcc.h> 24 #include <dt-bindings/clock/stm32mp1-clksrc.h> 25 #include <lib/mmio.h> 26 #include <lib/spinlock.h> 27 #include <lib/utils_def.h> 28 #include <plat/common/platform.h> 29 30 #define MAX_HSI_HZ 64000000 31 #define USB_PHY_48_MHZ 48000000 32 33 #define TIMEOUT_US_200MS U(200000) 34 #define TIMEOUT_US_1S U(1000000) 35 36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 41 42 const char *stm32mp_osc_node_label[NB_OSC] = { 43 [_LSI] = "clk-lsi", 44 [_LSE] = "clk-lse", 45 [_HSI] = "clk-hsi", 46 [_HSE] = "clk-hse", 47 [_CSI] = "clk-csi", 48 [_I2S_CKIN] = "i2s_ckin", 49 }; 50 51 enum stm32mp1_parent_id { 52 /* Oscillators are defined in enum stm32mp_osc_id */ 53 54 /* Other parent source */ 55 _HSI_KER = NB_OSC, 56 _HSE_KER, 57 _HSE_KER_DIV2, 58 _CSI_KER, 59 _PLL1_P, 60 _PLL1_Q, 61 _PLL1_R, 62 _PLL2_P, 63 _PLL2_Q, 64 _PLL2_R, 65 _PLL3_P, 66 _PLL3_Q, 67 _PLL3_R, 68 _PLL4_P, 69 _PLL4_Q, 70 _PLL4_R, 71 _ACLK, 72 _PCLK1, 73 _PCLK2, 74 _PCLK3, 75 _PCLK4, 76 _PCLK5, 77 _HCLK6, 78 _HCLK2, 79 _CK_PER, 80 _CK_MPU, 81 _CK_MCU, 82 _USB_PHY_48, 83 _PARENT_NB, 84 _UNKNOWN_ID = 0xff, 85 }; 86 87 /* Lists only the parent clock we are interested in */ 88 enum stm32mp1_parent_sel { 89 _I2C12_SEL, 90 _I2C35_SEL, 91 _STGEN_SEL, 92 _I2C46_SEL, 93 _SPI6_SEL, 94 _UART1_SEL, 95 _RNG1_SEL, 96 _UART6_SEL, 97 _UART24_SEL, 98 _UART35_SEL, 99 _UART78_SEL, 100 _SDMMC12_SEL, 101 _SDMMC3_SEL, 102 _QSPI_SEL, 103 _FMC_SEL, 104 _AXIS_SEL, 105 _MCUS_SEL, 106 _USBPHY_SEL, 107 _USBO_SEL, 108 _PARENT_SEL_NB, 109 _UNKNOWN_SEL = 0xff, 110 }; 111 112 enum stm32mp1_pll_id { 113 _PLL1, 114 _PLL2, 115 _PLL3, 116 _PLL4, 117 _PLL_NB 118 }; 119 120 enum stm32mp1_div_id { 121 _DIV_P, 122 _DIV_Q, 123 _DIV_R, 124 _DIV_NB, 125 }; 126 127 enum stm32mp1_clksrc_id { 128 CLKSRC_MPU, 129 CLKSRC_AXI, 130 CLKSRC_MCU, 131 CLKSRC_PLL12, 132 CLKSRC_PLL3, 133 CLKSRC_PLL4, 134 CLKSRC_RTC, 135 CLKSRC_MCO1, 136 CLKSRC_MCO2, 137 CLKSRC_NB 138 }; 139 140 enum stm32mp1_clkdiv_id { 141 CLKDIV_MPU, 142 CLKDIV_AXI, 143 CLKDIV_MCU, 144 CLKDIV_APB1, 145 CLKDIV_APB2, 146 CLKDIV_APB3, 147 CLKDIV_APB4, 148 CLKDIV_APB5, 149 CLKDIV_RTC, 150 CLKDIV_MCO1, 151 CLKDIV_MCO2, 152 CLKDIV_NB 153 }; 154 155 enum stm32mp1_pllcfg { 156 PLLCFG_M, 157 PLLCFG_N, 158 PLLCFG_P, 159 PLLCFG_Q, 160 PLLCFG_R, 161 PLLCFG_O, 162 PLLCFG_NB 163 }; 164 165 enum stm32mp1_pllcsg { 166 PLLCSG_MOD_PER, 167 PLLCSG_INC_STEP, 168 PLLCSG_SSCG_MODE, 169 PLLCSG_NB 170 }; 171 172 enum stm32mp1_plltype { 173 PLL_800, 174 PLL_1600, 175 PLL_TYPE_NB 176 }; 177 178 struct stm32mp1_pll { 179 uint8_t refclk_min; 180 uint8_t refclk_max; 181 uint8_t divn_max; 182 }; 183 184 struct stm32mp1_clk_gate { 185 uint16_t offset; 186 uint8_t bit; 187 uint8_t index; 188 uint8_t set_clr; 189 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 190 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 191 }; 192 193 struct stm32mp1_clk_sel { 194 uint16_t offset; 195 uint8_t src; 196 uint8_t msk; 197 uint8_t nb_parent; 198 const uint8_t *parent; 199 }; 200 201 #define REFCLK_SIZE 4 202 struct stm32mp1_clk_pll { 203 enum stm32mp1_plltype plltype; 204 uint16_t rckxselr; 205 uint16_t pllxcfgr1; 206 uint16_t pllxcfgr2; 207 uint16_t pllxfracr; 208 uint16_t pllxcr; 209 uint16_t pllxcsgr; 210 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 211 }; 212 213 /* Clocks with selectable source and non set/clr register access */ 214 #define _CLK_SELEC(off, b, idx, s) \ 215 { \ 216 .offset = (off), \ 217 .bit = (b), \ 218 .index = (idx), \ 219 .set_clr = 0, \ 220 .sel = (s), \ 221 .fixed = _UNKNOWN_ID, \ 222 } 223 224 /* Clocks with fixed source and non set/clr register access */ 225 #define _CLK_FIXED(off, b, idx, f) \ 226 { \ 227 .offset = (off), \ 228 .bit = (b), \ 229 .index = (idx), \ 230 .set_clr = 0, \ 231 .sel = _UNKNOWN_SEL, \ 232 .fixed = (f), \ 233 } 234 235 /* Clocks with selectable source and set/clr register access */ 236 #define _CLK_SC_SELEC(off, b, idx, s) \ 237 { \ 238 .offset = (off), \ 239 .bit = (b), \ 240 .index = (idx), \ 241 .set_clr = 1, \ 242 .sel = (s), \ 243 .fixed = _UNKNOWN_ID, \ 244 } 245 246 /* Clocks with fixed source and set/clr register access */ 247 #define _CLK_SC_FIXED(off, b, idx, f) \ 248 { \ 249 .offset = (off), \ 250 .bit = (b), \ 251 .index = (idx), \ 252 .set_clr = 1, \ 253 .sel = _UNKNOWN_SEL, \ 254 .fixed = (f), \ 255 } 256 257 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 258 [_ ## _label ## _SEL] = { \ 259 .offset = _rcc_selr, \ 260 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 261 .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \ 262 .parent = (_parents), \ 263 .nb_parent = ARRAY_SIZE(_parents) \ 264 } 265 266 #define _CLK_PLL(idx, type, off1, off2, off3, \ 267 off4, off5, off6, \ 268 p1, p2, p3, p4) \ 269 [(idx)] = { \ 270 .plltype = (type), \ 271 .rckxselr = (off1), \ 272 .pllxcfgr1 = (off2), \ 273 .pllxcfgr2 = (off3), \ 274 .pllxfracr = (off4), \ 275 .pllxcr = (off5), \ 276 .pllxcsgr = (off6), \ 277 .refclk[0] = (p1), \ 278 .refclk[1] = (p2), \ 279 .refclk[2] = (p3), \ 280 .refclk[3] = (p4), \ 281 } 282 283 static const uint8_t stm32mp1_clks[][2] = { 284 { CK_PER, _CK_PER }, 285 { CK_MPU, _CK_MPU }, 286 { CK_AXI, _ACLK }, 287 { CK_MCU, _CK_MCU }, 288 { CK_HSE, _HSE }, 289 { CK_CSI, _CSI }, 290 { CK_LSI, _LSI }, 291 { CK_LSE, _LSE }, 292 { CK_HSI, _HSI }, 293 { CK_HSE_DIV2, _HSE_KER_DIV2 }, 294 }; 295 296 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 297 298 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 299 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 300 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 301 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 302 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 303 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 304 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 305 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 306 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 307 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 308 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 309 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 310 311 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 312 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 313 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 314 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 315 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 316 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 317 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 318 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 319 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 320 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 321 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 322 323 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 324 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 325 326 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 327 328 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 329 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 330 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 331 332 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 333 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 334 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 335 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 336 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 337 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 338 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 339 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 340 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 341 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 342 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 343 344 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 345 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 346 347 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 348 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 349 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 350 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 351 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 352 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 353 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 354 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 355 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 356 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 357 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 358 359 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 360 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 361 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 362 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 363 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 364 365 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 366 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 367 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 368 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 369 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 370 371 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 372 }; 373 374 static const uint8_t i2c12_parents[] = { 375 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 376 }; 377 378 static const uint8_t i2c35_parents[] = { 379 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 380 }; 381 382 static const uint8_t stgen_parents[] = { 383 _HSI_KER, _HSE_KER 384 }; 385 386 static const uint8_t i2c46_parents[] = { 387 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 388 }; 389 390 static const uint8_t spi6_parents[] = { 391 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 392 }; 393 394 static const uint8_t usart1_parents[] = { 395 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 396 }; 397 398 static const uint8_t rng1_parents[] = { 399 _CSI, _PLL4_R, _LSE, _LSI 400 }; 401 402 static const uint8_t uart6_parents[] = { 403 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 404 }; 405 406 static const uint8_t uart234578_parents[] = { 407 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 408 }; 409 410 static const uint8_t sdmmc12_parents[] = { 411 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 412 }; 413 414 static const uint8_t sdmmc3_parents[] = { 415 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 416 }; 417 418 static const uint8_t qspi_parents[] = { 419 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 420 }; 421 422 static const uint8_t fmc_parents[] = { 423 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 424 }; 425 426 static const uint8_t ass_parents[] = { 427 _HSI, _HSE, _PLL2 428 }; 429 430 static const uint8_t mss_parents[] = { 431 _HSI, _HSE, _CSI, _PLL3 432 }; 433 434 static const uint8_t usbphy_parents[] = { 435 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 436 }; 437 438 static const uint8_t usbo_parents[] = { 439 _PLL4_R, _USB_PHY_48 440 }; 441 442 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 443 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 444 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 445 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 446 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 447 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 448 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 449 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 450 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 451 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 452 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 453 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 454 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 455 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 456 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 457 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 458 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 459 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 460 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 461 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 462 }; 463 464 /* Define characteristic of PLL according type */ 465 #define DIVN_MIN 24 466 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 467 [PLL_800] = { 468 .refclk_min = 4, 469 .refclk_max = 16, 470 .divn_max = 99, 471 }, 472 [PLL_1600] = { 473 .refclk_min = 8, 474 .refclk_max = 16, 475 .divn_max = 199, 476 }, 477 }; 478 479 /* PLLNCFGR2 register divider by output */ 480 static const uint8_t pllncfgr2[_DIV_NB] = { 481 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 482 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 483 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 484 }; 485 486 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 487 _CLK_PLL(_PLL1, PLL_1600, 488 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 489 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 490 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 491 _CLK_PLL(_PLL2, PLL_1600, 492 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 493 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 494 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 495 _CLK_PLL(_PLL3, PLL_800, 496 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 497 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 498 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 499 _CLK_PLL(_PLL4, PLL_800, 500 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 501 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 502 _HSI, _HSE, _CSI, _I2S_CKIN), 503 }; 504 505 /* Prescaler table lookups for clock computation */ 506 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 507 static const uint8_t stm32mp1_mcu_div[16] = { 508 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 509 }; 510 511 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 512 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 513 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 514 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 515 0, 1, 2, 3, 4, 4, 4, 4 516 }; 517 518 /* div = /1 /2 /3 /4 */ 519 static const uint8_t stm32mp1_axi_div[8] = { 520 1, 2, 3, 4, 4, 4, 4, 4 521 }; 522 523 /* RCC clock device driver private */ 524 static unsigned long stm32mp1_osc[NB_OSC]; 525 static struct spinlock reg_lock; 526 static unsigned int gate_refcounts[NB_GATES]; 527 static struct spinlock refcount_lock; 528 529 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 530 { 531 return &stm32mp1_clk_gate[idx]; 532 } 533 534 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 535 { 536 return &stm32mp1_clk_sel[idx]; 537 } 538 539 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 540 { 541 return &stm32mp1_clk_pll[idx]; 542 } 543 544 static int stm32mp1_lock_available(void) 545 { 546 /* The spinlocks are used only when MMU is enabled */ 547 return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT); 548 } 549 550 static void stm32mp1_clk_lock(struct spinlock *lock) 551 { 552 if (stm32mp1_lock_available() == 0U) { 553 return; 554 } 555 556 /* Assume interrupts are masked */ 557 spin_lock(lock); 558 } 559 560 static void stm32mp1_clk_unlock(struct spinlock *lock) 561 { 562 if (stm32mp1_lock_available() == 0U) { 563 return; 564 } 565 566 spin_unlock(lock); 567 } 568 569 bool stm32mp1_rcc_is_secure(void) 570 { 571 uintptr_t rcc_base = stm32mp_rcc_base(); 572 573 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 574 } 575 576 bool stm32mp1_rcc_is_mckprot(void) 577 { 578 uintptr_t rcc_base = stm32mp_rcc_base(); 579 580 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 581 } 582 583 void stm32mp1_clk_rcc_regs_lock(void) 584 { 585 stm32mp1_clk_lock(®_lock); 586 } 587 588 void stm32mp1_clk_rcc_regs_unlock(void) 589 { 590 stm32mp1_clk_unlock(®_lock); 591 } 592 593 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 594 { 595 if (idx >= NB_OSC) { 596 return 0; 597 } 598 599 return stm32mp1_osc[idx]; 600 } 601 602 static int stm32mp1_clk_get_gated_id(unsigned long id) 603 { 604 unsigned int i; 605 606 for (i = 0U; i < NB_GATES; i++) { 607 if (gate_ref(i)->index == id) { 608 return i; 609 } 610 } 611 612 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 613 614 return -EINVAL; 615 } 616 617 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 618 { 619 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 620 } 621 622 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 623 { 624 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 625 } 626 627 static int stm32mp1_clk_get_parent(unsigned long id) 628 { 629 const struct stm32mp1_clk_sel *sel; 630 uint32_t j, p_sel; 631 int i; 632 enum stm32mp1_parent_id p; 633 enum stm32mp1_parent_sel s; 634 uintptr_t rcc_base = stm32mp_rcc_base(); 635 636 for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) { 637 if (stm32mp1_clks[j][0] == id) { 638 return (int)stm32mp1_clks[j][1]; 639 } 640 } 641 642 i = stm32mp1_clk_get_gated_id(id); 643 if (i < 0) { 644 panic(); 645 } 646 647 p = stm32mp1_clk_get_fixed_parent(i); 648 if (p < _PARENT_NB) { 649 return (int)p; 650 } 651 652 s = stm32mp1_clk_get_sel(i); 653 if (s == _UNKNOWN_SEL) { 654 return -EINVAL; 655 } 656 if (s >= _PARENT_SEL_NB) { 657 panic(); 658 } 659 660 sel = clk_sel_ref(s); 661 p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src; 662 if (p_sel < sel->nb_parent) { 663 return (int)sel->parent[p_sel]; 664 } 665 666 return -EINVAL; 667 } 668 669 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 670 { 671 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 672 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 673 674 return stm32mp1_clk_get_fixed(pll->refclk[src]); 675 } 676 677 /* 678 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 679 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 680 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 681 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 682 */ 683 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 684 { 685 unsigned long refclk, fvco; 686 uint32_t cfgr1, fracr, divm, divn; 687 uintptr_t rcc_base = stm32mp_rcc_base(); 688 689 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 690 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 691 692 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 693 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 694 695 refclk = stm32mp1_pll_get_fref(pll); 696 697 /* 698 * With FRACV : 699 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 700 * Without FRACV 701 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 702 */ 703 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 704 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 705 RCC_PLLNFRACR_FRACV_SHIFT; 706 unsigned long long numerator, denominator; 707 708 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 709 numerator = refclk * numerator; 710 denominator = ((unsigned long long)divm + 1U) << 13; 711 fvco = (unsigned long)(numerator / denominator); 712 } else { 713 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 714 } 715 716 return fvco; 717 } 718 719 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 720 enum stm32mp1_div_id div_id) 721 { 722 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 723 unsigned long dfout; 724 uint32_t cfgr2, divy; 725 726 if (div_id >= _DIV_NB) { 727 return 0; 728 } 729 730 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 731 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 732 733 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 734 735 return dfout; 736 } 737 738 static unsigned long get_clock_rate(int p) 739 { 740 uint32_t reg, clkdiv; 741 unsigned long clock = 0; 742 uintptr_t rcc_base = stm32mp_rcc_base(); 743 744 switch (p) { 745 case _CK_MPU: 746 /* MPU sub system */ 747 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 748 switch (reg & RCC_SELR_SRC_MASK) { 749 case RCC_MPCKSELR_HSI: 750 clock = stm32mp1_clk_get_fixed(_HSI); 751 break; 752 case RCC_MPCKSELR_HSE: 753 clock = stm32mp1_clk_get_fixed(_HSE); 754 break; 755 case RCC_MPCKSELR_PLL: 756 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 757 break; 758 case RCC_MPCKSELR_PLL_MPUDIV: 759 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 760 761 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 762 clkdiv = reg & RCC_MPUDIV_MASK; 763 if (clkdiv != 0U) { 764 clock /= stm32mp1_mpu_div[clkdiv]; 765 } 766 break; 767 default: 768 break; 769 } 770 break; 771 /* AXI sub system */ 772 case _ACLK: 773 case _HCLK2: 774 case _HCLK6: 775 case _PCLK4: 776 case _PCLK5: 777 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 778 switch (reg & RCC_SELR_SRC_MASK) { 779 case RCC_ASSCKSELR_HSI: 780 clock = stm32mp1_clk_get_fixed(_HSI); 781 break; 782 case RCC_ASSCKSELR_HSE: 783 clock = stm32mp1_clk_get_fixed(_HSE); 784 break; 785 case RCC_ASSCKSELR_PLL: 786 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 787 break; 788 default: 789 break; 790 } 791 792 /* System clock divider */ 793 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 794 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 795 796 switch (p) { 797 case _PCLK4: 798 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 799 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 800 break; 801 case _PCLK5: 802 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 803 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 804 break; 805 default: 806 break; 807 } 808 break; 809 /* MCU sub system */ 810 case _CK_MCU: 811 case _PCLK1: 812 case _PCLK2: 813 case _PCLK3: 814 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 815 switch (reg & RCC_SELR_SRC_MASK) { 816 case RCC_MSSCKSELR_HSI: 817 clock = stm32mp1_clk_get_fixed(_HSI); 818 break; 819 case RCC_MSSCKSELR_HSE: 820 clock = stm32mp1_clk_get_fixed(_HSE); 821 break; 822 case RCC_MSSCKSELR_CSI: 823 clock = stm32mp1_clk_get_fixed(_CSI); 824 break; 825 case RCC_MSSCKSELR_PLL: 826 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 827 break; 828 default: 829 break; 830 } 831 832 /* MCU clock divider */ 833 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 834 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 835 836 switch (p) { 837 case _PCLK1: 838 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 839 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 840 break; 841 case _PCLK2: 842 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 843 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 844 break; 845 case _PCLK3: 846 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 847 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 848 break; 849 case _CK_MCU: 850 default: 851 break; 852 } 853 break; 854 case _CK_PER: 855 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 856 switch (reg & RCC_SELR_SRC_MASK) { 857 case RCC_CPERCKSELR_HSI: 858 clock = stm32mp1_clk_get_fixed(_HSI); 859 break; 860 case RCC_CPERCKSELR_HSE: 861 clock = stm32mp1_clk_get_fixed(_HSE); 862 break; 863 case RCC_CPERCKSELR_CSI: 864 clock = stm32mp1_clk_get_fixed(_CSI); 865 break; 866 default: 867 break; 868 } 869 break; 870 case _HSI: 871 case _HSI_KER: 872 clock = stm32mp1_clk_get_fixed(_HSI); 873 break; 874 case _CSI: 875 case _CSI_KER: 876 clock = stm32mp1_clk_get_fixed(_CSI); 877 break; 878 case _HSE: 879 case _HSE_KER: 880 clock = stm32mp1_clk_get_fixed(_HSE); 881 break; 882 case _HSE_KER_DIV2: 883 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 884 break; 885 case _LSI: 886 clock = stm32mp1_clk_get_fixed(_LSI); 887 break; 888 case _LSE: 889 clock = stm32mp1_clk_get_fixed(_LSE); 890 break; 891 /* PLL */ 892 case _PLL1_P: 893 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 894 break; 895 case _PLL1_Q: 896 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 897 break; 898 case _PLL1_R: 899 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 900 break; 901 case _PLL2_P: 902 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 903 break; 904 case _PLL2_Q: 905 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 906 break; 907 case _PLL2_R: 908 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 909 break; 910 case _PLL3_P: 911 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 912 break; 913 case _PLL3_Q: 914 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 915 break; 916 case _PLL3_R: 917 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 918 break; 919 case _PLL4_P: 920 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 921 break; 922 case _PLL4_Q: 923 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 924 break; 925 case _PLL4_R: 926 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 927 break; 928 /* Other */ 929 case _USB_PHY_48: 930 clock = USB_PHY_48_MHZ; 931 break; 932 default: 933 break; 934 } 935 936 return clock; 937 } 938 939 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 940 { 941 uintptr_t rcc_base = stm32mp_rcc_base(); 942 943 if (gate->set_clr != 0U) { 944 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 945 } else { 946 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 947 } 948 949 VERBOSE("Clock %d has been enabled", gate->index); 950 } 951 952 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 953 { 954 uintptr_t rcc_base = stm32mp_rcc_base(); 955 956 if (gate->set_clr != 0U) { 957 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 958 BIT(gate->bit)); 959 } else { 960 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 961 } 962 963 VERBOSE("Clock %d has been disabled", gate->index); 964 } 965 966 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 967 { 968 uintptr_t rcc_base = stm32mp_rcc_base(); 969 970 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 971 } 972 973 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 974 { 975 int i = stm32mp1_clk_get_gated_id(id); 976 977 if (i < 0) { 978 panic(); 979 } 980 981 return gate_refcounts[i]; 982 } 983 984 void __stm32mp1_clk_enable(unsigned long id, bool secure) 985 { 986 const struct stm32mp1_clk_gate *gate; 987 int i = stm32mp1_clk_get_gated_id(id); 988 unsigned int *refcnt; 989 990 if (i < 0) { 991 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 992 panic(); 993 } 994 995 gate = gate_ref(i); 996 refcnt = &gate_refcounts[i]; 997 998 stm32mp1_clk_lock(&refcount_lock); 999 1000 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1001 __clk_enable(gate); 1002 } 1003 1004 stm32mp1_clk_unlock(&refcount_lock); 1005 } 1006 1007 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1008 { 1009 const struct stm32mp1_clk_gate *gate; 1010 int i = stm32mp1_clk_get_gated_id(id); 1011 unsigned int *refcnt; 1012 1013 if (i < 0) { 1014 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1015 panic(); 1016 } 1017 1018 gate = gate_ref(i); 1019 refcnt = &gate_refcounts[i]; 1020 1021 stm32mp1_clk_lock(&refcount_lock); 1022 1023 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1024 __clk_disable(gate); 1025 } 1026 1027 stm32mp1_clk_unlock(&refcount_lock); 1028 } 1029 1030 void stm32mp_clk_enable(unsigned long id) 1031 { 1032 __stm32mp1_clk_enable(id, true); 1033 } 1034 1035 void stm32mp_clk_disable(unsigned long id) 1036 { 1037 __stm32mp1_clk_disable(id, true); 1038 } 1039 1040 bool stm32mp_clk_is_enabled(unsigned long id) 1041 { 1042 int i = stm32mp1_clk_get_gated_id(id); 1043 1044 if (i < 0) { 1045 panic(); 1046 } 1047 1048 return __clk_is_enabled(gate_ref(i)); 1049 } 1050 1051 unsigned long stm32mp_clk_get_rate(unsigned long id) 1052 { 1053 int p = stm32mp1_clk_get_parent(id); 1054 1055 if (p < 0) { 1056 return 0; 1057 } 1058 1059 return get_clock_rate(p); 1060 } 1061 1062 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1063 { 1064 uintptr_t address = stm32mp_rcc_base() + offset; 1065 1066 if (enable) { 1067 mmio_setbits_32(address, mask_on); 1068 } else { 1069 mmio_clrbits_32(address, mask_on); 1070 } 1071 } 1072 1073 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1074 { 1075 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1076 uintptr_t address = stm32mp_rcc_base() + offset; 1077 1078 mmio_write_32(address, mask_on); 1079 } 1080 1081 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1082 { 1083 uint64_t timeout; 1084 uint32_t mask_test; 1085 uintptr_t address = stm32mp_rcc_base() + offset; 1086 1087 if (enable) { 1088 mask_test = mask_rdy; 1089 } else { 1090 mask_test = 0; 1091 } 1092 1093 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1094 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1095 if (timeout_elapsed(timeout)) { 1096 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1097 mask_rdy, address, enable, mmio_read_32(address)); 1098 return -ETIMEDOUT; 1099 } 1100 } 1101 1102 return 0; 1103 } 1104 1105 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1106 { 1107 uint32_t value; 1108 uintptr_t rcc_base = stm32mp_rcc_base(); 1109 1110 if (digbyp) { 1111 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1112 } 1113 1114 if (bypass || digbyp) { 1115 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1116 } 1117 1118 /* 1119 * Warning: not recommended to switch directly from "high drive" 1120 * to "medium low drive", and vice-versa. 1121 */ 1122 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1123 RCC_BDCR_LSEDRV_SHIFT; 1124 1125 while (value != lsedrv) { 1126 if (value > lsedrv) { 1127 value--; 1128 } else { 1129 value++; 1130 } 1131 1132 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1133 RCC_BDCR_LSEDRV_MASK, 1134 value << RCC_BDCR_LSEDRV_SHIFT); 1135 } 1136 1137 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1138 } 1139 1140 static void stm32mp1_lse_wait(void) 1141 { 1142 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1143 VERBOSE("%s: failed\n", __func__); 1144 } 1145 } 1146 1147 static void stm32mp1_lsi_set(bool enable) 1148 { 1149 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1150 1151 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1152 VERBOSE("%s: failed\n", __func__); 1153 } 1154 } 1155 1156 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1157 { 1158 uintptr_t rcc_base = stm32mp_rcc_base(); 1159 1160 if (digbyp) { 1161 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1162 } 1163 1164 if (bypass || digbyp) { 1165 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1166 } 1167 1168 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1169 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1170 VERBOSE("%s: failed\n", __func__); 1171 } 1172 1173 if (css) { 1174 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1175 } 1176 } 1177 1178 static void stm32mp1_csi_set(bool enable) 1179 { 1180 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1181 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1182 VERBOSE("%s: failed\n", __func__); 1183 } 1184 } 1185 1186 static void stm32mp1_hsi_set(bool enable) 1187 { 1188 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1189 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1190 VERBOSE("%s: failed\n", __func__); 1191 } 1192 } 1193 1194 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1195 { 1196 uint64_t timeout; 1197 uintptr_t rcc_base = stm32mp_rcc_base(); 1198 uintptr_t address = rcc_base + RCC_OCRDYR; 1199 1200 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1201 RCC_HSICFGR_HSIDIV_MASK, 1202 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1203 1204 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1205 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1206 if (timeout_elapsed(timeout)) { 1207 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1208 address, mmio_read_32(address)); 1209 return -ETIMEDOUT; 1210 } 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int stm32mp1_hsidiv(unsigned long hsifreq) 1217 { 1218 uint8_t hsidiv; 1219 uint32_t hsidivfreq = MAX_HSI_HZ; 1220 1221 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1222 if (hsidivfreq == hsifreq) { 1223 break; 1224 } 1225 1226 hsidivfreq /= 2U; 1227 } 1228 1229 if (hsidiv == 4U) { 1230 ERROR("Invalid clk-hsi frequency\n"); 1231 return -1; 1232 } 1233 1234 if (hsidiv != 0U) { 1235 return stm32mp1_set_hsidiv(hsidiv); 1236 } 1237 1238 return 0; 1239 } 1240 1241 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1242 unsigned int clksrc, 1243 uint32_t *pllcfg, int plloff) 1244 { 1245 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1246 uintptr_t rcc_base = stm32mp_rcc_base(); 1247 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1248 enum stm32mp1_plltype type = pll->plltype; 1249 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1250 unsigned long refclk; 1251 uint32_t ifrge = 0U; 1252 uint32_t src, value, fracv; 1253 1254 /* Check PLL output */ 1255 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1256 return false; 1257 } 1258 1259 /* Check current clksrc */ 1260 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1261 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1262 return false; 1263 } 1264 1265 /* Check Div */ 1266 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1267 1268 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1269 (pllcfg[PLLCFG_M] + 1U); 1270 1271 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1272 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1273 return false; 1274 } 1275 1276 if ((type == PLL_800) && (refclk >= 8000000U)) { 1277 ifrge = 1U; 1278 } 1279 1280 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1281 RCC_PLLNCFGR1_DIVN_MASK; 1282 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1283 RCC_PLLNCFGR1_DIVM_MASK; 1284 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1285 RCC_PLLNCFGR1_IFRGE_MASK; 1286 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1287 return false; 1288 } 1289 1290 /* Fractional configuration */ 1291 fracv = fdt_read_uint32_default(plloff, "frac", 0); 1292 1293 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1294 value |= RCC_PLLNFRACR_FRACLE; 1295 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1296 return false; 1297 } 1298 1299 /* Output config */ 1300 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1301 RCC_PLLNCFGR2_DIVP_MASK; 1302 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1303 RCC_PLLNCFGR2_DIVQ_MASK; 1304 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1305 RCC_PLLNCFGR2_DIVR_MASK; 1306 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1307 return false; 1308 } 1309 1310 return true; 1311 } 1312 1313 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1314 { 1315 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1316 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1317 1318 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1319 mmio_clrsetbits_32(pllxcr, 1320 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1321 RCC_PLLNCR_DIVREN, 1322 RCC_PLLNCR_PLLON); 1323 } 1324 1325 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1326 { 1327 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1328 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1329 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1330 1331 /* Wait PLL lock */ 1332 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1333 if (timeout_elapsed(timeout)) { 1334 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1335 pll_id, pllxcr, mmio_read_32(pllxcr)); 1336 return -ETIMEDOUT; 1337 } 1338 } 1339 1340 /* Start the requested output */ 1341 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1342 1343 return 0; 1344 } 1345 1346 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1347 { 1348 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1349 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1350 uint64_t timeout; 1351 1352 /* Stop all output */ 1353 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1354 RCC_PLLNCR_DIVREN); 1355 1356 /* Stop PLL */ 1357 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1358 1359 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1360 /* Wait PLL stopped */ 1361 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1362 if (timeout_elapsed(timeout)) { 1363 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1364 pll_id, pllxcr, mmio_read_32(pllxcr)); 1365 return -ETIMEDOUT; 1366 } 1367 } 1368 1369 return 0; 1370 } 1371 1372 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1373 uint32_t *pllcfg) 1374 { 1375 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1376 uintptr_t rcc_base = stm32mp_rcc_base(); 1377 uint32_t value; 1378 1379 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1380 RCC_PLLNCFGR2_DIVP_MASK; 1381 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1382 RCC_PLLNCFGR2_DIVQ_MASK; 1383 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1384 RCC_PLLNCFGR2_DIVR_MASK; 1385 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1386 } 1387 1388 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1389 uint32_t *pllcfg, uint32_t fracv) 1390 { 1391 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1392 uintptr_t rcc_base = stm32mp_rcc_base(); 1393 enum stm32mp1_plltype type = pll->plltype; 1394 unsigned long refclk; 1395 uint32_t ifrge = 0; 1396 uint32_t src, value; 1397 1398 src = mmio_read_32(rcc_base + pll->rckxselr) & 1399 RCC_SELR_REFCLK_SRC_MASK; 1400 1401 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1402 (pllcfg[PLLCFG_M] + 1U); 1403 1404 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1405 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1406 return -EINVAL; 1407 } 1408 1409 if ((type == PLL_800) && (refclk >= 8000000U)) { 1410 ifrge = 1U; 1411 } 1412 1413 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1414 RCC_PLLNCFGR1_DIVN_MASK; 1415 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1416 RCC_PLLNCFGR1_DIVM_MASK; 1417 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1418 RCC_PLLNCFGR1_IFRGE_MASK; 1419 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1420 1421 /* Fractional configuration */ 1422 value = 0; 1423 mmio_write_32(rcc_base + pll->pllxfracr, value); 1424 1425 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1426 mmio_write_32(rcc_base + pll->pllxfracr, value); 1427 1428 value |= RCC_PLLNFRACR_FRACLE; 1429 mmio_write_32(rcc_base + pll->pllxfracr, value); 1430 1431 stm32mp1_pll_config_output(pll_id, pllcfg); 1432 1433 return 0; 1434 } 1435 1436 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1437 { 1438 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1439 uint32_t pllxcsg = 0; 1440 1441 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1442 RCC_PLLNCSGR_MOD_PER_MASK; 1443 1444 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1445 RCC_PLLNCSGR_INC_STEP_MASK; 1446 1447 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1448 RCC_PLLNCSGR_SSCG_MODE_MASK; 1449 1450 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1451 1452 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1453 RCC_PLLNCR_SSCG_CTRL); 1454 } 1455 1456 static int stm32mp1_set_clksrc(unsigned int clksrc) 1457 { 1458 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1459 uint64_t timeout; 1460 1461 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1462 clksrc & RCC_SELR_SRC_MASK); 1463 1464 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1465 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1466 if (timeout_elapsed(timeout)) { 1467 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1468 clksrc_address, mmio_read_32(clksrc_address)); 1469 return -ETIMEDOUT; 1470 } 1471 } 1472 1473 return 0; 1474 } 1475 1476 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1477 { 1478 uint64_t timeout; 1479 1480 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1481 clkdiv & RCC_DIVR_DIV_MASK); 1482 1483 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1484 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1485 if (timeout_elapsed(timeout)) { 1486 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1487 clkdiv, address, mmio_read_32(address)); 1488 return -ETIMEDOUT; 1489 } 1490 } 1491 1492 return 0; 1493 } 1494 1495 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1496 { 1497 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1498 1499 /* 1500 * Binding clksrc : 1501 * bit15-4 offset 1502 * bit3: disable 1503 * bit2-0: MCOSEL[2:0] 1504 */ 1505 if ((clksrc & 0x8U) != 0U) { 1506 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1507 } else { 1508 mmio_clrsetbits_32(clksrc_address, 1509 RCC_MCOCFG_MCOSRC_MASK, 1510 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1511 mmio_clrsetbits_32(clksrc_address, 1512 RCC_MCOCFG_MCODIV_MASK, 1513 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1514 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1515 } 1516 } 1517 1518 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1519 { 1520 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1521 1522 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1523 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1524 mmio_clrsetbits_32(address, 1525 RCC_BDCR_RTCSRC_MASK, 1526 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1527 1528 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1529 } 1530 1531 if (lse_css) { 1532 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1533 } 1534 } 1535 1536 static void stm32mp1_stgen_config(void) 1537 { 1538 uintptr_t stgen; 1539 uint32_t cntfid0; 1540 unsigned long rate; 1541 unsigned long long counter; 1542 1543 stgen = fdt_get_stgen_base(); 1544 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1545 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1546 1547 if (cntfid0 == rate) { 1548 return; 1549 } 1550 1551 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1552 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1553 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1554 counter = (counter * rate / cntfid0); 1555 1556 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1557 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1558 mmio_write_32(stgen + CNTFID_OFF, rate); 1559 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1560 1561 write_cntfrq((u_register_t)rate); 1562 1563 /* Need to update timer with new frequency */ 1564 generic_delay_timer_init(); 1565 } 1566 1567 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1568 { 1569 uintptr_t stgen; 1570 unsigned long long cnt; 1571 1572 stgen = fdt_get_stgen_base(); 1573 1574 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1575 mmio_read_32(stgen + CNTCVL_OFF); 1576 1577 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1578 1579 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1580 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1581 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1582 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1583 } 1584 1585 static void stm32mp1_pkcs_config(uint32_t pkcs) 1586 { 1587 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1588 uint32_t value = pkcs & 0xFU; 1589 uint32_t mask = 0xFU; 1590 1591 if ((pkcs & BIT(31)) != 0U) { 1592 mask <<= 4; 1593 value <<= 4; 1594 } 1595 1596 mmio_clrsetbits_32(address, mask, value); 1597 } 1598 1599 int stm32mp1_clk_init(void) 1600 { 1601 uintptr_t rcc_base = stm32mp_rcc_base(); 1602 unsigned int clksrc[CLKSRC_NB]; 1603 unsigned int clkdiv[CLKDIV_NB]; 1604 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1605 int plloff[_PLL_NB]; 1606 int ret, len; 1607 enum stm32mp1_pll_id i; 1608 bool lse_css = false; 1609 bool pll3_preserve = false; 1610 bool pll4_preserve = false; 1611 bool pll4_bootrom = false; 1612 const fdt32_t *pkcs_cell; 1613 1614 /* Check status field to disable security */ 1615 if (!fdt_get_rcc_secure_status()) { 1616 mmio_write_32(rcc_base + RCC_TZCR, 0); 1617 } 1618 1619 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1620 (uint32_t)CLKSRC_NB); 1621 if (ret < 0) { 1622 return -FDT_ERR_NOTFOUND; 1623 } 1624 1625 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1626 (uint32_t)CLKDIV_NB); 1627 if (ret < 0) { 1628 return -FDT_ERR_NOTFOUND; 1629 } 1630 1631 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1632 char name[12]; 1633 1634 snprintf(name, sizeof(name), "st,pll@%d", i); 1635 plloff[i] = fdt_rcc_subnode_offset(name); 1636 1637 if (!fdt_check_node(plloff[i])) { 1638 continue; 1639 } 1640 1641 ret = fdt_read_uint32_array(plloff[i], "cfg", 1642 pllcfg[i], (int)PLLCFG_NB); 1643 if (ret < 0) { 1644 return -FDT_ERR_NOTFOUND; 1645 } 1646 } 1647 1648 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1649 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1650 1651 /* 1652 * Switch ON oscillator found in device-tree. 1653 * Note: HSI already ON after BootROM stage. 1654 */ 1655 if (stm32mp1_osc[_LSI] != 0U) { 1656 stm32mp1_lsi_set(true); 1657 } 1658 if (stm32mp1_osc[_LSE] != 0U) { 1659 bool bypass, digbyp; 1660 uint32_t lsedrv; 1661 1662 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1663 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1664 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1665 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1666 LSEDRV_MEDIUM_HIGH); 1667 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1668 } 1669 if (stm32mp1_osc[_HSE] != 0U) { 1670 bool bypass, digbyp, css; 1671 1672 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1673 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1674 css = fdt_osc_read_bool(_HSE, "st,css"); 1675 stm32mp1_hse_enable(bypass, digbyp, css); 1676 } 1677 /* 1678 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1679 * => switch on CSI even if node is not present in device tree 1680 */ 1681 stm32mp1_csi_set(true); 1682 1683 /* Come back to HSI */ 1684 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1685 if (ret != 0) { 1686 return ret; 1687 } 1688 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1689 if (ret != 0) { 1690 return ret; 1691 } 1692 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1693 if (ret != 0) { 1694 return ret; 1695 } 1696 1697 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1698 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1699 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1700 clksrc[CLKSRC_PLL3], 1701 pllcfg[_PLL3], 1702 plloff[_PLL3]); 1703 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1704 clksrc[CLKSRC_PLL4], 1705 pllcfg[_PLL4], 1706 plloff[_PLL4]); 1707 } 1708 1709 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1710 if (((i == _PLL3) && pll3_preserve) || 1711 ((i == _PLL4) && pll4_preserve)) { 1712 continue; 1713 } 1714 1715 ret = stm32mp1_pll_stop(i); 1716 if (ret != 0) { 1717 return ret; 1718 } 1719 } 1720 1721 /* Configure HSIDIV */ 1722 if (stm32mp1_osc[_HSI] != 0U) { 1723 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1724 if (ret != 0) { 1725 return ret; 1726 } 1727 stm32mp1_stgen_config(); 1728 } 1729 1730 /* Select DIV */ 1731 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1732 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1733 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1734 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1735 if (ret != 0) { 1736 return ret; 1737 } 1738 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1739 if (ret != 0) { 1740 return ret; 1741 } 1742 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1743 if (ret != 0) { 1744 return ret; 1745 } 1746 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1747 if (ret != 0) { 1748 return ret; 1749 } 1750 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1751 if (ret != 0) { 1752 return ret; 1753 } 1754 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1755 if (ret != 0) { 1756 return ret; 1757 } 1758 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1759 if (ret != 0) { 1760 return ret; 1761 } 1762 1763 /* No ready bit for RTC */ 1764 mmio_write_32(rcc_base + RCC_RTCDIVR, 1765 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1766 1767 /* Configure PLLs source */ 1768 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1769 if (ret != 0) { 1770 return ret; 1771 } 1772 1773 if (!pll3_preserve) { 1774 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1775 if (ret != 0) { 1776 return ret; 1777 } 1778 } 1779 1780 if (!pll4_preserve) { 1781 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1782 if (ret != 0) { 1783 return ret; 1784 } 1785 } 1786 1787 /* Configure and start PLLs */ 1788 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1789 uint32_t fracv; 1790 uint32_t csg[PLLCSG_NB]; 1791 1792 if (((i == _PLL3) && pll3_preserve) || 1793 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1794 continue; 1795 } 1796 1797 if (!fdt_check_node(plloff[i])) { 1798 continue; 1799 } 1800 1801 if ((i == _PLL4) && pll4_bootrom) { 1802 /* Set output divider if not done by the Bootrom */ 1803 stm32mp1_pll_config_output(i, pllcfg[i]); 1804 continue; 1805 } 1806 1807 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1808 1809 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1810 if (ret != 0) { 1811 return ret; 1812 } 1813 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1814 (uint32_t)PLLCSG_NB); 1815 if (ret == 0) { 1816 stm32mp1_pll_csg(i, csg); 1817 } else if (ret != -FDT_ERR_NOTFOUND) { 1818 return ret; 1819 } 1820 1821 stm32mp1_pll_start(i); 1822 } 1823 /* Wait and start PLLs ouptut when ready */ 1824 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1825 if (!fdt_check_node(plloff[i])) { 1826 continue; 1827 } 1828 1829 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1830 if (ret != 0) { 1831 return ret; 1832 } 1833 } 1834 /* Wait LSE ready before to use it */ 1835 if (stm32mp1_osc[_LSE] != 0U) { 1836 stm32mp1_lse_wait(); 1837 } 1838 1839 /* Configure with expected clock source */ 1840 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1841 if (ret != 0) { 1842 return ret; 1843 } 1844 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1845 if (ret != 0) { 1846 return ret; 1847 } 1848 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1849 if (ret != 0) { 1850 return ret; 1851 } 1852 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1853 1854 /* Configure PKCK */ 1855 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1856 if (pkcs_cell != NULL) { 1857 bool ckper_disabled = false; 1858 uint32_t j; 1859 1860 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1861 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1862 1863 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1864 ckper_disabled = true; 1865 continue; 1866 } 1867 stm32mp1_pkcs_config(pkcs); 1868 } 1869 1870 /* 1871 * CKPER is source for some peripheral clocks 1872 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1873 * only if previous clock is still ON 1874 * => deactivated CKPER only after switching clock 1875 */ 1876 if (ckper_disabled) { 1877 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 1878 } 1879 } 1880 1881 /* Switch OFF HSI if not found in device-tree */ 1882 if (stm32mp1_osc[_HSI] == 0U) { 1883 stm32mp1_hsi_set(false); 1884 } 1885 stm32mp1_stgen_config(); 1886 1887 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1888 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 1889 RCC_DDRITFCR_DDRCKMOD_MASK, 1890 RCC_DDRITFCR_DDRCKMOD_SSR << 1891 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1892 1893 return 0; 1894 } 1895 1896 static void stm32mp1_osc_clk_init(const char *name, 1897 enum stm32mp_osc_id index) 1898 { 1899 uint32_t frequency; 1900 1901 if (fdt_osc_read_freq(name, &frequency) == 0) { 1902 stm32mp1_osc[index] = frequency; 1903 } 1904 } 1905 1906 static void stm32mp1_osc_init(void) 1907 { 1908 enum stm32mp_osc_id i; 1909 1910 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1911 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 1912 } 1913 } 1914 1915 int stm32mp1_clk_probe(void) 1916 { 1917 stm32mp1_osc_init(); 1918 1919 return 0; 1920 } 1921