1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/clock/stm32mp1-clksrc.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <libfdt.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <stdint.h> 20 #include <stdio.h> 21 #include <stm32mp1_clk.h> 22 #include <stm32mp1_clkfunc.h> 23 #include <stm32mp1_dt.h> 24 #include <stm32mp1_private.h> 25 #include <stm32mp1_rcc.h> 26 #include <utils_def.h> 27 28 #define MAX_HSI_HZ 64000000 29 30 #define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U) 31 #define TIMEOUT_1S plat_get_syscnt_freq2() 32 33 #define PLLRDY_TIMEOUT TIMEOUT_200MS 34 #define CLKSRC_TIMEOUT TIMEOUT_200MS 35 #define CLKDIV_TIMEOUT TIMEOUT_200MS 36 #define HSIDIV_TIMEOUT TIMEOUT_200MS 37 #define OSCRDY_TIMEOUT TIMEOUT_1S 38 39 enum stm32mp1_parent_id { 40 /* Oscillators are defined in enum stm32mp_osc_id */ 41 42 /* Other parent source */ 43 _HSI_KER = NB_OSC, 44 _HSE_KER, 45 _HSE_KER_DIV2, 46 _CSI_KER, 47 _PLL1_P, 48 _PLL1_Q, 49 _PLL1_R, 50 _PLL2_P, 51 _PLL2_Q, 52 _PLL2_R, 53 _PLL3_P, 54 _PLL3_Q, 55 _PLL3_R, 56 _PLL4_P, 57 _PLL4_Q, 58 _PLL4_R, 59 _ACLK, 60 _PCLK1, 61 _PCLK2, 62 _PCLK3, 63 _PCLK4, 64 _PCLK5, 65 _HCLK6, 66 _HCLK2, 67 _CK_PER, 68 _CK_MPU, 69 _PARENT_NB, 70 _UNKNOWN_ID = 0xff, 71 }; 72 73 enum stm32mp1_parent_sel { 74 _I2C46_SEL, 75 _UART6_SEL, 76 _UART24_SEL, 77 _UART35_SEL, 78 _UART78_SEL, 79 _SDMMC12_SEL, 80 _SDMMC3_SEL, 81 _QSPI_SEL, 82 _FMC_SEL, 83 _USBPHY_SEL, 84 _USBO_SEL, 85 _STGEN_SEL, 86 _PARENT_SEL_NB, 87 _UNKNOWN_SEL = 0xff, 88 }; 89 90 enum stm32mp1_pll_id { 91 _PLL1, 92 _PLL2, 93 _PLL3, 94 _PLL4, 95 _PLL_NB 96 }; 97 98 enum stm32mp1_div_id { 99 _DIV_P, 100 _DIV_Q, 101 _DIV_R, 102 _DIV_NB, 103 }; 104 105 enum stm32mp1_clksrc_id { 106 CLKSRC_MPU, 107 CLKSRC_AXI, 108 CLKSRC_PLL12, 109 CLKSRC_PLL3, 110 CLKSRC_PLL4, 111 CLKSRC_RTC, 112 CLKSRC_MCO1, 113 CLKSRC_MCO2, 114 CLKSRC_NB 115 }; 116 117 enum stm32mp1_clkdiv_id { 118 CLKDIV_MPU, 119 CLKDIV_AXI, 120 CLKDIV_APB1, 121 CLKDIV_APB2, 122 CLKDIV_APB3, 123 CLKDIV_APB4, 124 CLKDIV_APB5, 125 CLKDIV_RTC, 126 CLKDIV_MCO1, 127 CLKDIV_MCO2, 128 CLKDIV_NB 129 }; 130 131 enum stm32mp1_pllcfg { 132 PLLCFG_M, 133 PLLCFG_N, 134 PLLCFG_P, 135 PLLCFG_Q, 136 PLLCFG_R, 137 PLLCFG_O, 138 PLLCFG_NB 139 }; 140 141 enum stm32mp1_pllcsg { 142 PLLCSG_MOD_PER, 143 PLLCSG_INC_STEP, 144 PLLCSG_SSCG_MODE, 145 PLLCSG_NB 146 }; 147 148 enum stm32mp1_plltype { 149 PLL_800, 150 PLL_1600, 151 PLL_TYPE_NB 152 }; 153 154 struct stm32mp1_pll { 155 uint8_t refclk_min; 156 uint8_t refclk_max; 157 uint8_t divn_max; 158 }; 159 160 struct stm32mp1_clk_gate { 161 uint16_t offset; 162 uint8_t bit; 163 uint8_t index; 164 uint8_t set_clr; 165 enum stm32mp1_parent_sel sel; 166 enum stm32mp1_parent_id fixed; 167 bool secure; 168 }; 169 170 struct stm32mp1_clk_sel { 171 uint16_t offset; 172 uint8_t src; 173 uint8_t msk; 174 uint8_t nb_parent; 175 const uint8_t *parent; 176 }; 177 178 #define REFCLK_SIZE 4 179 struct stm32mp1_clk_pll { 180 enum stm32mp1_plltype plltype; 181 uint16_t rckxselr; 182 uint16_t pllxcfgr1; 183 uint16_t pllxcfgr2; 184 uint16_t pllxfracr; 185 uint16_t pllxcr; 186 uint16_t pllxcsgr; 187 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 188 }; 189 190 struct stm32mp1_clk_data { 191 const struct stm32mp1_clk_gate *gate; 192 const struct stm32mp1_clk_sel *sel; 193 const struct stm32mp1_clk_pll *pll; 194 const int nb_gate; 195 }; 196 197 struct stm32mp1_clk_priv { 198 uint32_t base; 199 const struct stm32mp1_clk_data *data; 200 unsigned long osc[NB_OSC]; 201 uint32_t pkcs_usb_value; 202 }; 203 204 #define STM32MP1_CLK(off, b, idx, s) \ 205 { \ 206 .offset = (off), \ 207 .bit = (b), \ 208 .index = (idx), \ 209 .set_clr = 0, \ 210 .sel = (s), \ 211 .fixed = _UNKNOWN_ID, \ 212 .secure = 0, \ 213 } 214 215 #define STM32MP1_CLK_F(off, b, idx, f) \ 216 { \ 217 .offset = (off), \ 218 .bit = (b), \ 219 .index = (idx), \ 220 .set_clr = 0, \ 221 .sel = _UNKNOWN_SEL, \ 222 .fixed = (f), \ 223 .secure = 0, \ 224 } 225 226 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 227 { \ 228 .offset = (off), \ 229 .bit = (b), \ 230 .index = (idx), \ 231 .set_clr = 1, \ 232 .sel = (s), \ 233 .fixed = _UNKNOWN_ID, \ 234 .secure = 0, \ 235 } 236 237 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 238 { \ 239 .offset = (off), \ 240 .bit = (b), \ 241 .index = (idx), \ 242 .set_clr = 1, \ 243 .sel = _UNKNOWN_SEL, \ 244 .fixed = (f), \ 245 .secure = 0, \ 246 } 247 248 #define STM32MP1_CLK_SEC_SET_CLR(off, b, idx, s) \ 249 { \ 250 .offset = (off), \ 251 .bit = (b), \ 252 .index = (idx), \ 253 .set_clr = 1, \ 254 .sel = (s), \ 255 .fixed = _UNKNOWN_ID, \ 256 .secure = 1, \ 257 } 258 259 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 260 [(idx)] = { \ 261 .offset = (off), \ 262 .src = (s), \ 263 .msk = (m), \ 264 .parent = (p), \ 265 .nb_parent = ARRAY_SIZE((p)) \ 266 } 267 268 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, \ 269 off4, off5, off6, \ 270 p1, p2, p3, p4) \ 271 [(idx)] = { \ 272 .plltype = (type), \ 273 .rckxselr = (off1), \ 274 .pllxcfgr1 = (off2), \ 275 .pllxcfgr2 = (off3), \ 276 .pllxfracr = (off4), \ 277 .pllxcr = (off5), \ 278 .pllxcsgr = (off6), \ 279 .refclk[0] = (p1), \ 280 .refclk[1] = (p2), \ 281 .refclk[2] = (p3), \ 282 .refclk[3] = (p4), \ 283 } 284 285 static const uint8_t stm32mp1_clks[][2] = { 286 {CK_PER, _CK_PER}, 287 {CK_MPU, _CK_MPU}, 288 {CK_AXI, _ACLK}, 289 {CK_HSE, _HSE}, 290 {CK_CSI, _CSI}, 291 {CK_LSI, _LSI}, 292 {CK_LSE, _LSE}, 293 {CK_HSI, _HSI}, 294 {CK_HSE_DIV2, _HSE_KER_DIV2}, 295 }; 296 297 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 298 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 299 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 300 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 301 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 302 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 303 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 304 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 305 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 306 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 307 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 308 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 309 310 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 311 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 312 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 313 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 314 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 315 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 316 317 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 318 319 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 320 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 321 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 322 323 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 324 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 325 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 11, TZC1, _UNKNOWN_SEL), 326 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 12, TZC2, _UNKNOWN_SEL), 327 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 328 329 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 330 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 331 332 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 333 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 334 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 335 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 336 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 337 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 338 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 339 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 340 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 341 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 342 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 343 344 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 345 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 5, HASH1, _UNKNOWN_SEL), 346 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _CSI_KER), 347 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _UNKNOWN_SEL), 348 349 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 350 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 351 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 352 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 353 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 354 355 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 356 }; 357 358 static const uint8_t i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 359 static const uint8_t uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 360 _HSE_KER}; 361 static const uint8_t uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 362 _HSE_KER}; 363 static const uint8_t uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 364 _HSE_KER}; 365 static const uint8_t uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 366 _HSE_KER}; 367 static const uint8_t sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 368 static const uint8_t sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 369 static const uint8_t qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 370 static const uint8_t fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 371 static const uint8_t usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 372 static const uint8_t usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 373 static const uint8_t stgen_parents[] = {_HSI_KER, _HSE_KER}; 374 375 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 376 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 377 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 378 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 379 uart24_parents), 380 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 381 uart35_parents), 382 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 383 uart78_parents), 384 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 385 sdmmc12_parents), 386 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 387 sdmmc3_parents), 388 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 389 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 390 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 391 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 392 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 393 }; 394 395 /* Define characteristic of PLL according type */ 396 #define DIVN_MIN 24 397 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 398 [PLL_800] = { 399 .refclk_min = 4, 400 .refclk_max = 16, 401 .divn_max = 99, 402 }, 403 [PLL_1600] = { 404 .refclk_min = 8, 405 .refclk_max = 16, 406 .divn_max = 199, 407 }, 408 }; 409 410 /* PLLNCFGR2 register divider by output */ 411 static const uint8_t pllncfgr2[_DIV_NB] = { 412 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 413 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 414 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT 415 }; 416 417 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 418 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 419 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 420 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 421 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 422 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 423 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 424 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 425 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 426 STM32MP1_CLK_PLL(_PLL3, PLL_800, 427 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 428 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 429 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 430 STM32MP1_CLK_PLL(_PLL4, PLL_800, 431 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 432 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 433 _HSI, _HSE, _CSI, _I2S_CKIN), 434 }; 435 436 /* Prescaler table lookups for clock computation */ 437 438 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 439 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 440 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 441 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 442 0, 1, 2, 3, 4, 4, 4, 4 443 }; 444 445 /* div = /1 /2 /3 /4 */ 446 static const uint8_t stm32mp1_axi_div[8] = { 447 1, 2, 3, 4, 4, 4, 4, 4 448 }; 449 450 static const struct stm32mp1_clk_data stm32mp1_data = { 451 .gate = stm32mp1_clk_gate, 452 .sel = stm32mp1_clk_sel, 453 .pll = stm32mp1_clk_pll, 454 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 455 }; 456 457 static struct stm32mp1_clk_priv stm32mp1_clk_priv_data; 458 459 static unsigned long stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, 460 enum stm32mp_osc_id idx) 461 { 462 if (idx >= NB_OSC) { 463 return 0; 464 } 465 466 return priv->osc[idx]; 467 } 468 469 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 470 { 471 const struct stm32mp1_clk_gate *gate = priv->data->gate; 472 int i; 473 int nb_clks = priv->data->nb_gate; 474 475 for (i = 0; i < nb_clks; i++) { 476 if (gate[i].index == id) { 477 return i; 478 } 479 } 480 481 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 482 483 return -EINVAL; 484 } 485 486 static enum stm32mp1_parent_sel 487 stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, int i) 488 { 489 const struct stm32mp1_clk_gate *gate = priv->data->gate; 490 491 return gate[i].sel; 492 } 493 494 static enum stm32mp1_parent_id 495 stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, int i) 496 { 497 const struct stm32mp1_clk_gate *gate = priv->data->gate; 498 499 return gate[i].fixed; 500 } 501 502 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 503 unsigned long id) 504 { 505 const struct stm32mp1_clk_sel *sel = priv->data->sel; 506 uint32_t j, p_sel; 507 int i; 508 enum stm32mp1_parent_id p; 509 enum stm32mp1_parent_sel s; 510 511 for (j = 0; j < ARRAY_SIZE(stm32mp1_clks); j++) { 512 if (stm32mp1_clks[j][0] == id) { 513 return (int)stm32mp1_clks[j][1]; 514 } 515 } 516 517 i = stm32mp1_clk_get_id(priv, id); 518 if (i < 0) { 519 return i; 520 } 521 522 p = stm32mp1_clk_get_fixed_parent(priv, i); 523 if (p < _PARENT_NB) { 524 return (int)p; 525 } 526 527 s = stm32mp1_clk_get_sel(priv, i); 528 if (s >= _PARENT_SEL_NB) { 529 return -EINVAL; 530 } 531 532 p_sel = (mmio_read_32(priv->base + sel[s].offset) >> sel[s].src) & 533 sel[s].msk; 534 535 if (p_sel < sel[s].nb_parent) { 536 return (int)sel[s].parent[p_sel]; 537 } 538 539 ERROR("%s: no parents defined for clk id %ld\n", __func__, id); 540 541 return -EINVAL; 542 } 543 544 static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv, 545 enum stm32mp1_pll_id pll_id) 546 { 547 const struct stm32mp1_clk_pll *pll = priv->data->pll; 548 uint32_t selr, src; 549 unsigned long refclk; 550 551 selr = mmio_read_32(priv->base + pll[pll_id].rckxselr); 552 src = selr & RCC_SELR_REFCLK_SRC_MASK; 553 554 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 555 556 return refclk; 557 } 558 559 /* 560 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 561 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 562 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 563 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 564 */ 565 static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, 566 enum stm32mp1_pll_id pll_id) 567 { 568 const struct stm32mp1_clk_pll *pll = priv->data->pll; 569 unsigned long refclk, fvco; 570 uint32_t cfgr1, fracr, divm, divn; 571 572 cfgr1 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr1); 573 fracr = mmio_read_32(priv->base + pll[pll_id].pllxfracr); 574 575 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 576 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 577 578 refclk = stm32mp1_pll_get_fref_ck(priv, pll_id); 579 580 /* 581 * With FRACV : 582 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 583 * Without FRACV 584 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 585 */ 586 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 587 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 588 >> RCC_PLLNFRACR_FRACV_SHIFT; 589 unsigned long long numerator, denominator; 590 591 numerator = ((unsigned long long)divn + 1U) << 13; 592 numerator = (refclk * numerator) + fracv; 593 denominator = ((unsigned long long)divm + 1U) << 13; 594 fvco = (unsigned long)(numerator / denominator); 595 } else { 596 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 597 } 598 599 return fvco; 600 } 601 602 static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 603 enum stm32mp1_pll_id pll_id, 604 enum stm32mp1_div_id div_id) 605 { 606 const struct stm32mp1_clk_pll *pll = priv->data->pll; 607 unsigned long dfout; 608 uint32_t cfgr2, divy; 609 610 if (div_id >= _DIV_NB) { 611 return 0; 612 } 613 614 cfgr2 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr2); 615 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 616 617 dfout = stm32mp1_pll_get_fvco(priv, pll_id) / (divy + 1U); 618 619 return dfout; 620 } 621 622 static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 623 { 624 uint32_t reg, clkdiv; 625 unsigned long clock = 0; 626 627 switch (p) { 628 case _CK_MPU: 629 /* MPU sub system */ 630 reg = mmio_read_32(priv->base + RCC_MPCKSELR); 631 switch (reg & RCC_SELR_SRC_MASK) { 632 case RCC_MPCKSELR_HSI: 633 clock = stm32mp1_clk_get_fixed(priv, _HSI); 634 break; 635 case RCC_MPCKSELR_HSE: 636 clock = stm32mp1_clk_get_fixed(priv, _HSE); 637 break; 638 case RCC_MPCKSELR_PLL: 639 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 640 break; 641 case RCC_MPCKSELR_PLL_MPUDIV: 642 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 643 644 reg = mmio_read_32(priv->base + RCC_MPCKDIVR); 645 clkdiv = reg & RCC_MPUDIV_MASK; 646 if (clkdiv != 0U) { 647 clock /= stm32mp1_mpu_div[clkdiv]; 648 } 649 650 break; 651 default: 652 break; 653 } 654 break; 655 /* AXI sub system */ 656 case _ACLK: 657 case _HCLK2: 658 case _HCLK6: 659 case _PCLK4: 660 case _PCLK5: 661 reg = mmio_read_32(priv->base + RCC_ASSCKSELR); 662 switch (reg & RCC_SELR_SRC_MASK) { 663 case RCC_ASSCKSELR_HSI: 664 clock = stm32mp1_clk_get_fixed(priv, _HSI); 665 break; 666 case RCC_ASSCKSELR_HSE: 667 clock = stm32mp1_clk_get_fixed(priv, _HSE); 668 break; 669 case RCC_ASSCKSELR_PLL: 670 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 671 break; 672 default: 673 break; 674 } 675 676 /* System clock divider */ 677 reg = mmio_read_32(priv->base + RCC_AXIDIVR); 678 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 679 680 switch (p) { 681 case _PCLK4: 682 reg = mmio_read_32(priv->base + RCC_APB4DIVR); 683 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 684 break; 685 case _PCLK5: 686 reg = mmio_read_32(priv->base + RCC_APB5DIVR); 687 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 688 break; 689 default: 690 break; 691 } 692 break; 693 case _CK_PER: 694 reg = mmio_read_32(priv->base + RCC_CPERCKSELR); 695 switch (reg & RCC_SELR_SRC_MASK) { 696 case RCC_CPERCKSELR_HSI: 697 clock = stm32mp1_clk_get_fixed(priv, _HSI); 698 break; 699 case RCC_CPERCKSELR_HSE: 700 clock = stm32mp1_clk_get_fixed(priv, _HSE); 701 break; 702 case RCC_CPERCKSELR_CSI: 703 clock = stm32mp1_clk_get_fixed(priv, _CSI); 704 break; 705 default: 706 break; 707 } 708 break; 709 case _HSI: 710 case _HSI_KER: 711 clock = stm32mp1_clk_get_fixed(priv, _HSI); 712 break; 713 case _CSI: 714 case _CSI_KER: 715 clock = stm32mp1_clk_get_fixed(priv, _CSI); 716 break; 717 case _HSE: 718 case _HSE_KER: 719 clock = stm32mp1_clk_get_fixed(priv, _HSE); 720 break; 721 case _HSE_KER_DIV2: 722 clock = stm32mp1_clk_get_fixed(priv, _HSE) >> 1; 723 break; 724 case _LSI: 725 clock = stm32mp1_clk_get_fixed(priv, _LSI); 726 break; 727 case _LSE: 728 clock = stm32mp1_clk_get_fixed(priv, _LSE); 729 break; 730 /* PLL */ 731 case _PLL1_P: 732 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 733 break; 734 case _PLL1_Q: 735 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_Q); 736 break; 737 case _PLL1_R: 738 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_R); 739 break; 740 case _PLL2_P: 741 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 742 break; 743 case _PLL2_Q: 744 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_Q); 745 break; 746 case _PLL2_R: 747 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_R); 748 break; 749 case _PLL3_P: 750 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 751 break; 752 case _PLL3_Q: 753 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_Q); 754 break; 755 case _PLL3_R: 756 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_R); 757 break; 758 case _PLL4_P: 759 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_P); 760 break; 761 case _PLL4_Q: 762 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_Q); 763 break; 764 case _PLL4_R: 765 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_R); 766 break; 767 /* Other */ 768 case _USB_PHY_48: 769 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 770 break; 771 default: 772 break; 773 } 774 775 return clock; 776 } 777 778 bool stm32mp1_clk_is_enabled(unsigned long id) 779 { 780 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 781 const struct stm32mp1_clk_gate *gate = priv->data->gate; 782 int i = stm32mp1_clk_get_id(priv, id); 783 784 if (i < 0) { 785 return false; 786 } 787 788 return ((mmio_read_32(priv->base + gate[i].offset) & 789 BIT(gate[i].bit)) != 0U); 790 } 791 792 int stm32mp1_clk_enable(unsigned long id) 793 { 794 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 795 const struct stm32mp1_clk_gate *gate = priv->data->gate; 796 int i = stm32mp1_clk_get_id(priv, id); 797 798 if (i < 0) { 799 return i; 800 } 801 802 if (gate[i].set_clr != 0U) { 803 mmio_write_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 804 } else { 805 mmio_setbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 806 } 807 808 return 0; 809 } 810 811 int stm32mp1_clk_disable(unsigned long id) 812 { 813 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 814 const struct stm32mp1_clk_gate *gate = priv->data->gate; 815 int i = stm32mp1_clk_get_id(priv, id); 816 817 if (i < 0) { 818 return i; 819 } 820 821 if (gate[i].set_clr != 0U) { 822 mmio_write_32(priv->base + gate[i].offset 823 + RCC_MP_ENCLRR_OFFSET, 824 BIT(gate[i].bit)); 825 } else { 826 mmio_clrbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); 827 } 828 829 return 0; 830 } 831 832 unsigned long stm32mp1_clk_get_rate(unsigned long id) 833 { 834 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 835 int p = stm32mp1_clk_get_parent(priv, id); 836 unsigned long rate; 837 838 if (p < 0) { 839 return 0; 840 } 841 842 rate = stm32mp1_clk_get(priv, p); 843 844 return rate; 845 } 846 847 static void stm32mp1_ls_osc_set(int enable, uint32_t rcc, uint32_t offset, 848 uint32_t mask_on) 849 { 850 uint32_t address = rcc + offset; 851 852 if (enable != 0) { 853 mmio_setbits_32(address, mask_on); 854 } else { 855 mmio_clrbits_32(address, mask_on); 856 } 857 } 858 859 static void stm32mp1_hs_ocs_set(int enable, uint32_t rcc, uint32_t mask_on) 860 { 861 if (enable != 0) { 862 mmio_setbits_32(rcc + RCC_OCENSETR, mask_on); 863 } else { 864 mmio_setbits_32(rcc + RCC_OCENCLRR, mask_on); 865 } 866 } 867 868 static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, 869 uint32_t mask_rdy) 870 { 871 unsigned long start; 872 uint32_t mask_test; 873 uint32_t address = rcc + offset; 874 875 if (enable != 0) { 876 mask_test = mask_rdy; 877 } else { 878 mask_test = 0; 879 } 880 881 start = get_timer(0); 882 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 883 if (get_timer(start) > OSCRDY_TIMEOUT) { 884 ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n", 885 mask_rdy, address, enable, mmio_read_32(address)); 886 return -ETIMEDOUT; 887 } 888 } 889 890 return 0; 891 } 892 893 static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv) 894 { 895 uint32_t value; 896 897 if (bypass) { 898 mmio_setbits_32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 899 } 900 901 /* 902 * Warning: not recommended to switch directly from "high drive" 903 * to "medium low drive", and vice-versa. 904 */ 905 value = (mmio_read_32(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 906 RCC_BDCR_LSEDRV_SHIFT; 907 908 while (value != lsedrv) { 909 if (value > lsedrv) { 910 value--; 911 } else { 912 value++; 913 } 914 915 mmio_clrsetbits_32(rcc + RCC_BDCR, 916 RCC_BDCR_LSEDRV_MASK, 917 value << RCC_BDCR_LSEDRV_SHIFT); 918 } 919 920 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 921 } 922 923 static void stm32mp1_lse_wait(uint32_t rcc) 924 { 925 if (stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 926 VERBOSE("%s: failed\n", __func__); 927 } 928 } 929 930 static void stm32mp1_lsi_set(uint32_t rcc, int enable) 931 { 932 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 933 if (stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 934 0) { 935 VERBOSE("%s: failed\n", __func__); 936 } 937 } 938 939 static void stm32mp1_hse_enable(uint32_t rcc, bool bypass, bool css) 940 { 941 if (bypass) { 942 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 943 } 944 945 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 946 if (stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 947 0) { 948 VERBOSE("%s: failed\n", __func__); 949 } 950 951 if (css) { 952 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 953 } 954 } 955 956 static void stm32mp1_csi_set(uint32_t rcc, int enable) 957 { 958 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 959 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 960 0) { 961 VERBOSE("%s: failed\n", __func__); 962 } 963 } 964 965 static void stm32mp1_hsi_set(uint32_t rcc, int enable) 966 { 967 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 968 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 969 0) { 970 VERBOSE("%s: failed\n", __func__); 971 } 972 } 973 974 static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) 975 { 976 unsigned long start; 977 uint32_t address = rcc + RCC_OCRDYR; 978 979 mmio_clrsetbits_32(rcc + RCC_HSICFGR, 980 RCC_HSICFGR_HSIDIV_MASK, 981 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 982 983 start = get_timer(0); 984 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 985 if (get_timer(start) > HSIDIV_TIMEOUT) { 986 ERROR("HSIDIV failed @ 0x%x: 0x%x\n", 987 address, mmio_read_32(address)); 988 return -ETIMEDOUT; 989 } 990 } 991 992 return 0; 993 } 994 995 static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq) 996 { 997 uint8_t hsidiv; 998 uint32_t hsidivfreq = MAX_HSI_HZ; 999 1000 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1001 if (hsidivfreq == hsifreq) { 1002 break; 1003 } 1004 1005 hsidivfreq /= 2U; 1006 } 1007 1008 if (hsidiv == 4U) { 1009 ERROR("Invalid clk-hsi frequency\n"); 1010 return -1; 1011 } 1012 1013 if (hsidiv != 0U) { 1014 return stm32mp1_set_hsidiv(rcc, hsidiv); 1015 } 1016 1017 return 0; 1018 } 1019 1020 static void stm32mp1_pll_start(struct stm32mp1_clk_priv *priv, 1021 enum stm32mp1_pll_id pll_id) 1022 { 1023 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1024 1025 mmio_write_32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_PLLON); 1026 } 1027 1028 static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv, 1029 enum stm32mp1_pll_id pll_id, uint32_t output) 1030 { 1031 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1032 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1033 unsigned long start; 1034 1035 start = get_timer(0); 1036 /* Wait PLL lock */ 1037 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1038 if (get_timer(start) > PLLRDY_TIMEOUT) { 1039 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 1040 pll_id, pllxcr, mmio_read_32(pllxcr)); 1041 return -ETIMEDOUT; 1042 } 1043 } 1044 1045 /* Start the requested output */ 1046 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1047 1048 return 0; 1049 } 1050 1051 static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, 1052 enum stm32mp1_pll_id pll_id) 1053 { 1054 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1055 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; 1056 unsigned long start; 1057 1058 /* Stop all output */ 1059 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1060 RCC_PLLNCR_DIVREN); 1061 1062 /* Stop PLL */ 1063 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1064 1065 start = get_timer(0); 1066 /* Wait PLL stopped */ 1067 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1068 if (get_timer(start) > PLLRDY_TIMEOUT) { 1069 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", 1070 pll_id, pllxcr, mmio_read_32(pllxcr)); 1071 return -ETIMEDOUT; 1072 } 1073 } 1074 1075 return 0; 1076 } 1077 1078 static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv, 1079 enum stm32mp1_pll_id pll_id, 1080 uint32_t *pllcfg) 1081 { 1082 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1083 uint32_t rcc = priv->base; 1084 uint32_t value; 1085 1086 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1087 RCC_PLLNCFGR2_DIVP_MASK; 1088 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1089 RCC_PLLNCFGR2_DIVQ_MASK; 1090 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1091 RCC_PLLNCFGR2_DIVR_MASK; 1092 mmio_write_32(rcc + pll[pll_id].pllxcfgr2, value); 1093 } 1094 1095 static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv, 1096 enum stm32mp1_pll_id pll_id, 1097 uint32_t *pllcfg, uint32_t fracv) 1098 { 1099 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1100 uint32_t rcc = priv->base; 1101 enum stm32mp1_plltype type = pll[pll_id].plltype; 1102 unsigned long refclk; 1103 uint32_t ifrge = 0; 1104 uint32_t src, value; 1105 1106 src = mmio_read_32(priv->base + pll[pll_id].rckxselr) & 1107 RCC_SELR_REFCLK_SRC_MASK; 1108 1109 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1110 (pllcfg[PLLCFG_M] + 1U); 1111 1112 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1113 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1114 return -EINVAL; 1115 } 1116 1117 if ((type == PLL_800) && (refclk >= 8000000U)) { 1118 ifrge = 1U; 1119 } 1120 1121 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1122 RCC_PLLNCFGR1_DIVN_MASK; 1123 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1124 RCC_PLLNCFGR1_DIVM_MASK; 1125 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1126 RCC_PLLNCFGR1_IFRGE_MASK; 1127 mmio_write_32(rcc + pll[pll_id].pllxcfgr1, value); 1128 1129 /* Fractional configuration */ 1130 value = 0; 1131 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1132 1133 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1134 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1135 1136 value |= RCC_PLLNFRACR_FRACLE; 1137 mmio_write_32(rcc + pll[pll_id].pllxfracr, value); 1138 1139 stm32mp1_pll_config_output(priv, pll_id, pllcfg); 1140 1141 return 0; 1142 } 1143 1144 static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv, 1145 enum stm32mp1_pll_id pll_id, 1146 uint32_t *csg) 1147 { 1148 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1149 uint32_t pllxcsg = 0; 1150 1151 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1152 RCC_PLLNCSGR_MOD_PER_MASK; 1153 1154 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1155 RCC_PLLNCSGR_INC_STEP_MASK; 1156 1157 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1158 RCC_PLLNCSGR_SSCG_MODE_MASK; 1159 1160 mmio_write_32(priv->base + pll[pll_id].pllxcsgr, pllxcsg); 1161 } 1162 1163 static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv, 1164 unsigned int clksrc) 1165 { 1166 uint32_t address = priv->base + (clksrc >> 4); 1167 unsigned long start; 1168 1169 mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK, 1170 clksrc & RCC_SELR_SRC_MASK); 1171 1172 start = get_timer(0); 1173 while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) { 1174 if (get_timer(start) > CLKSRC_TIMEOUT) { 1175 ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1176 clksrc, address, mmio_read_32(address)); 1177 return -ETIMEDOUT; 1178 } 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) 1185 { 1186 unsigned long start; 1187 1188 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1189 clkdiv & RCC_DIVR_DIV_MASK); 1190 1191 start = get_timer(0); 1192 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1193 if (get_timer(start) > CLKDIV_TIMEOUT) { 1194 ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1195 clkdiv, address, mmio_read_32(address)); 1196 return -ETIMEDOUT; 1197 } 1198 } 1199 1200 return 0; 1201 } 1202 1203 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1204 uint32_t clksrc, uint32_t clkdiv) 1205 { 1206 uint32_t address = priv->base + (clksrc >> 4); 1207 1208 /* 1209 * Binding clksrc : 1210 * bit15-4 offset 1211 * bit3: disable 1212 * bit2-0: MCOSEL[2:0] 1213 */ 1214 if ((clksrc & 0x8U) != 0U) { 1215 mmio_clrbits_32(address, RCC_MCOCFG_MCOON); 1216 } else { 1217 mmio_clrsetbits_32(address, 1218 RCC_MCOCFG_MCOSRC_MASK, 1219 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1220 mmio_clrsetbits_32(address, 1221 RCC_MCOCFG_MCODIV_MASK, 1222 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1223 mmio_setbits_32(address, RCC_MCOCFG_MCOON); 1224 } 1225 } 1226 1227 static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv, 1228 unsigned int clksrc, bool lse_css) 1229 { 1230 uint32_t address = priv->base + RCC_BDCR; 1231 1232 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1233 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1234 mmio_clrsetbits_32(address, 1235 RCC_BDCR_RTCSRC_MASK, 1236 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1237 1238 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1239 } 1240 1241 if (lse_css) { 1242 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1243 } 1244 } 1245 1246 #define CNTCVL_OFF 0x008 1247 #define CNTCVU_OFF 0x00C 1248 1249 static void stm32mp1_stgen_config(struct stm32mp1_clk_priv *priv) 1250 { 1251 uintptr_t stgen; 1252 int p; 1253 uint32_t cntfid0; 1254 unsigned long rate; 1255 1256 stgen = fdt_get_stgen_base(); 1257 1258 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1259 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1260 rate = stm32mp1_clk_get(priv, p); 1261 1262 if (cntfid0 != rate) { 1263 unsigned long long counter; 1264 1265 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1266 counter = (unsigned long long) 1267 mmio_read_32(stgen + CNTCVL_OFF); 1268 counter |= ((unsigned long long) 1269 (mmio_read_32(stgen + CNTCVU_OFF))) << 32; 1270 counter = (counter * rate / cntfid0); 1271 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1272 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1273 mmio_write_32(stgen + CNTFID_OFF, rate); 1274 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1275 1276 write_cntfrq((u_register_t)rate); 1277 1278 /* Need to update timer with new frequency */ 1279 generic_delay_timer_init(); 1280 } 1281 } 1282 1283 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1284 { 1285 uintptr_t stgen; 1286 unsigned long long cnt; 1287 1288 stgen = fdt_get_stgen_base(); 1289 1290 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1291 mmio_read_32(stgen + CNTCVL_OFF); 1292 1293 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1294 1295 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1296 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1297 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1298 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1299 } 1300 1301 static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs) 1302 { 1303 uint32_t address = priv->base + ((pkcs >> 4) & 0xFFFU); 1304 uint32_t value = pkcs & 0xFU; 1305 uint32_t mask = 0xFU; 1306 1307 if ((pkcs & BIT(31)) != 0U) { 1308 mask <<= 4; 1309 value <<= 4; 1310 } 1311 1312 mmio_clrsetbits_32(address, mask, value); 1313 } 1314 1315 int stm32mp1_clk_init(void) 1316 { 1317 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1318 uint32_t rcc = priv->base; 1319 unsigned int clksrc[CLKSRC_NB]; 1320 unsigned int clkdiv[CLKDIV_NB]; 1321 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1322 int plloff[_PLL_NB]; 1323 int ret, len; 1324 enum stm32mp1_pll_id i; 1325 bool lse_css = false; 1326 const uint32_t *pkcs_cell; 1327 1328 /* Check status field to disable security */ 1329 if (!fdt_get_rcc_secure_status()) { 1330 mmio_write_32(rcc + RCC_TZCR, 0); 1331 } 1332 1333 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1334 (uint32_t)CLKSRC_NB); 1335 if (ret < 0) { 1336 return -FDT_ERR_NOTFOUND; 1337 } 1338 1339 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1340 (uint32_t)CLKDIV_NB); 1341 if (ret < 0) { 1342 return -FDT_ERR_NOTFOUND; 1343 } 1344 1345 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1346 char name[12]; 1347 1348 snprintf(name, sizeof(name), "st,pll@%d", i); 1349 plloff[i] = fdt_rcc_subnode_offset(name); 1350 1351 if (!fdt_check_node(plloff[i])) { 1352 continue; 1353 } 1354 1355 ret = fdt_read_uint32_array(plloff[i], "cfg", 1356 pllcfg[i], (int)PLLCFG_NB); 1357 if (ret < 0) { 1358 return -FDT_ERR_NOTFOUND; 1359 } 1360 } 1361 1362 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1363 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1364 1365 /* 1366 * Switch ON oscillator found in device-tree. 1367 * Note: HSI already ON after BootROM stage. 1368 */ 1369 if (priv->osc[_LSI] != 0U) { 1370 stm32mp1_lsi_set(rcc, 1); 1371 } 1372 if (priv->osc[_LSE] != 0U) { 1373 bool bypass; 1374 uint32_t lsedrv; 1375 1376 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1377 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1378 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1379 LSEDRV_MEDIUM_HIGH); 1380 stm32mp1_lse_enable(rcc, bypass, lsedrv); 1381 } 1382 if (priv->osc[_HSE] != 0U) { 1383 bool bypass, css; 1384 1385 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1386 css = fdt_osc_read_bool(_LSE, "st,css"); 1387 stm32mp1_hse_enable(rcc, bypass, css); 1388 } 1389 /* 1390 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1391 * => switch on CSI even if node is not present in device tree 1392 */ 1393 stm32mp1_csi_set(rcc, 1); 1394 1395 /* Come back to HSI */ 1396 ret = stm32mp1_set_clksrc(priv, CLK_MPU_HSI); 1397 if (ret != 0) { 1398 return ret; 1399 } 1400 ret = stm32mp1_set_clksrc(priv, CLK_AXI_HSI); 1401 if (ret != 0) { 1402 return ret; 1403 } 1404 1405 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1406 if (i == _PLL4) 1407 continue; 1408 ret = stm32mp1_pll_stop(priv, i); 1409 if (ret != 0) { 1410 return ret; 1411 } 1412 } 1413 1414 /* Configure HSIDIV */ 1415 if (priv->osc[_HSI] != 0U) { 1416 ret = stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1417 if (ret != 0) { 1418 return ret; 1419 } 1420 stm32mp1_stgen_config(priv); 1421 } 1422 1423 /* Select DIV */ 1424 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1425 mmio_write_32(rcc + RCC_MPCKDIVR, 1426 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1427 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1428 if (ret != 0) { 1429 return ret; 1430 } 1431 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1432 if (ret != 0) { 1433 return ret; 1434 } 1435 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1436 if (ret != 0) { 1437 return ret; 1438 } 1439 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1440 if (ret != 0) { 1441 return ret; 1442 } 1443 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1444 if (ret != 0) { 1445 return ret; 1446 } 1447 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1448 if (ret != 0) { 1449 return ret; 1450 } 1451 1452 /* No ready bit for RTC */ 1453 mmio_write_32(rcc + RCC_RTCDIVR, 1454 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1455 1456 /* Configure PLLs source */ 1457 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1458 if (ret != 0) { 1459 return ret; 1460 } 1461 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1462 if (ret != 0) { 1463 return ret; 1464 } 1465 1466 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1467 if (ret != 0) { 1468 return ret; 1469 } 1470 1471 /* Configure and start PLLs */ 1472 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1473 uint32_t fracv; 1474 uint32_t csg[PLLCSG_NB]; 1475 1476 if (!fdt_check_node(plloff[i])) { 1477 continue; 1478 } 1479 1480 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1481 1482 ret = stm32mp1_pll_config(priv, i, pllcfg[i], fracv); 1483 if (ret != 0) { 1484 return ret; 1485 } 1486 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1487 (uint32_t)PLLCSG_NB); 1488 if (ret == 0) { 1489 stm32mp1_pll_csg(priv, i, csg); 1490 } else if (ret != -FDT_ERR_NOTFOUND) { 1491 return ret; 1492 } 1493 1494 stm32mp1_pll_start(priv, i); 1495 } 1496 /* Wait and start PLLs ouptut when ready */ 1497 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1498 if (!fdt_check_node(plloff[i])) { 1499 continue; 1500 } 1501 1502 ret = stm32mp1_pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1503 if (ret != 0) { 1504 return ret; 1505 } 1506 } 1507 /* Wait LSE ready before to use it */ 1508 if (priv->osc[_LSE] != 0U) { 1509 stm32mp1_lse_wait(rcc); 1510 } 1511 1512 /* Configure with expected clock source */ 1513 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_MPU]); 1514 if (ret != 0) { 1515 return ret; 1516 } 1517 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_AXI]); 1518 if (ret != 0) { 1519 return ret; 1520 } 1521 stm32mp1_set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1522 1523 /* Configure PKCK */ 1524 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1525 if (pkcs_cell != NULL) { 1526 bool ckper_disabled = false; 1527 uint32_t j; 1528 1529 priv->pkcs_usb_value = 0; 1530 1531 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1532 uint32_t pkcs = (uint32_t)fdt32_to_cpu(pkcs_cell[j]); 1533 1534 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1535 ckper_disabled = true; 1536 continue; 1537 } 1538 stm32mp1_pkcs_config(priv, pkcs); 1539 } 1540 1541 /* 1542 * CKPER is source for some peripheral clocks 1543 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1544 * only if previous clock is still ON 1545 * => deactivated CKPER only after switching clock 1546 */ 1547 if (ckper_disabled) { 1548 stm32mp1_pkcs_config(priv, CLK_CKPER_DISABLED); 1549 } 1550 } 1551 1552 /* Switch OFF HSI if not found in device-tree */ 1553 if (priv->osc[_HSI] == 0U) { 1554 stm32mp1_hsi_set(rcc, 0); 1555 } 1556 stm32mp1_stgen_config(priv); 1557 1558 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1559 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 1560 RCC_DDRITFCR_DDRCKMOD_MASK, 1561 RCC_DDRITFCR_DDRCKMOD_SSR << 1562 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1563 1564 return 0; 1565 } 1566 1567 static void stm32mp1_osc_clk_init(const char *name, 1568 struct stm32mp1_clk_priv *priv, 1569 enum stm32mp_osc_id index) 1570 { 1571 uint32_t frequency; 1572 1573 priv->osc[index] = 0; 1574 1575 if (fdt_osc_read_freq(name, &frequency) != 0) { 1576 ERROR("%s frequency request failed\n", name); 1577 panic(); 1578 } else { 1579 priv->osc[index] = frequency; 1580 } 1581 } 1582 1583 static void stm32mp1_osc_init(void) 1584 { 1585 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1586 enum stm32mp_osc_id i; 1587 1588 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1589 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], priv, i); 1590 } 1591 } 1592 1593 int stm32mp1_clk_probe(void) 1594 { 1595 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; 1596 1597 priv->base = fdt_rcc_read_addr(); 1598 if (priv->base == 0U) { 1599 return -EINVAL; 1600 } 1601 1602 priv->data = &stm32mp1_data; 1603 1604 if ((priv->data->gate == NULL) || (priv->data->sel == NULL) || 1605 (priv->data->pll == NULL)) { 1606 return -EINVAL; 1607 } 1608 1609 stm32mp1_osc_init(); 1610 1611 return 0; 1612 } 1613