1 /* 2 * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_rcc.h> 21 #include <dt-bindings/clock/stm32mp1-clksrc.h> 22 #include <lib/mmio.h> 23 #include <lib/spinlock.h> 24 #include <lib/utils_def.h> 25 #include <libfdt.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 30 enum stm32mp1_pllcfg { 31 PLLCFG_M, 32 PLLCFG_N, 33 PLL_DIV_MN_NB, 34 PLLCFG_P = PLL_DIV_MN_NB, 35 PLLCFG_Q, 36 PLLCFG_R, 37 PLLCFG_O, 38 PLLCFG_NB 39 }; 40 41 #define PLL_DIV_MN_NB 2 42 #define PLL_DIV_PQR_NB 3 43 44 enum stm32mp1_pllcsg { 45 PLLCSG_MOD_PER, 46 PLLCSG_INC_STEP, 47 PLLCSG_SSCG_MODE, 48 PLLCSG_NB 49 }; 50 51 struct stm32_pll_dt_cfg { 52 bool status; 53 uint32_t src; 54 uint32_t cfg[PLLCFG_NB]; 55 uint32_t frac; 56 bool csg_enabled; 57 uint32_t csg[PLLCSG_NB]; 58 }; 59 60 struct stm32_clk_platdata { 61 uint32_t npll; 62 struct stm32_pll_dt_cfg *pll; 63 uint32_t nclksrc; 64 uint32_t *clksrc; 65 uint32_t nclkdiv; 66 uint32_t *clkdiv; 67 bool lse_css; 68 }; 69 70 struct stm32_clk_priv { 71 uintptr_t base; 72 const struct mux_cfg *parents; 73 const uint32_t nb_parents; 74 const struct div_cfg *div; 75 const uint32_t nb_div; 76 void *pdata; 77 }; 78 79 static struct stm32_clk_priv *stm32_clock_data; 80 81 static struct stm32_clk_priv *clk_stm32_get_priv(void) 82 { 83 return stm32_clock_data; 84 } 85 86 static int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base) 87 { 88 stm32_clock_data = priv; 89 90 priv->base = base; 91 92 return 0; 93 } 94 95 #define MAX_HSI_HZ 64000000 96 #define USB_PHY_48_MHZ 48000000 97 98 #define TIMEOUT_US_200MS U(200000) 99 #define TIMEOUT_US_1S U(1000000) 100 101 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 102 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 103 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 104 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 105 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 106 107 struct mux_cfg { 108 uint16_t offset; 109 uint8_t shift; 110 uint8_t width; 111 uint8_t bitrdy; 112 }; 113 114 struct div_cfg { 115 uint16_t offset; 116 uint8_t shift; 117 uint8_t width; 118 uint8_t bitrdy; 119 }; 120 121 #define DIV_NO_BIT_RDY UINT8_MAX 122 123 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\ 124 [(_id)] = {\ 125 .offset = (_offset),\ 126 .shift = (_shift),\ 127 .width = (_width),\ 128 .bitrdy = (_bitrdy),\ 129 } 130 131 static const struct div_cfg dividers_mp15[] = { 132 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31), 133 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 31), 134 DIV_CFG(DIV_MCU, RCC_MCUDIVR, 0, 4, 31), 135 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 31), 136 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 31), 137 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 31), 138 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 31), 139 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31), 140 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, DIV_NO_BIT_RDY), 141 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, DIV_NO_BIT_RDY), 142 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, DIV_NO_BIT_RDY), 143 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, DIV_NO_BIT_RDY), 144 DIV_CFG(DIV_ETHPTP, RCC_ETHCKSELR, 4, 4, DIV_NO_BIT_RDY), 145 }; 146 147 /* 148 * MUX CONFIG 149 */ 150 151 #define MUX_NO_BIT_RDY UINT8_MAX 152 153 #define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\ 154 [(_id)] = {\ 155 .offset = (_offset),\ 156 .shift = (_shift),\ 157 .width = (_width),\ 158 .bitrdy = (_bitrdy),\ 159 } 160 161 #define MUX_CFG(_id, _offset, _shift, _width)\ 162 MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY) 163 164 static const struct mux_cfg parent_mp15[MUX_NB] = { 165 MUX_CFG(MUX_PLL12, RCC_RCK12SELR, 0, 2), 166 MUX_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2), 167 MUX_CFG(MUX_PLL4, RCC_RCK4SELR, 0, 2), 168 MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2), 169 MUXRDY_CFG(MUX_MPU, RCC_MPCKSELR, 0, 2, 31), 170 MUXRDY_CFG(MUX_AXI, RCC_ASSCKSELR, 0, 3, 31), 171 MUXRDY_CFG(MUX_MCU, RCC_MSSCKSELR, 0, 2, 31), 172 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2), 173 MUX_CFG(MUX_SDMMC12, RCC_SDMMC12CKSELR, 0, 3), 174 MUX_CFG(MUX_SPI2S23, RCC_SPI2S23CKSELR, 0, 3), 175 MUX_CFG(MUX_SPI45, RCC_SPI45CKSELR, 0, 3), 176 MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3), 177 MUX_CFG(MUX_I2C35, RCC_I2C35CKSELR, 0, 3), 178 MUX_CFG(MUX_LPTIM23, RCC_LPTIM23CKSELR, 0, 3), 179 MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3), 180 MUX_CFG(MUX_UART24, RCC_UART24CKSELR, 0, 3), 181 MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3), 182 MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3), 183 MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3), 184 MUX_CFG(MUX_ETH, RCC_ETHCKSELR, 0, 2), 185 MUX_CFG(MUX_I2C46, RCC_I2C46CKSELR, 0, 3), 186 MUX_CFG(MUX_RNG2, RCC_RNG2CKSELR, 0, 2), 187 MUX_CFG(MUX_SDMMC3, RCC_SDMMC3CKSELR, 0, 3), 188 MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2), 189 MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2), 190 MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2), 191 MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1), 192 MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2), 193 MUX_CFG(MUX_SPI2S1, RCC_SPI2S1CKSELR, 0, 3), 194 MUX_CFG(MUX_CEC, RCC_CECCKSELR, 0, 2), 195 MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3), 196 MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3), 197 MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2), 198 MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3), 199 MUX_CFG(MUX_SAI3, RCC_SAI3CKSELR, 0, 3), 200 MUX_CFG(MUX_SAI4, RCC_SAI4CKSELR, 0, 3), 201 MUX_CFG(MUX_ADC, RCC_ADCCKSELR, 0, 2), 202 MUX_CFG(MUX_DSI, RCC_DSICKSELR, 0, 1), 203 MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2), 204 MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2), 205 MUX_CFG(MUX_UART1, RCC_UART1CKSELR, 0, 3), 206 MUX_CFG(MUX_SPI6, RCC_SPI6CKSELR, 0, 3), 207 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3), 208 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3), 209 }; 210 211 #define MASK_WIDTH_SHIFT(_width, _shift) \ 212 GENMASK(((_width) + (_shift) - 1U), (_shift)) 213 214 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id) 215 { 216 const struct mux_cfg *mux; 217 uint32_t mask; 218 219 if (mux_id >= priv->nb_parents) { 220 panic(); 221 } 222 223 mux = &priv->parents[mux_id]; 224 225 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); 226 227 return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift; 228 } 229 230 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) 231 { 232 const struct mux_cfg *mux = &priv->parents[pid]; 233 uintptr_t address = priv->base + mux->offset; 234 uint32_t mask; 235 uint64_t timeout; 236 237 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); 238 239 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); 240 241 if (mux->bitrdy == MUX_NO_BIT_RDY) { 242 return 0; 243 } 244 245 timeout = timeout_init_us(CLKSRC_TIMEOUT); 246 247 mask = BIT(mux->bitrdy); 248 249 while ((mmio_read_32(address) & mask) == 0U) { 250 if (timeout_elapsed(timeout)) { 251 return -ETIMEDOUT; 252 } 253 } 254 255 return 0; 256 } 257 258 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val) 259 { 260 uint32_t data = val & CMD_DATA_MASK; 261 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 262 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 263 264 return clk_mux_set_parent(priv, mux, sel); 265 } 266 267 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) 268 { 269 const struct div_cfg *divider; 270 uintptr_t address; 271 uint64_t timeout; 272 uint32_t mask; 273 274 if (div_id >= priv->nb_div) { 275 panic(); 276 } 277 278 divider = &priv->div[div_id]; 279 address = priv->base + divider->offset; 280 281 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); 282 mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); 283 284 if (divider->bitrdy == DIV_NO_BIT_RDY) { 285 return 0; 286 } 287 288 timeout = timeout_init_us(CLKSRC_TIMEOUT); 289 mask = BIT(divider->bitrdy); 290 291 while ((mmio_read_32(address) & mask) == 0U) { 292 if (timeout_elapsed(timeout)) { 293 return -ETIMEDOUT; 294 } 295 } 296 297 return 0; 298 } 299 300 const char *stm32mp_osc_node_label[NB_OSC] = { 301 [_LSI] = "clk-lsi", 302 [_LSE] = "clk-lse", 303 [_HSI] = "clk-hsi", 304 [_HSE] = "clk-hse", 305 [_CSI] = "clk-csi", 306 [_I2S_CKIN] = "i2s_ckin", 307 }; 308 309 enum stm32mp1_parent_id { 310 /* Oscillators are defined in enum stm32mp_osc_id */ 311 312 /* Other parent source */ 313 _HSI_KER = NB_OSC, 314 _HSE_KER, 315 _HSE_KER_DIV2, 316 _HSE_RTC, 317 _CSI_KER, 318 _PLL1_P, 319 _PLL1_Q, 320 _PLL1_R, 321 _PLL2_P, 322 _PLL2_Q, 323 _PLL2_R, 324 _PLL3_P, 325 _PLL3_Q, 326 _PLL3_R, 327 _PLL4_P, 328 _PLL4_Q, 329 _PLL4_R, 330 _ACLK, 331 _PCLK1, 332 _PCLK2, 333 _PCLK3, 334 _PCLK4, 335 _PCLK5, 336 _HCLK6, 337 _HCLK2, 338 _CK_PER, 339 _CK_MPU, 340 _CK_MCU, 341 _USB_PHY_48, 342 _PARENT_NB, 343 _UNKNOWN_ID = 0xff, 344 }; 345 346 /* Lists only the parent clock we are interested in */ 347 enum stm32mp1_parent_sel { 348 _I2C12_SEL, 349 _I2C35_SEL, 350 _STGEN_SEL, 351 _I2C46_SEL, 352 _SPI6_SEL, 353 _UART1_SEL, 354 _RNG1_SEL, 355 _UART6_SEL, 356 _UART24_SEL, 357 _UART35_SEL, 358 _UART78_SEL, 359 _SDMMC12_SEL, 360 _SDMMC3_SEL, 361 _QSPI_SEL, 362 _FMC_SEL, 363 _AXIS_SEL, 364 _MCUS_SEL, 365 _USBPHY_SEL, 366 _USBO_SEL, 367 _MPU_SEL, 368 _CKPER_SEL, 369 _RTC_SEL, 370 _PARENT_SEL_NB, 371 _UNKNOWN_SEL = 0xff, 372 }; 373 374 /* State the parent clock ID straight related to a clock */ 375 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 376 [_HSE] = CK_HSE, 377 [_HSI] = CK_HSI, 378 [_CSI] = CK_CSI, 379 [_LSE] = CK_LSE, 380 [_LSI] = CK_LSI, 381 [_I2S_CKIN] = _UNKNOWN_ID, 382 [_USB_PHY_48] = _UNKNOWN_ID, 383 [_HSI_KER] = CK_HSI, 384 [_HSE_KER] = CK_HSE, 385 [_HSE_KER_DIV2] = CK_HSE_DIV2, 386 [_HSE_RTC] = _UNKNOWN_ID, 387 [_CSI_KER] = CK_CSI, 388 [_PLL1_P] = PLL1_P, 389 [_PLL1_Q] = PLL1_Q, 390 [_PLL1_R] = PLL1_R, 391 [_PLL2_P] = PLL2_P, 392 [_PLL2_Q] = PLL2_Q, 393 [_PLL2_R] = PLL2_R, 394 [_PLL3_P] = PLL3_P, 395 [_PLL3_Q] = PLL3_Q, 396 [_PLL3_R] = PLL3_R, 397 [_PLL4_P] = PLL4_P, 398 [_PLL4_Q] = PLL4_Q, 399 [_PLL4_R] = PLL4_R, 400 [_ACLK] = CK_AXI, 401 [_PCLK1] = CK_AXI, 402 [_PCLK2] = CK_AXI, 403 [_PCLK3] = CK_AXI, 404 [_PCLK4] = CK_AXI, 405 [_PCLK5] = CK_AXI, 406 [_CK_PER] = CK_PER, 407 [_CK_MPU] = CK_MPU, 408 [_CK_MCU] = CK_MCU, 409 }; 410 411 static unsigned int clock_id2parent_id(unsigned long id) 412 { 413 unsigned int n; 414 415 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 416 if (parent_id_clock_id[n] == id) { 417 return n; 418 } 419 } 420 421 return _UNKNOWN_ID; 422 } 423 424 enum stm32mp1_pll_id { 425 _PLL1, 426 _PLL2, 427 _PLL3, 428 _PLL4, 429 _PLL_NB 430 }; 431 432 enum stm32mp1_div_id { 433 _DIV_P, 434 _DIV_Q, 435 _DIV_R, 436 _DIV_NB, 437 }; 438 439 enum stm32mp1_clksrc_id { 440 CLKSRC_MPU, 441 CLKSRC_AXI, 442 CLKSRC_MCU, 443 CLKSRC_PLL12, 444 CLKSRC_PLL3, 445 CLKSRC_PLL4, 446 CLKSRC_RTC, 447 CLKSRC_MCO1, 448 CLKSRC_MCO2, 449 CLKSRC_NB 450 }; 451 452 enum stm32mp1_clkdiv_id { 453 CLKDIV_MPU, 454 CLKDIV_AXI, 455 CLKDIV_MCU, 456 CLKDIV_APB1, 457 CLKDIV_APB2, 458 CLKDIV_APB3, 459 CLKDIV_APB4, 460 CLKDIV_APB5, 461 CLKDIV_RTC, 462 CLKDIV_MCO1, 463 CLKDIV_MCO2, 464 CLKDIV_NB 465 }; 466 467 enum stm32mp1_plltype { 468 PLL_800, 469 PLL_1600, 470 PLL_TYPE_NB 471 }; 472 473 struct stm32mp1_pll { 474 uint8_t refclk_min; 475 uint8_t refclk_max; 476 }; 477 478 struct stm32mp1_clk_gate { 479 uint16_t offset; 480 uint8_t bit; 481 uint8_t index; 482 uint8_t set_clr; 483 uint8_t secure; 484 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 485 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 486 }; 487 488 struct stm32mp1_clk_sel { 489 uint16_t offset; 490 uint8_t src; 491 uint8_t msk; 492 uint8_t nb_parent; 493 const uint8_t *parent; 494 }; 495 496 #define REFCLK_SIZE 4 497 struct stm32mp1_clk_pll { 498 enum stm32mp1_plltype plltype; 499 uint16_t rckxselr; 500 uint16_t pllxcfgr1; 501 uint16_t pllxcfgr2; 502 uint16_t pllxfracr; 503 uint16_t pllxcr; 504 uint16_t pllxcsgr; 505 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 506 }; 507 508 /* Clocks with selectable source and non set/clr register access */ 509 #define _CLK_SELEC(sec, off, b, idx, s) \ 510 { \ 511 .offset = (off), \ 512 .bit = (b), \ 513 .index = (idx), \ 514 .set_clr = 0, \ 515 .secure = (sec), \ 516 .sel = (s), \ 517 .fixed = _UNKNOWN_ID, \ 518 } 519 520 /* Clocks with fixed source and non set/clr register access */ 521 #define _CLK_FIXED(sec, off, b, idx, f) \ 522 { \ 523 .offset = (off), \ 524 .bit = (b), \ 525 .index = (idx), \ 526 .set_clr = 0, \ 527 .secure = (sec), \ 528 .sel = _UNKNOWN_SEL, \ 529 .fixed = (f), \ 530 } 531 532 /* Clocks with selectable source and set/clr register access */ 533 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 534 { \ 535 .offset = (off), \ 536 .bit = (b), \ 537 .index = (idx), \ 538 .set_clr = 1, \ 539 .secure = (sec), \ 540 .sel = (s), \ 541 .fixed = _UNKNOWN_ID, \ 542 } 543 544 /* Clocks with fixed source and set/clr register access */ 545 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 546 { \ 547 .offset = (off), \ 548 .bit = (b), \ 549 .index = (idx), \ 550 .set_clr = 1, \ 551 .secure = (sec), \ 552 .sel = _UNKNOWN_SEL, \ 553 .fixed = (f), \ 554 } 555 556 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 557 [_ ## _label ## _SEL] = { \ 558 .offset = _rcc_selr, \ 559 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 560 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 561 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 562 .parent = (_parents), \ 563 .nb_parent = ARRAY_SIZE(_parents) \ 564 } 565 566 #define _CLK_PLL(idx, type, off1, off2, off3, \ 567 off4, off5, off6, \ 568 p1, p2, p3, p4) \ 569 [(idx)] = { \ 570 .plltype = (type), \ 571 .rckxselr = (off1), \ 572 .pllxcfgr1 = (off2), \ 573 .pllxcfgr2 = (off3), \ 574 .pllxfracr = (off4), \ 575 .pllxcr = (off5), \ 576 .pllxcsgr = (off6), \ 577 .refclk[0] = (p1), \ 578 .refclk[1] = (p2), \ 579 .refclk[2] = (p3), \ 580 .refclk[3] = (p4), \ 581 } 582 583 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 584 585 #define SEC 1 586 #define N_S 0 587 588 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 589 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 590 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 591 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 592 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 593 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 594 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 595 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 596 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 597 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 598 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 599 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 600 601 #if defined(IMAGE_BL32) 602 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 603 #endif 604 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 605 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 606 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 607 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 608 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 609 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 610 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 611 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 612 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 613 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 614 615 #if defined(IMAGE_BL32) 616 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 617 #endif 618 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 619 620 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 621 622 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 623 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 624 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 625 626 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 627 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 628 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 629 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 630 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 631 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 632 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 633 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 634 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 635 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 636 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 637 638 #if defined(IMAGE_BL32) 639 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 640 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 641 #endif 642 643 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 644 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 645 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 646 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 647 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 648 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 649 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 650 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 651 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 652 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 653 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 654 655 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 656 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 657 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 658 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 659 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 660 661 #if defined(IMAGE_BL2) 662 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 663 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 664 #endif 665 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 666 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 667 #if defined(IMAGE_BL32) 668 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 669 #endif 670 671 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 672 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 673 }; 674 675 static const uint8_t i2c12_parents[] = { 676 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 677 }; 678 679 static const uint8_t i2c35_parents[] = { 680 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 681 }; 682 683 static const uint8_t stgen_parents[] = { 684 _HSI_KER, _HSE_KER 685 }; 686 687 static const uint8_t i2c46_parents[] = { 688 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 689 }; 690 691 static const uint8_t spi6_parents[] = { 692 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 693 }; 694 695 static const uint8_t usart1_parents[] = { 696 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 697 }; 698 699 static const uint8_t rng1_parents[] = { 700 _CSI, _PLL4_R, _LSE, _LSI 701 }; 702 703 static const uint8_t uart6_parents[] = { 704 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 705 }; 706 707 static const uint8_t uart234578_parents[] = { 708 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 709 }; 710 711 static const uint8_t sdmmc12_parents[] = { 712 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 713 }; 714 715 static const uint8_t sdmmc3_parents[] = { 716 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 717 }; 718 719 static const uint8_t qspi_parents[] = { 720 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 721 }; 722 723 static const uint8_t fmc_parents[] = { 724 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 725 }; 726 727 static const uint8_t axiss_parents[] = { 728 _HSI, _HSE, _PLL2_P 729 }; 730 731 static const uint8_t mcuss_parents[] = { 732 _HSI, _HSE, _CSI, _PLL3_P 733 }; 734 735 static const uint8_t usbphy_parents[] = { 736 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 737 }; 738 739 static const uint8_t usbo_parents[] = { 740 _PLL4_R, _USB_PHY_48 741 }; 742 743 static const uint8_t mpu_parents[] = { 744 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 745 }; 746 747 static const uint8_t per_parents[] = { 748 _HSI, _HSE, _CSI, 749 }; 750 751 static const uint8_t rtc_parents[] = { 752 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 753 }; 754 755 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 756 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 757 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 758 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 759 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 760 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 761 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 762 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 763 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 764 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 765 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 766 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 767 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 768 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 769 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 770 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 771 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 772 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 773 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 774 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 775 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 776 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 777 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 778 }; 779 780 /* Define characteristic of PLL according type */ 781 #define POST_DIVM_MIN 8000000U 782 #define POST_DIVM_MAX 16000000U 783 #define DIVM_MIN 0U 784 #define DIVM_MAX 63U 785 #define DIVN_MIN 24U 786 #define DIVN_MAX 99U 787 #define DIVP_MIN 0U 788 #define DIVP_MAX 127U 789 #define FRAC_MAX 8192U 790 #define VCO_MIN 800000000U 791 #define VCO_MAX 1600000000U 792 793 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 794 [PLL_800] = { 795 .refclk_min = 4, 796 .refclk_max = 16, 797 }, 798 [PLL_1600] = { 799 .refclk_min = 8, 800 .refclk_max = 16, 801 }, 802 }; 803 804 /* PLLNCFGR2 register divider by output */ 805 static const uint8_t pllncfgr2[_DIV_NB] = { 806 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 807 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 808 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 809 }; 810 811 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 812 _CLK_PLL(_PLL1, PLL_1600, 813 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 814 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 815 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 816 _CLK_PLL(_PLL2, PLL_1600, 817 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 818 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 819 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 820 _CLK_PLL(_PLL3, PLL_800, 821 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 822 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 823 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 824 _CLK_PLL(_PLL4, PLL_800, 825 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 826 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 827 _HSI, _HSE, _CSI, _I2S_CKIN), 828 }; 829 830 /* Prescaler table lookups for clock computation */ 831 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 832 static const uint8_t stm32mp1_mcu_div[16] = { 833 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 834 }; 835 836 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 837 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 838 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 839 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 840 0, 1, 2, 3, 4, 4, 4, 4 841 }; 842 843 /* div = /1 /2 /3 /4 */ 844 static const uint8_t stm32mp1_axi_div[8] = { 845 1, 2, 3, 4, 4, 4, 4, 4 846 }; 847 848 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 849 [_HSI] = "HSI", 850 [_HSE] = "HSE", 851 [_CSI] = "CSI", 852 [_LSI] = "LSI", 853 [_LSE] = "LSE", 854 [_I2S_CKIN] = "I2S_CKIN", 855 [_HSI_KER] = "HSI_KER", 856 [_HSE_KER] = "HSE_KER", 857 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 858 [_HSE_RTC] = "HSE_RTC", 859 [_CSI_KER] = "CSI_KER", 860 [_PLL1_P] = "PLL1_P", 861 [_PLL1_Q] = "PLL1_Q", 862 [_PLL1_R] = "PLL1_R", 863 [_PLL2_P] = "PLL2_P", 864 [_PLL2_Q] = "PLL2_Q", 865 [_PLL2_R] = "PLL2_R", 866 [_PLL3_P] = "PLL3_P", 867 [_PLL3_Q] = "PLL3_Q", 868 [_PLL3_R] = "PLL3_R", 869 [_PLL4_P] = "PLL4_P", 870 [_PLL4_Q] = "PLL4_Q", 871 [_PLL4_R] = "PLL4_R", 872 [_ACLK] = "ACLK", 873 [_PCLK1] = "PCLK1", 874 [_PCLK2] = "PCLK2", 875 [_PCLK3] = "PCLK3", 876 [_PCLK4] = "PCLK4", 877 [_PCLK5] = "PCLK5", 878 [_HCLK6] = "KCLK6", 879 [_HCLK2] = "HCLK2", 880 [_CK_PER] = "CK_PER", 881 [_CK_MPU] = "CK_MPU", 882 [_CK_MCU] = "CK_MCU", 883 [_USB_PHY_48] = "USB_PHY_48", 884 }; 885 886 /* RCC clock device driver private */ 887 static unsigned long stm32mp1_osc[NB_OSC]; 888 static struct spinlock reg_lock; 889 static unsigned int gate_refcounts[NB_GATES]; 890 static struct spinlock refcount_lock; 891 892 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 893 { 894 return &stm32mp1_clk_gate[idx]; 895 } 896 897 #if defined(IMAGE_BL32) 898 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 899 { 900 return gate->secure == N_S; 901 } 902 #endif 903 904 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 905 { 906 return &stm32mp1_clk_sel[idx]; 907 } 908 909 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 910 { 911 return &stm32mp1_clk_pll[idx]; 912 } 913 914 static void stm32mp1_clk_lock(struct spinlock *lock) 915 { 916 if (stm32mp_lock_available()) { 917 /* Assume interrupts are masked */ 918 spin_lock(lock); 919 } 920 } 921 922 static void stm32mp1_clk_unlock(struct spinlock *lock) 923 { 924 if (stm32mp_lock_available()) { 925 spin_unlock(lock); 926 } 927 } 928 929 bool stm32mp1_rcc_is_secure(void) 930 { 931 uintptr_t rcc_base = stm32mp_rcc_base(); 932 uint32_t mask = RCC_TZCR_TZEN; 933 934 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 935 } 936 937 bool stm32mp1_rcc_is_mckprot(void) 938 { 939 uintptr_t rcc_base = stm32mp_rcc_base(); 940 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 941 942 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 943 } 944 945 void stm32mp1_clk_rcc_regs_lock(void) 946 { 947 stm32mp1_clk_lock(®_lock); 948 } 949 950 void stm32mp1_clk_rcc_regs_unlock(void) 951 { 952 stm32mp1_clk_unlock(®_lock); 953 } 954 955 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 956 { 957 if (idx >= NB_OSC) { 958 return 0; 959 } 960 961 return stm32mp1_osc[idx]; 962 } 963 964 static int stm32mp1_clk_get_gated_id(unsigned long id) 965 { 966 unsigned int i; 967 968 for (i = 0U; i < NB_GATES; i++) { 969 if (gate_ref(i)->index == id) { 970 return i; 971 } 972 } 973 974 ERROR("%s: clk id %lu not found\n", __func__, id); 975 976 return -EINVAL; 977 } 978 979 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 980 { 981 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 982 } 983 984 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 985 { 986 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 987 } 988 989 static int stm32mp1_clk_get_parent(unsigned long id) 990 { 991 const struct stm32mp1_clk_sel *sel; 992 uint32_t p_sel; 993 int i; 994 enum stm32mp1_parent_id p; 995 enum stm32mp1_parent_sel s; 996 uintptr_t rcc_base = stm32mp_rcc_base(); 997 998 /* Few non gateable clock have a static parent ID, find them */ 999 i = (int)clock_id2parent_id(id); 1000 if (i != _UNKNOWN_ID) { 1001 return i; 1002 } 1003 1004 i = stm32mp1_clk_get_gated_id(id); 1005 if (i < 0) { 1006 panic(); 1007 } 1008 1009 p = stm32mp1_clk_get_fixed_parent(i); 1010 if (p < _PARENT_NB) { 1011 return (int)p; 1012 } 1013 1014 s = stm32mp1_clk_get_sel(i); 1015 if (s == _UNKNOWN_SEL) { 1016 return -EINVAL; 1017 } 1018 if (s >= _PARENT_SEL_NB) { 1019 panic(); 1020 } 1021 1022 sel = clk_sel_ref(s); 1023 p_sel = (mmio_read_32(rcc_base + sel->offset) & 1024 (sel->msk << sel->src)) >> sel->src; 1025 if (p_sel < sel->nb_parent) { 1026 return (int)sel->parent[p_sel]; 1027 } 1028 1029 return -EINVAL; 1030 } 1031 1032 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 1033 { 1034 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 1035 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 1036 1037 return stm32mp1_clk_get_fixed(pll->refclk[src]); 1038 } 1039 1040 /* 1041 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 1042 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 1043 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 1044 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 1045 */ 1046 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 1047 { 1048 unsigned long refclk, fvco; 1049 uint32_t cfgr1, fracr, divm, divn; 1050 uintptr_t rcc_base = stm32mp_rcc_base(); 1051 1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 1053 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 1054 1055 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 1056 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 1057 1058 refclk = stm32mp1_pll_get_fref(pll); 1059 1060 /* 1061 * With FRACV : 1062 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 1063 * Without FRACV 1064 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 1065 */ 1066 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 1067 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 1068 RCC_PLLNFRACR_FRACV_SHIFT; 1069 unsigned long long numerator, denominator; 1070 1071 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 1072 numerator = refclk * numerator; 1073 denominator = ((unsigned long long)divm + 1U) << 13; 1074 fvco = (unsigned long)(numerator / denominator); 1075 } else { 1076 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 1077 } 1078 1079 return fvco; 1080 } 1081 1082 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 1083 enum stm32mp1_div_id div_id) 1084 { 1085 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1086 unsigned long dfout; 1087 uint32_t cfgr2, divy; 1088 1089 if (div_id >= _DIV_NB) { 1090 return 0; 1091 } 1092 1093 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 1094 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 1095 1096 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 1097 1098 return dfout; 1099 } 1100 1101 static unsigned long get_clock_rate(int p) 1102 { 1103 uint32_t reg, clkdiv; 1104 unsigned long clock = 0; 1105 uintptr_t rcc_base = stm32mp_rcc_base(); 1106 1107 switch (p) { 1108 case _CK_MPU: 1109 /* MPU sub system */ 1110 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 1111 switch (reg & RCC_SELR_SRC_MASK) { 1112 case RCC_MPCKSELR_HSI: 1113 clock = stm32mp1_clk_get_fixed(_HSI); 1114 break; 1115 case RCC_MPCKSELR_HSE: 1116 clock = stm32mp1_clk_get_fixed(_HSE); 1117 break; 1118 case RCC_MPCKSELR_PLL: 1119 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1120 break; 1121 case RCC_MPCKSELR_PLL_MPUDIV: 1122 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1123 1124 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 1125 clkdiv = reg & RCC_MPUDIV_MASK; 1126 clock >>= stm32mp1_mpu_div[clkdiv]; 1127 break; 1128 default: 1129 break; 1130 } 1131 break; 1132 /* AXI sub system */ 1133 case _ACLK: 1134 case _HCLK2: 1135 case _HCLK6: 1136 case _PCLK4: 1137 case _PCLK5: 1138 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 1139 switch (reg & RCC_SELR_SRC_MASK) { 1140 case RCC_ASSCKSELR_HSI: 1141 clock = stm32mp1_clk_get_fixed(_HSI); 1142 break; 1143 case RCC_ASSCKSELR_HSE: 1144 clock = stm32mp1_clk_get_fixed(_HSE); 1145 break; 1146 case RCC_ASSCKSELR_PLL: 1147 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1148 break; 1149 default: 1150 break; 1151 } 1152 1153 /* System clock divider */ 1154 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 1155 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 1156 1157 switch (p) { 1158 case _PCLK4: 1159 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 1160 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1161 break; 1162 case _PCLK5: 1163 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 1164 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1165 break; 1166 default: 1167 break; 1168 } 1169 break; 1170 /* MCU sub system */ 1171 case _CK_MCU: 1172 case _PCLK1: 1173 case _PCLK2: 1174 case _PCLK3: 1175 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 1176 switch (reg & RCC_SELR_SRC_MASK) { 1177 case RCC_MSSCKSELR_HSI: 1178 clock = stm32mp1_clk_get_fixed(_HSI); 1179 break; 1180 case RCC_MSSCKSELR_HSE: 1181 clock = stm32mp1_clk_get_fixed(_HSE); 1182 break; 1183 case RCC_MSSCKSELR_CSI: 1184 clock = stm32mp1_clk_get_fixed(_CSI); 1185 break; 1186 case RCC_MSSCKSELR_PLL: 1187 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1188 break; 1189 default: 1190 break; 1191 } 1192 1193 /* MCU clock divider */ 1194 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 1195 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 1196 1197 switch (p) { 1198 case _PCLK1: 1199 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 1200 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1201 break; 1202 case _PCLK2: 1203 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 1204 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1205 break; 1206 case _PCLK3: 1207 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 1208 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1209 break; 1210 case _CK_MCU: 1211 default: 1212 break; 1213 } 1214 break; 1215 case _CK_PER: 1216 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 1217 switch (reg & RCC_SELR_SRC_MASK) { 1218 case RCC_CPERCKSELR_HSI: 1219 clock = stm32mp1_clk_get_fixed(_HSI); 1220 break; 1221 case RCC_CPERCKSELR_HSE: 1222 clock = stm32mp1_clk_get_fixed(_HSE); 1223 break; 1224 case RCC_CPERCKSELR_CSI: 1225 clock = stm32mp1_clk_get_fixed(_CSI); 1226 break; 1227 default: 1228 break; 1229 } 1230 break; 1231 case _HSI: 1232 case _HSI_KER: 1233 clock = stm32mp1_clk_get_fixed(_HSI); 1234 break; 1235 case _CSI: 1236 case _CSI_KER: 1237 clock = stm32mp1_clk_get_fixed(_CSI); 1238 break; 1239 case _HSE: 1240 case _HSE_KER: 1241 clock = stm32mp1_clk_get_fixed(_HSE); 1242 break; 1243 case _HSE_KER_DIV2: 1244 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 1245 break; 1246 case _HSE_RTC: 1247 clock = stm32mp1_clk_get_fixed(_HSE); 1248 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 1249 break; 1250 case _LSI: 1251 clock = stm32mp1_clk_get_fixed(_LSI); 1252 break; 1253 case _LSE: 1254 clock = stm32mp1_clk_get_fixed(_LSE); 1255 break; 1256 /* PLL */ 1257 case _PLL1_P: 1258 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1259 break; 1260 case _PLL1_Q: 1261 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1262 break; 1263 case _PLL1_R: 1264 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1265 break; 1266 case _PLL2_P: 1267 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1268 break; 1269 case _PLL2_Q: 1270 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1271 break; 1272 case _PLL2_R: 1273 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1274 break; 1275 case _PLL3_P: 1276 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1277 break; 1278 case _PLL3_Q: 1279 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1280 break; 1281 case _PLL3_R: 1282 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1283 break; 1284 case _PLL4_P: 1285 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1286 break; 1287 case _PLL4_Q: 1288 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1289 break; 1290 case _PLL4_R: 1291 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1292 break; 1293 /* Other */ 1294 case _USB_PHY_48: 1295 clock = USB_PHY_48_MHZ; 1296 break; 1297 default: 1298 break; 1299 } 1300 1301 return clock; 1302 } 1303 1304 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1305 { 1306 uintptr_t rcc_base = stm32mp_rcc_base(); 1307 1308 VERBOSE("Enable clock %u\n", gate->index); 1309 1310 if (gate->set_clr != 0U) { 1311 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1312 } else { 1313 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1314 } 1315 } 1316 1317 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1318 { 1319 uintptr_t rcc_base = stm32mp_rcc_base(); 1320 1321 VERBOSE("Disable clock %u\n", gate->index); 1322 1323 if (gate->set_clr != 0U) { 1324 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1325 BIT(gate->bit)); 1326 } else { 1327 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1328 } 1329 } 1330 1331 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1332 { 1333 uintptr_t rcc_base = stm32mp_rcc_base(); 1334 1335 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1336 } 1337 1338 /* Oscillators and PLLs are not gated at runtime */ 1339 static bool clock_is_always_on(unsigned long id) 1340 { 1341 switch (id) { 1342 case CK_HSE: 1343 case CK_CSI: 1344 case CK_LSI: 1345 case CK_LSE: 1346 case CK_HSI: 1347 case CK_HSE_DIV2: 1348 case PLL1_Q: 1349 case PLL1_R: 1350 case PLL2_P: 1351 case PLL2_Q: 1352 case PLL2_R: 1353 case PLL3_P: 1354 case PLL3_Q: 1355 case PLL3_R: 1356 case CK_AXI: 1357 case CK_MPU: 1358 case CK_MCU: 1359 case RTC: 1360 return true; 1361 default: 1362 return false; 1363 } 1364 } 1365 1366 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1367 { 1368 const struct stm32mp1_clk_gate *gate; 1369 int i; 1370 1371 if (clock_is_always_on(id)) { 1372 return; 1373 } 1374 1375 i = stm32mp1_clk_get_gated_id(id); 1376 if (i < 0) { 1377 ERROR("Clock %lu can't be enabled\n", id); 1378 panic(); 1379 } 1380 1381 gate = gate_ref(i); 1382 1383 if (!with_refcnt) { 1384 __clk_enable(gate); 1385 return; 1386 } 1387 1388 #if defined(IMAGE_BL32) 1389 if (gate_is_non_secure(gate)) { 1390 /* Enable non-secure clock w/o any refcounting */ 1391 __clk_enable(gate); 1392 return; 1393 } 1394 #endif 1395 1396 stm32mp1_clk_lock(&refcount_lock); 1397 1398 if (gate_refcounts[i] == 0U) { 1399 __clk_enable(gate); 1400 } 1401 1402 gate_refcounts[i]++; 1403 if (gate_refcounts[i] == UINT_MAX) { 1404 ERROR("Clock %lu refcount reached max value\n", id); 1405 panic(); 1406 } 1407 1408 stm32mp1_clk_unlock(&refcount_lock); 1409 } 1410 1411 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1412 { 1413 const struct stm32mp1_clk_gate *gate; 1414 int i; 1415 1416 if (clock_is_always_on(id)) { 1417 return; 1418 } 1419 1420 i = stm32mp1_clk_get_gated_id(id); 1421 if (i < 0) { 1422 ERROR("Clock %lu can't be disabled\n", id); 1423 panic(); 1424 } 1425 1426 gate = gate_ref(i); 1427 1428 if (!with_refcnt) { 1429 __clk_disable(gate); 1430 return; 1431 } 1432 1433 #if defined(IMAGE_BL32) 1434 if (gate_is_non_secure(gate)) { 1435 /* Don't disable non-secure clocks */ 1436 return; 1437 } 1438 #endif 1439 1440 stm32mp1_clk_lock(&refcount_lock); 1441 1442 if (gate_refcounts[i] == 0U) { 1443 ERROR("Clock %lu refcount reached 0\n", id); 1444 panic(); 1445 } 1446 gate_refcounts[i]--; 1447 1448 if (gate_refcounts[i] == 0U) { 1449 __clk_disable(gate); 1450 } 1451 1452 stm32mp1_clk_unlock(&refcount_lock); 1453 } 1454 1455 static int stm32mp_clk_enable(unsigned long id) 1456 { 1457 __stm32mp1_clk_enable(id, true); 1458 1459 return 0; 1460 } 1461 1462 static void stm32mp_clk_disable(unsigned long id) 1463 { 1464 __stm32mp1_clk_disable(id, true); 1465 } 1466 1467 static bool stm32mp_clk_is_enabled(unsigned long id) 1468 { 1469 int i; 1470 1471 if (clock_is_always_on(id)) { 1472 return true; 1473 } 1474 1475 i = stm32mp1_clk_get_gated_id(id); 1476 if (i < 0) { 1477 panic(); 1478 } 1479 1480 return __clk_is_enabled(gate_ref(i)); 1481 } 1482 1483 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1484 { 1485 uintptr_t rcc_base = stm32mp_rcc_base(); 1486 int p = stm32mp1_clk_get_parent(id); 1487 uint32_t prescaler, timpre; 1488 unsigned long parent_rate; 1489 1490 if (p < 0) { 1491 return 0; 1492 } 1493 1494 parent_rate = get_clock_rate(p); 1495 1496 switch (id) { 1497 case TIM2_K: 1498 case TIM3_K: 1499 case TIM4_K: 1500 case TIM5_K: 1501 case TIM6_K: 1502 case TIM7_K: 1503 case TIM12_K: 1504 case TIM13_K: 1505 case TIM14_K: 1506 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1507 RCC_APBXDIV_MASK; 1508 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1509 RCC_TIMGXPRER_TIMGXPRE; 1510 break; 1511 1512 case TIM1_K: 1513 case TIM8_K: 1514 case TIM15_K: 1515 case TIM16_K: 1516 case TIM17_K: 1517 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1518 RCC_APBXDIV_MASK; 1519 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1520 RCC_TIMGXPRER_TIMGXPRE; 1521 break; 1522 1523 default: 1524 return parent_rate; 1525 } 1526 1527 if (prescaler == 0U) { 1528 return parent_rate; 1529 } 1530 1531 return parent_rate * (timpre + 1U) * 2U; 1532 } 1533 1534 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1535 { 1536 uintptr_t address = stm32mp_rcc_base() + offset; 1537 1538 if (enable) { 1539 mmio_setbits_32(address, mask_on); 1540 } else { 1541 mmio_clrbits_32(address, mask_on); 1542 } 1543 } 1544 1545 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1546 { 1547 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1548 uintptr_t address = stm32mp_rcc_base() + offset; 1549 1550 mmio_write_32(address, mask_on); 1551 } 1552 1553 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1554 { 1555 uint64_t timeout; 1556 uint32_t mask_test; 1557 uintptr_t address = stm32mp_rcc_base() + offset; 1558 1559 if (enable) { 1560 mask_test = mask_rdy; 1561 } else { 1562 mask_test = 0; 1563 } 1564 1565 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1566 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1567 if (timeout_elapsed(timeout)) { 1568 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1569 mask_rdy, address, enable, mmio_read_32(address)); 1570 return -ETIMEDOUT; 1571 } 1572 } 1573 1574 return 0; 1575 } 1576 1577 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1578 { 1579 uint32_t value; 1580 uintptr_t rcc_base = stm32mp_rcc_base(); 1581 1582 /* Do not reconfigure LSE if it is already ON */ 1583 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { 1584 return; 1585 } 1586 1587 if (digbyp) { 1588 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1589 } 1590 1591 if (bypass || digbyp) { 1592 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1593 } 1594 1595 /* 1596 * Warning: not recommended to switch directly from "high drive" 1597 * to "medium low drive", and vice-versa. 1598 */ 1599 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1600 RCC_BDCR_LSEDRV_SHIFT; 1601 1602 while (value != lsedrv) { 1603 if (value > lsedrv) { 1604 value--; 1605 } else { 1606 value++; 1607 } 1608 1609 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1610 RCC_BDCR_LSEDRV_MASK, 1611 value << RCC_BDCR_LSEDRV_SHIFT); 1612 } 1613 1614 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1615 } 1616 1617 static void stm32mp1_lse_wait(void) 1618 { 1619 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1620 EARLY_ERROR("%s: failed\n", __func__); 1621 } 1622 } 1623 1624 static void stm32mp1_lsi_set(bool enable) 1625 { 1626 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1627 1628 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1629 EARLY_ERROR("%s: failed\n", __func__); 1630 } 1631 } 1632 1633 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1634 { 1635 uintptr_t rcc_base = stm32mp_rcc_base(); 1636 1637 if (digbyp) { 1638 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1639 } 1640 1641 if (bypass || digbyp) { 1642 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1643 } 1644 1645 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1646 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1647 EARLY_ERROR("%s: failed\n", __func__); 1648 } 1649 1650 if (css) { 1651 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1652 } 1653 1654 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1655 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1656 (!(digbyp || bypass))) { 1657 panic(); 1658 } 1659 #endif 1660 } 1661 1662 static void stm32mp1_csi_set(bool enable) 1663 { 1664 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1665 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1666 EARLY_ERROR("%s: failed\n", __func__); 1667 } 1668 } 1669 1670 static void stm32mp1_hsi_set(bool enable) 1671 { 1672 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1673 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1674 EARLY_ERROR("%s: failed\n", __func__); 1675 } 1676 } 1677 1678 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1679 { 1680 uint64_t timeout; 1681 uintptr_t rcc_base = stm32mp_rcc_base(); 1682 uintptr_t address = rcc_base + RCC_OCRDYR; 1683 1684 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1685 RCC_HSICFGR_HSIDIV_MASK, 1686 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1687 1688 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1689 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1690 if (timeout_elapsed(timeout)) { 1691 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1692 address, mmio_read_32(address)); 1693 return -ETIMEDOUT; 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int stm32mp1_hsidiv(unsigned long hsifreq) 1701 { 1702 uint8_t hsidiv; 1703 uint32_t hsidivfreq = MAX_HSI_HZ; 1704 1705 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1706 if (hsidivfreq == hsifreq) { 1707 break; 1708 } 1709 1710 hsidivfreq /= 2U; 1711 } 1712 1713 if (hsidiv == 4U) { 1714 EARLY_ERROR("Invalid clk-hsi frequency\n"); 1715 return -1; 1716 } 1717 1718 if (hsidiv != 0U) { 1719 return stm32mp1_set_hsidiv(hsidiv); 1720 } 1721 1722 return 0; 1723 } 1724 1725 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1726 unsigned int clksrc, 1727 uint32_t *pllcfg, uint32_t fracv) 1728 { 1729 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1730 uintptr_t rcc_base = stm32mp_rcc_base(); 1731 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1732 enum stm32mp1_plltype type = pll->plltype; 1733 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1734 unsigned long refclk; 1735 uint32_t ifrge = 0U; 1736 uint32_t src, value; 1737 1738 /* Check PLL output */ 1739 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1740 return false; 1741 } 1742 1743 /* Check current clksrc */ 1744 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1745 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1746 return false; 1747 } 1748 1749 /* Check Div */ 1750 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1751 1752 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1753 (pllcfg[PLLCFG_M] + 1U); 1754 1755 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1756 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1757 return false; 1758 } 1759 1760 if ((type == PLL_800) && (refclk >= 8000000U)) { 1761 ifrge = 1U; 1762 } 1763 1764 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1765 RCC_PLLNCFGR1_DIVN_MASK; 1766 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1767 RCC_PLLNCFGR1_DIVM_MASK; 1768 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1769 RCC_PLLNCFGR1_IFRGE_MASK; 1770 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1771 return false; 1772 } 1773 1774 /* Fractional configuration */ 1775 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1776 value |= RCC_PLLNFRACR_FRACLE; 1777 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1778 return false; 1779 } 1780 1781 /* Output config */ 1782 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1783 RCC_PLLNCFGR2_DIVP_MASK; 1784 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1785 RCC_PLLNCFGR2_DIVQ_MASK; 1786 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1787 RCC_PLLNCFGR2_DIVR_MASK; 1788 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1789 return false; 1790 } 1791 1792 return true; 1793 } 1794 1795 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1796 { 1797 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1798 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1799 1800 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1801 mmio_clrsetbits_32(pllxcr, 1802 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1803 RCC_PLLNCR_DIVREN, 1804 RCC_PLLNCR_PLLON); 1805 } 1806 1807 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1808 { 1809 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1810 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1811 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1812 1813 /* Wait PLL lock */ 1814 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1815 if (timeout_elapsed(timeout)) { 1816 EARLY_ERROR("PLL%u start failed @ 0x%lx: 0x%x\n", 1817 pll_id, pllxcr, mmio_read_32(pllxcr)); 1818 return -ETIMEDOUT; 1819 } 1820 } 1821 1822 /* Start the requested output */ 1823 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1824 1825 return 0; 1826 } 1827 1828 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1829 { 1830 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1831 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1832 uint64_t timeout; 1833 1834 /* Stop all output */ 1835 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1836 RCC_PLLNCR_DIVREN); 1837 1838 /* Stop PLL */ 1839 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1840 1841 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1842 /* Wait PLL stopped */ 1843 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1844 if (timeout_elapsed(timeout)) { 1845 EARLY_ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n", 1846 pll_id, pllxcr, mmio_read_32(pllxcr)); 1847 return -ETIMEDOUT; 1848 } 1849 } 1850 1851 return 0; 1852 } 1853 1854 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1855 uint32_t *pllcfg) 1856 { 1857 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1858 uintptr_t rcc_base = stm32mp_rcc_base(); 1859 uint32_t value; 1860 1861 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1862 RCC_PLLNCFGR2_DIVP_MASK; 1863 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1864 RCC_PLLNCFGR2_DIVQ_MASK; 1865 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1866 RCC_PLLNCFGR2_DIVR_MASK; 1867 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1868 } 1869 1870 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1871 uint32_t *pllcfg, uint32_t fracv) 1872 { 1873 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1874 uintptr_t rcc_base = stm32mp_rcc_base(); 1875 enum stm32mp1_plltype type = pll->plltype; 1876 unsigned long refclk; 1877 uint32_t ifrge = 0; 1878 uint32_t src, value; 1879 1880 src = mmio_read_32(rcc_base + pll->rckxselr) & 1881 RCC_SELR_REFCLK_SRC_MASK; 1882 1883 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1884 (pllcfg[PLLCFG_M] + 1U); 1885 1886 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1887 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1888 return -EINVAL; 1889 } 1890 1891 if ((type == PLL_800) && (refclk >= 8000000U)) { 1892 ifrge = 1U; 1893 } 1894 1895 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1896 RCC_PLLNCFGR1_DIVN_MASK; 1897 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1898 RCC_PLLNCFGR1_DIVM_MASK; 1899 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1900 RCC_PLLNCFGR1_IFRGE_MASK; 1901 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1902 1903 /* Fractional configuration */ 1904 value = 0; 1905 mmio_write_32(rcc_base + pll->pllxfracr, value); 1906 1907 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1908 mmio_write_32(rcc_base + pll->pllxfracr, value); 1909 1910 value |= RCC_PLLNFRACR_FRACLE; 1911 mmio_write_32(rcc_base + pll->pllxfracr, value); 1912 1913 stm32mp1_pll_config_output(pll_id, pllcfg); 1914 1915 return 0; 1916 } 1917 1918 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1919 { 1920 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1921 uint32_t pllxcsg = 0; 1922 1923 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1924 RCC_PLLNCSGR_MOD_PER_MASK; 1925 1926 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1927 RCC_PLLNCSGR_INC_STEP_MASK; 1928 1929 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1930 RCC_PLLNCSGR_SSCG_MODE_MASK; 1931 1932 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1933 1934 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1935 RCC_PLLNCR_SSCG_CTRL); 1936 } 1937 1938 static int clk_compute_pll1_settings(unsigned long input_freq, 1939 uint32_t freq_khz, 1940 uint32_t *pllcfg, uint32_t *fracv) 1941 { 1942 unsigned long long best_diff = ULLONG_MAX; 1943 unsigned int divm; 1944 1945 /* Following parameters have always the same value */ 1946 pllcfg[PLLCFG_Q] = 0U; 1947 pllcfg[PLLCFG_R] = 0U; 1948 pllcfg[PLLCFG_O] = PQR(1, 0, 0); 1949 1950 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) { 1951 unsigned long post_divm = input_freq / divm; 1952 unsigned int divp; 1953 1954 if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) { 1955 continue; 1956 } 1957 1958 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { 1959 unsigned long long output_freq = freq_khz * 1000ULL; 1960 unsigned long long freq; 1961 unsigned long long divn; 1962 unsigned long long frac; 1963 unsigned int i; 1964 1965 freq = output_freq * divm * (divp + 1U); 1966 1967 divn = (freq / input_freq) - 1U; 1968 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { 1969 continue; 1970 } 1971 1972 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); 1973 1974 /* 2 loops to refine the fractional part */ 1975 for (i = 2U; i != 0U; i--) { 1976 unsigned long long diff; 1977 unsigned long long vco; 1978 1979 if (frac > FRAC_MAX) { 1980 break; 1981 } 1982 1983 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); 1984 1985 if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) { 1986 frac++; 1987 continue; 1988 } 1989 1990 freq = vco / (divp + 1U); 1991 if (output_freq < freq) { 1992 diff = freq - output_freq; 1993 } else { 1994 diff = output_freq - freq; 1995 } 1996 1997 if (diff < best_diff) { 1998 pllcfg[PLLCFG_M] = divm - 1U; 1999 pllcfg[PLLCFG_N] = (uint32_t)divn; 2000 pllcfg[PLLCFG_P] = divp; 2001 *fracv = (uint32_t)frac; 2002 2003 if (diff == 0U) { 2004 return 0; 2005 } 2006 2007 best_diff = diff; 2008 } 2009 2010 frac++; 2011 } 2012 } 2013 } 2014 2015 if (best_diff == ULLONG_MAX) { 2016 return -EINVAL; 2017 } 2018 2019 return 0; 2020 } 2021 2022 static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz, 2023 uint32_t *pllcfg, uint32_t *fracv) 2024 { 2025 unsigned long input_freq = 0UL; 2026 2027 assert(pllcfg != NULL); 2028 assert(fracv != NULL); 2029 2030 switch (clksrc) { 2031 case CLK_PLL12_HSI: 2032 input_freq = stm32mp_clk_get_rate(CK_HSI); 2033 break; 2034 case CLK_PLL12_HSE: 2035 input_freq = stm32mp_clk_get_rate(CK_HSE); 2036 break; 2037 default: 2038 break; 2039 } 2040 2041 if (input_freq == 0UL) { 2042 panic(); 2043 } 2044 2045 return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv); 2046 } 2047 2048 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) 2049 { 2050 struct stm32_clk_platdata *pdata = priv->pdata; 2051 uint32_t i; 2052 2053 for (i = 0U; i < pdata->nclkdiv; i++) { 2054 uint32_t div_id, div_n; 2055 uint32_t val; 2056 int ret; 2057 2058 val = pdata->clkdiv[i] & CMD_DATA_MASK; 2059 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; 2060 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 2061 2062 ret = clk_stm32_set_div(priv, div_id, div_n); 2063 if (ret != 0) { 2064 return ret; 2065 } 2066 } 2067 2068 return 0; 2069 } 2070 2071 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 2072 { 2073 uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 2074 uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; 2075 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 2076 struct stm32_clk_platdata *pdata = priv->pdata; 2077 2078 if (binding_id == RTC) { 2079 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 2080 2081 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || (enable != 0U)) { 2082 mmio_clrsetbits_32(address, RCC_BDCR_RTCSRC_MASK, 2083 (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 2084 2085 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 2086 /* Configure LSE CSS */ 2087 if (pdata->lse_css) { 2088 mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON); 2089 } 2090 } 2091 } 2092 2093 return 0; 2094 } 2095 2096 static int stm32_clk_configure_by_addr_val(struct stm32_clk_priv *priv, 2097 uint32_t data) 2098 { 2099 uint32_t addr = data >> CLK_ADDR_SHIFT; 2100 uint32_t val = data & CLK_ADDR_VAL_MASK; 2101 2102 mmio_setbits_32(priv->base + addr, val); 2103 2104 return 0; 2105 } 2106 2107 static int stm32_clk_source_configure(struct stm32_clk_priv *priv) 2108 { 2109 struct stm32_clk_platdata *pdata = priv->pdata; 2110 bool ckper_disabled = false; 2111 uint32_t i; 2112 2113 for (i = 0U; i < pdata->nclksrc; i++) { 2114 uint32_t val = pdata->clksrc[i]; 2115 uint32_t cmd, cmd_data; 2116 int ret; 2117 2118 if (val & CMD_ADDR_BIT) { 2119 ret = stm32_clk_configure_by_addr_val(priv, val & ~CMD_ADDR_BIT); 2120 if (ret != 0) { 2121 return ret; 2122 } 2123 2124 continue; 2125 } 2126 2127 if (val == (uint32_t)CLK_CKPER_DISABLED) { 2128 ckper_disabled = true; 2129 continue; 2130 } 2131 2132 cmd = (val & CMD_MASK) >> CMD_SHIFT; 2133 cmd_data = val & ~CMD_MASK; 2134 2135 switch (cmd) { 2136 case CMD_MUX: 2137 ret = stm32_clk_configure_mux(priv, cmd_data); 2138 break; 2139 2140 case CMD_CLK: 2141 ret = stm32_clk_configure_clk(priv, cmd_data); 2142 break; 2143 default: 2144 ret = -EINVAL; 2145 break; 2146 } 2147 2148 if (ret != 0) { 2149 return ret; 2150 } 2151 } 2152 2153 /* 2154 * CKPER is source for some peripheral clocks 2155 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2156 * only if previous clock is still ON 2157 * => deactivate CKPER only after switching clock 2158 */ 2159 if (!ckper_disabled) { 2160 return 0; 2161 } 2162 2163 return stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED); 2164 } 2165 2166 static int stm32mp1_pll_configure_src(struct stm32_clk_priv *priv, int pll_idx) 2167 { 2168 struct stm32_clk_platdata *pdata = priv->pdata; 2169 struct stm32_pll_dt_cfg *pll_conf = &pdata->pll[pll_idx]; 2170 2171 if (!pll_conf->status) { 2172 return 0; 2173 } 2174 2175 return stm32_clk_configure_mux(priv, pll_conf->src); 2176 } 2177 2178 int stm32mp1_clk_init(void) 2179 { 2180 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 2181 struct stm32_clk_platdata *pdata = priv->pdata; 2182 struct stm32_pll_dt_cfg *pll_conf = pdata->pll; 2183 int ret; 2184 enum stm32mp1_pll_id i; 2185 bool pll3_preserve = false; 2186 bool pll4_preserve = false; 2187 bool pll4_bootrom = false; 2188 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 2189 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 2190 uint32_t usbreg_bootrom = 0U; 2191 2192 if (!pll_conf[_PLL1].status) { 2193 ret = clk_get_pll1_settings(pll_conf[_PLL2].src, PLL1_NOMINAL_FREQ_IN_KHZ, 2194 pll_conf[_PLL1].cfg, &pll_conf[_PLL1].frac); 2195 if (ret != 0) { 2196 return ret; 2197 } 2198 2199 pll_conf[_PLL1].status = true; 2200 pll_conf[_PLL1].src = pll_conf[_PLL2].src; 2201 } 2202 2203 /* 2204 * Switch ON oscillator found in device-tree. 2205 * Note: HSI already ON after BootROM stage. 2206 */ 2207 if (stm32mp1_osc[_LSI] != 0U) { 2208 stm32mp1_lsi_set(true); 2209 } 2210 if (stm32mp1_osc[_LSE] != 0U) { 2211 const char *name = stm32mp_osc_node_label[_LSE]; 2212 bool bypass, digbyp; 2213 uint32_t lsedrv; 2214 2215 bypass = fdt_clk_read_bool(name, "st,bypass"); 2216 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2217 pdata->lse_css = fdt_clk_read_bool(name, "st,css"); 2218 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 2219 LSEDRV_MEDIUM_HIGH); 2220 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 2221 } 2222 if (stm32mp1_osc[_HSE] != 0U) { 2223 const char *name = stm32mp_osc_node_label[_HSE]; 2224 bool bypass, digbyp, css; 2225 2226 bypass = fdt_clk_read_bool(name, "st,bypass"); 2227 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2228 css = fdt_clk_read_bool(name, "st,css"); 2229 stm32mp1_hse_enable(bypass, digbyp, css); 2230 } 2231 /* 2232 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 2233 * => switch on CSI even if node is not present in device tree 2234 */ 2235 stm32mp1_csi_set(true); 2236 2237 /* Come back to HSI */ 2238 ret = stm32_clk_configure_mux(priv, CLK_MPU_HSI); 2239 if (ret != 0) { 2240 return ret; 2241 } 2242 ret = stm32_clk_configure_mux(priv, CLK_AXI_HSI); 2243 if (ret != 0) { 2244 return ret; 2245 } 2246 ret = stm32_clk_configure_mux(priv, CLK_MCU_HSI); 2247 if (ret != 0) { 2248 return ret; 2249 } 2250 if ((mmio_read_32(priv->base + RCC_MP_RSTSCLRR) & 2251 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 2252 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 2253 pll_conf[_PLL3].src, 2254 pll_conf[_PLL3].cfg, 2255 pll_conf[_PLL3].frac); 2256 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 2257 pll_conf[_PLL4].src, 2258 pll_conf[_PLL4].cfg, 2259 pll_conf[_PLL4].frac); 2260 } 2261 /* Don't initialize PLL4, when used by BOOTROM */ 2262 if ((stm32mp_get_boot_itf_selected() == 2263 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 2264 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 2265 pll4_bootrom = true; 2266 pll4_preserve = true; 2267 } 2268 2269 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2270 if (((i == _PLL3) && pll3_preserve) || 2271 ((i == _PLL4) && pll4_preserve)) { 2272 continue; 2273 } 2274 2275 ret = stm32mp1_pll_stop(i); 2276 if (ret != 0) { 2277 return ret; 2278 } 2279 } 2280 2281 /* Configure HSIDIV */ 2282 if (stm32mp1_osc[_HSI] != 0U) { 2283 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 2284 if (ret != 0) { 2285 return ret; 2286 } 2287 2288 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2289 } 2290 2291 /* Configure dividers */ 2292 ret = stm32_clk_dividers_configure(priv); 2293 if (ret != 0) { 2294 return ret; 2295 } 2296 2297 /* Configure PLLs source */ 2298 ret = stm32mp1_pll_configure_src(priv, _PLL1); 2299 if (ret != 0) { 2300 return ret; 2301 } 2302 2303 if (!pll3_preserve) { 2304 ret = stm32mp1_pll_configure_src(priv, _PLL3); 2305 if (ret != 0) { 2306 return ret; 2307 } 2308 } 2309 2310 if (!pll4_preserve) { 2311 ret = stm32mp1_pll_configure_src(priv, _PLL4); 2312 if (ret != 0) { 2313 return ret; 2314 } 2315 } 2316 2317 /* Configure and start PLLs */ 2318 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2319 if (((i == _PLL3) && pll3_preserve) || 2320 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2321 continue; 2322 } 2323 2324 if (!pll_conf[i].status) { 2325 continue; 2326 } 2327 2328 if ((i == _PLL4) && pll4_bootrom) { 2329 /* Set output divider if not done by the Bootrom */ 2330 stm32mp1_pll_config_output(i, pll_conf[i].cfg); 2331 continue; 2332 } 2333 2334 ret = stm32mp1_pll_config(i, pll_conf[i].cfg, pll_conf[i].frac); 2335 if (ret != 0) { 2336 return ret; 2337 } 2338 2339 if (pll_conf[i].csg_enabled) { 2340 stm32mp1_pll_csg(i, pll_conf[i].csg); 2341 } 2342 2343 stm32mp1_pll_start(i); 2344 } 2345 /* Wait and start PLLs output when ready */ 2346 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2347 if (!pll_conf[i].status) { 2348 continue; 2349 } 2350 2351 ret = stm32mp1_pll_output(i, pll_conf[i].cfg[PLLCFG_O]); 2352 if (ret != 0) { 2353 return ret; 2354 } 2355 } 2356 /* Wait LSE ready before to use it */ 2357 if (stm32mp1_osc[_LSE] != 0U) { 2358 stm32mp1_lse_wait(); 2359 } 2360 2361 if (pll4_bootrom) { 2362 usbreg_bootrom = mmio_read_32(priv->base + RCC_USBCKSELR); 2363 } 2364 2365 /* Configure with expected clock source */ 2366 ret = stm32_clk_source_configure(priv); 2367 if (ret != 0) { 2368 panic(); 2369 } 2370 2371 if (pll4_bootrom) { 2372 uint32_t usbreg_value, usbreg_mask; 2373 const struct stm32mp1_clk_sel *sel; 2374 2375 sel = clk_sel_ref(_USBPHY_SEL); 2376 usbreg_mask = (uint32_t)sel->msk << sel->src; 2377 sel = clk_sel_ref(_USBO_SEL); 2378 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2379 2380 usbreg_value = mmio_read_32(priv->base + RCC_USBCKSELR) & 2381 usbreg_mask; 2382 usbreg_bootrom &= usbreg_mask; 2383 if (usbreg_bootrom != usbreg_value) { 2384 EARLY_ERROR("forbidden new USB clk path\n"); 2385 EARLY_ERROR("vs bootrom on USB boot\n"); 2386 return -FDT_ERR_BADVALUE; 2387 } 2388 } 2389 2390 /* Switch OFF HSI if not found in device-tree */ 2391 if (stm32mp1_osc[_HSI] == 0U) { 2392 stm32mp1_hsi_set(false); 2393 } 2394 2395 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2396 2397 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2398 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 2399 RCC_DDRITFCR_DDRCKMOD_MASK, 2400 RCC_DDRITFCR_DDRCKMOD_SSR << 2401 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2402 2403 return 0; 2404 } 2405 2406 static void stm32mp1_osc_clk_init(const char *name, 2407 enum stm32mp_osc_id index) 2408 { 2409 uint32_t frequency; 2410 2411 if (fdt_osc_read_freq(name, &frequency) == 0) { 2412 stm32mp1_osc[index] = frequency; 2413 } 2414 } 2415 2416 static void stm32mp1_osc_init(void) 2417 { 2418 enum stm32mp_osc_id i; 2419 2420 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2421 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2422 } 2423 } 2424 2425 #ifdef STM32MP_SHARED_RESOURCES 2426 /* 2427 * Get the parent ID of the target parent clock, for tagging as secure 2428 * shared clock dependencies. 2429 */ 2430 static int get_parent_id_parent(unsigned int parent_id) 2431 { 2432 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2433 enum stm32mp1_pll_id pll_id; 2434 uint32_t p_sel; 2435 uintptr_t rcc_base = stm32mp_rcc_base(); 2436 2437 switch (parent_id) { 2438 case _ACLK: 2439 case _PCLK4: 2440 case _PCLK5: 2441 s = _AXIS_SEL; 2442 break; 2443 case _PLL1_P: 2444 case _PLL1_Q: 2445 case _PLL1_R: 2446 pll_id = _PLL1; 2447 break; 2448 case _PLL2_P: 2449 case _PLL2_Q: 2450 case _PLL2_R: 2451 pll_id = _PLL2; 2452 break; 2453 case _PLL3_P: 2454 case _PLL3_Q: 2455 case _PLL3_R: 2456 pll_id = _PLL3; 2457 break; 2458 case _PLL4_P: 2459 case _PLL4_Q: 2460 case _PLL4_R: 2461 pll_id = _PLL4; 2462 break; 2463 case _PCLK1: 2464 case _PCLK2: 2465 case _HCLK2: 2466 case _HCLK6: 2467 case _CK_PER: 2468 case _CK_MPU: 2469 case _CK_MCU: 2470 case _USB_PHY_48: 2471 /* We do not expect to access these */ 2472 panic(); 2473 break; 2474 default: 2475 /* Other parents have no parent */ 2476 return -1; 2477 } 2478 2479 if (s != _UNKNOWN_SEL) { 2480 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2481 2482 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2483 sel->msk; 2484 2485 if (p_sel < sel->nb_parent) { 2486 return (int)sel->parent[p_sel]; 2487 } 2488 } else { 2489 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2490 2491 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2492 RCC_SELR_REFCLK_SRC_MASK; 2493 2494 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2495 return (int)pll->refclk[p_sel]; 2496 } 2497 } 2498 2499 VERBOSE("No parent selected for %s\n", 2500 stm32mp1_clk_parent_name[parent_id]); 2501 2502 return -1; 2503 } 2504 2505 static void secure_parent_clocks(unsigned long parent_id) 2506 { 2507 int grandparent_id; 2508 2509 switch (parent_id) { 2510 case _PLL3_P: 2511 case _PLL3_Q: 2512 case _PLL3_R: 2513 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2514 break; 2515 2516 /* These clocks are always secure when RCC is secure */ 2517 case _ACLK: 2518 case _HCLK2: 2519 case _HCLK6: 2520 case _PCLK4: 2521 case _PCLK5: 2522 case _PLL1_P: 2523 case _PLL1_Q: 2524 case _PLL1_R: 2525 case _PLL2_P: 2526 case _PLL2_Q: 2527 case _PLL2_R: 2528 case _HSI: 2529 case _HSI_KER: 2530 case _LSI: 2531 case _CSI: 2532 case _CSI_KER: 2533 case _HSE: 2534 case _HSE_KER: 2535 case _HSE_KER_DIV2: 2536 case _HSE_RTC: 2537 case _LSE: 2538 break; 2539 2540 default: 2541 VERBOSE("Cannot secure parent clock %s\n", 2542 stm32mp1_clk_parent_name[parent_id]); 2543 panic(); 2544 } 2545 2546 grandparent_id = get_parent_id_parent(parent_id); 2547 if (grandparent_id >= 0) { 2548 secure_parent_clocks(grandparent_id); 2549 } 2550 } 2551 2552 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2553 { 2554 int parent_id; 2555 2556 if (!stm32mp1_rcc_is_secure()) { 2557 return; 2558 } 2559 2560 switch (clock_id) { 2561 case PLL1: 2562 case PLL2: 2563 /* PLL1/PLL2 are always secure: nothing to do */ 2564 break; 2565 case PLL3: 2566 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2567 break; 2568 case PLL4: 2569 ERROR("PLL4 cannot be secured\n"); 2570 panic(); 2571 break; 2572 default: 2573 /* Others are expected gateable clock */ 2574 parent_id = stm32mp1_clk_get_parent(clock_id); 2575 if (parent_id < 0) { 2576 INFO("No parent found for clock %lu\n", clock_id); 2577 } else { 2578 secure_parent_clocks(parent_id); 2579 } 2580 break; 2581 } 2582 } 2583 #endif /* STM32MP_SHARED_RESOURCES */ 2584 2585 void stm32mp1_clk_mcuss_protect(bool enable) 2586 { 2587 uintptr_t rcc_base = stm32mp_rcc_base(); 2588 2589 if (enable) { 2590 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2591 } else { 2592 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2593 } 2594 } 2595 2596 static void sync_earlyboot_clocks_state(void) 2597 { 2598 unsigned int idx; 2599 const unsigned long secure_enable[] = { 2600 AXIDCG, 2601 BSEC, 2602 DDRC1, DDRC1LP, 2603 DDRC2, DDRC2LP, 2604 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2605 DDRPHYC, DDRPHYCLP, 2606 RTCAPB, 2607 TZC1, TZC2, 2608 TZPC, 2609 STGEN_K, 2610 }; 2611 2612 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2613 stm32mp_clk_enable(secure_enable[idx]); 2614 } 2615 } 2616 2617 static const struct clk_ops stm32mp_clk_ops = { 2618 .enable = stm32mp_clk_enable, 2619 .disable = stm32mp_clk_disable, 2620 .is_enabled = stm32mp_clk_is_enabled, 2621 .get_rate = stm32mp_clk_get_rate, 2622 .get_parent = stm32mp1_clk_get_parent, 2623 }; 2624 2625 struct stm32_pll_dt_cfg mp15_pll[_PLL_NB]; 2626 uint32_t mp15_clksrc[MUX_NB]; 2627 uint32_t mp15_clkdiv[DIV_NB]; 2628 2629 struct stm32_clk_platdata stm32mp15_clock_pdata = { 2630 .pll = mp15_pll, 2631 .npll = _PLL_NB, 2632 .clksrc = mp15_clksrc, 2633 .nclksrc = MUX_NB, 2634 .clkdiv = mp15_clkdiv, 2635 .nclkdiv = DIV_NB, 2636 }; 2637 2638 static struct stm32_clk_priv stm32mp15_clock_data = { 2639 .base = RCC_BASE, 2640 .parents = parent_mp15, 2641 .nb_parents = ARRAY_SIZE(parent_mp15), 2642 .div = dividers_mp15, 2643 .nb_div = ARRAY_SIZE(dividers_mp15), 2644 .pdata = &stm32mp15_clock_pdata, 2645 }; 2646 2647 static int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, 2648 uint32_t *tab, uint32_t *nb) 2649 { 2650 const fdt32_t *cell; 2651 int len = 0; 2652 uint32_t i; 2653 2654 cell = fdt_getprop(fdt, node, name, &len); 2655 if (cell == NULL) { 2656 *nb = 0U; 2657 return 0; 2658 } 2659 2660 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 2661 tab[i] = fdt32_to_cpu(cell[i]); 2662 } 2663 2664 *nb = (uint32_t)len / sizeof(uint32_t); 2665 2666 return 0; 2667 } 2668 2669 #define RCC_PLL_NAME_SIZE 12 2670 2671 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2672 { 2673 int err; 2674 2675 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, &pll->cfg[PLLCFG_M]); 2676 if (err != 0) { 2677 return err; 2678 } 2679 2680 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg); 2681 if (err == 0) { 2682 pll->csg_enabled = true; 2683 } else if (err == -FDT_ERR_NOTFOUND) { 2684 pll->csg_enabled = false; 2685 } else { 2686 return err; 2687 } 2688 2689 pll->status = true; 2690 2691 pll->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); 2692 2693 pll->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); 2694 2695 return 0; 2696 } 2697 2698 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2699 { 2700 int err; 2701 2702 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB, 2703 &pll->cfg[PLLCFG_P]); 2704 if (err != 0) { 2705 return err; 2706 } 2707 2708 pll->cfg[PLLCFG_O] = PQR(1, 1, 1); 2709 2710 return 0; 2711 } 2712 2713 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2714 { 2715 const fdt32_t *cuint; 2716 int subnode_pll; 2717 int subnode_vco; 2718 int err; 2719 2720 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2721 if (cuint == NULL) { 2722 /* Case of no pll is defined */ 2723 return 0; 2724 } 2725 2726 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2727 if (subnode_pll < 0) { 2728 return -FDT_ERR_NOTFOUND; 2729 } 2730 2731 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); 2732 if (cuint == NULL) { 2733 return -FDT_ERR_NOTFOUND; 2734 } 2735 2736 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2737 if (subnode_vco < 0) { 2738 return -FDT_ERR_NOTFOUND; 2739 } 2740 2741 err = clk_stm32_load_vco_config(fdt, subnode_vco, pll); 2742 if (err != 0) { 2743 return err; 2744 } 2745 2746 err = clk_stm32_load_output_config(fdt, subnode_pll, pll); 2747 if (err != 0) { 2748 return err; 2749 } 2750 2751 return 0; 2752 } 2753 2754 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2755 { 2756 size_t i = 0U; 2757 2758 for (i = _PLL1; i < pdata->npll; i++) { 2759 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 2760 char name[RCC_PLL_NAME_SIZE]; 2761 int subnode; 2762 int err; 2763 2764 snprintf(name, sizeof(name), "st,pll@%u", i); 2765 2766 subnode = fdt_subnode_offset(fdt, node, name); 2767 if (!fdt_check_node(subnode)) { 2768 continue; 2769 } 2770 2771 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2772 if (err != 0) { 2773 panic(); 2774 } 2775 } 2776 2777 return 0; 2778 } 2779 2780 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2781 { 2782 void *fdt = NULL; 2783 int node; 2784 uint32_t err; 2785 2786 if (fdt_get_address(&fdt) == 0) { 2787 return -ENOENT; 2788 } 2789 2790 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2791 if (node < 0) { 2792 panic(); 2793 } 2794 2795 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2796 if (err != 0) { 2797 return err; 2798 } 2799 2800 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv); 2801 if (err != 0) { 2802 return err; 2803 } 2804 2805 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc); 2806 if (err != 0) { 2807 return err; 2808 } 2809 2810 return 0; 2811 } 2812 2813 int stm32mp1_clk_probe(void) 2814 { 2815 uintptr_t base = RCC_BASE; 2816 int ret; 2817 2818 #if defined(IMAGE_BL32) 2819 if (!fdt_get_rcc_secure_state()) { 2820 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); 2821 } 2822 #endif 2823 2824 stm32mp1_osc_init(); 2825 2826 ret = stm32_clk_parse_fdt(&stm32mp15_clock_pdata); 2827 if (ret != 0) { 2828 return ret; 2829 } 2830 2831 ret = clk_stm32_init(&stm32mp15_clock_data, base); 2832 if (ret != 0) { 2833 return ret; 2834 } 2835 2836 sync_earlyboot_clocks_state(); 2837 2838 clk_register(&stm32mp_clk_ops); 2839 2840 return 0; 2841 } 2842