1 /* 2 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include "clk-stm32-core.h" 13 #include <common/fdt_wrappers.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/st/stm32mp2_clk.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <lib/mmio.h> 20 #include <lib/spinlock.h> 21 #include <lib/utils_def.h> 22 #include <libfdt.h> 23 24 #include <platform_def.h> 25 26 struct stm32_osci_dt_cfg { 27 unsigned long freq; 28 uint32_t drive; 29 bool bypass; 30 bool digbyp; 31 bool css; 32 }; 33 34 struct stm32_pll_dt_cfg { 35 uint32_t src; 36 uint32_t frac; 37 uint32_t cfg[PLLCFG_NB]; 38 uint32_t csg[PLLCSG_NB]; 39 bool csg_enabled; 40 bool enabled; 41 }; 42 43 struct stm32_clk_platdata { 44 uintptr_t rcc_base; 45 uint32_t nosci; 46 struct stm32_osci_dt_cfg *osci; 47 uint32_t npll; 48 struct stm32_pll_dt_cfg *pll; 49 uint32_t nflexgen; 50 uint32_t *flexgen; 51 uint32_t nbusclk; 52 uint32_t *busclk; 53 uint32_t nkernelclk; 54 uint32_t *kernelclk; 55 }; 56 57 /* A35 Sub-System which manages its own PLL (PLL1) */ 58 #define A35_SS_CHGCLKREQ 0x0000 59 #define A35_SS_PLL_FREQ1 0x0080 60 #define A35_SS_PLL_FREQ2 0x0090 61 #define A35_SS_PLL_ENABLE 0x00a0 62 63 #define A35_SS_CHGCLKREQ_ARM_CHGCLKREQ BIT(0) 64 #define A35_SS_CHGCLKREQ_ARM_CHGCLKACK BIT(1) 65 66 #define A35_SS_PLL_FREQ1_FBDIV_MASK GENMASK(11, 0) 67 #define A35_SS_PLL_FREQ1_FBDIV_SHIFT 0 68 #define A35_SS_PLL_FREQ1_REFDIV_MASK GENMASK(21, 16) 69 #define A35_SS_PLL_FREQ1_REFDIV_SHIFT 16 70 71 #define A35_SS_PLL_FREQ2_POSTDIV1_MASK GENMASK(2, 0) 72 #define A35_SS_PLL_FREQ2_POSTDIV1_SHIFT 0 73 #define A35_SS_PLL_FREQ2_POSTDIV2_MASK GENMASK(5, 3) 74 #define A35_SS_PLL_FREQ2_POSTDIV2_SHIFT 3 75 76 #define A35_SS_PLL_ENABLE_PD BIT(0) 77 #define A35_SS_PLL_ENABLE_LOCKP BIT(1) 78 #define A35_SS_PLL_ENABLE_NRESET_SWPLL_FF BIT(2) 79 80 #define TIMEOUT_US_200MS U(200000) 81 #define TIMEOUT_US_1S U(1000000) 82 83 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 84 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 85 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 86 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 87 88 /* PLL minimal frequencies for clock sources */ 89 #define PLL_REFCLK_MIN UL(5000000) 90 #define PLL_FRAC_REFCLK_MIN UL(10000000) 91 92 #define XBAR_CHANNEL_NB 64 93 94 /* Warning, should be start to 1 */ 95 enum clock { 96 _CK_0_MHZ, 97 98 /* ROOT CLOCKS */ 99 _CK_HSI, 100 _CK_HSE, 101 _CK_MSI, 102 _CK_LSI, 103 _CK_LSE, 104 _I2SCKIN, 105 _SPDIFSYMB, 106 _CK_PLL1, 107 _CK_PLL2, 108 #if !STM32MP21 109 _CK_PLL3, 110 #endif /* !STM32MP21 */ 111 _CK_PLL4, 112 _CK_PLL5, 113 _CK_PLL6, 114 _CK_PLL7, 115 _CK_PLL8, 116 _CK_HSE_RTC, 117 _CK_RTCCK, 118 _CK_ICN_HS_MCU, 119 _CK_ICN_SDMMC, 120 _CK_ICN_DDR, 121 _CK_ICN_HSL, 122 _CK_ICN_NIC, 123 _CK_ICN_LS_MCU, 124 _CK_FLEXGEN_07, 125 _CK_FLEXGEN_08, 126 _CK_FLEXGEN_09, 127 _CK_FLEXGEN_10, 128 _CK_FLEXGEN_11, 129 _CK_FLEXGEN_12, 130 _CK_FLEXGEN_13, 131 _CK_FLEXGEN_14, 132 _CK_FLEXGEN_15, 133 _CK_FLEXGEN_16, 134 _CK_FLEXGEN_17, 135 _CK_FLEXGEN_18, 136 _CK_FLEXGEN_19, 137 _CK_FLEXGEN_20, 138 _CK_FLEXGEN_21, 139 _CK_FLEXGEN_22, 140 _CK_FLEXGEN_23, 141 _CK_FLEXGEN_24, 142 _CK_FLEXGEN_25, 143 _CK_FLEXGEN_26, 144 _CK_FLEXGEN_27, 145 _CK_FLEXGEN_28, 146 _CK_FLEXGEN_29, 147 _CK_FLEXGEN_30, 148 _CK_FLEXGEN_31, 149 _CK_FLEXGEN_32, 150 _CK_FLEXGEN_33, 151 _CK_FLEXGEN_34, 152 _CK_FLEXGEN_35, 153 _CK_FLEXGEN_36, 154 _CK_FLEXGEN_37, 155 _CK_FLEXGEN_38, 156 _CK_FLEXGEN_39, 157 _CK_FLEXGEN_40, 158 _CK_FLEXGEN_41, 159 _CK_FLEXGEN_42, 160 _CK_FLEXGEN_43, 161 _CK_FLEXGEN_44, 162 _CK_FLEXGEN_45, 163 _CK_FLEXGEN_46, 164 _CK_FLEXGEN_47, 165 _CK_FLEXGEN_48, 166 _CK_FLEXGEN_49, 167 _CK_FLEXGEN_50, 168 _CK_FLEXGEN_51, 169 _CK_FLEXGEN_52, 170 _CK_FLEXGEN_53, 171 _CK_FLEXGEN_54, 172 _CK_FLEXGEN_55, 173 _CK_FLEXGEN_56, 174 _CK_FLEXGEN_57, 175 _CK_FLEXGEN_58, 176 _CK_FLEXGEN_59, 177 _CK_FLEXGEN_60, 178 _CK_FLEXGEN_61, 179 _CK_FLEXGEN_62, 180 _CK_FLEXGEN_63, 181 _CK_ICN_APB1, 182 _CK_ICN_APB2, 183 _CK_ICN_APB3, 184 _CK_ICN_APB4, 185 #if STM32MP21 186 _CK_ICN_APB5, 187 #endif /* STM32MP21 */ 188 _CK_ICN_APBDBG, 189 _CK_BKPSRAM, 190 _CK_BSEC, 191 _CK_CRC, 192 _CK_CRYP1, 193 _CK_CRYP2, 194 _CK_DDR, 195 _CK_DDRCAPB, 196 _CK_DDRCP, 197 _CK_DDRPHYC, 198 _CK_FMC, 199 _CK_GPIOA, 200 _CK_GPIOB, 201 _CK_GPIOC, 202 _CK_GPIOD, 203 _CK_GPIOE, 204 _CK_GPIOF, 205 _CK_GPIOG, 206 _CK_GPIOH, 207 _CK_GPIOI, 208 #if !STM32MP21 209 _CK_GPIOJ, 210 _CK_GPIOK, 211 #endif /* !STM32MP21 */ 212 _CK_GPIOZ, 213 #if STM32MP21 214 _CK_HASH1, 215 _CK_HASH2, 216 #else /* STM32MP21 */ 217 _CK_HASH, 218 #endif /* STM32MP21 */ 219 _CK_I2C1, 220 _CK_I2C2, 221 #if !STM32MP23 222 _CK_I2C3, 223 #endif /* !STM32MP23 */ 224 #if STM32MP25 225 _CK_I2C4, 226 _CK_I2C5, 227 _CK_I2C6, 228 #endif /* STM32MP25 */ 229 #if !STM32MP21 230 _CK_I2C7, 231 _CK_I2C8, 232 #endif /* !STM32MP21 */ 233 _CK_IWDG1, 234 _CK_IWDG2, 235 _CK_OSPI1, 236 #if !STM32MP21 237 _CK_OSPI2, 238 _CK_OSPIIOM, 239 #endif /* !STM32MP21 */ 240 _CK_PKA, 241 _CK_RETRAM, 242 #if STM32MP21 243 _CK_RNG1, 244 _CK_RNG2, 245 #else /* STM32MP21 */ 246 _CK_RNG, 247 #endif /* STM32MP21 */ 248 _CK_RTC, 249 _CK_SAES, 250 _CK_SDMMC1, 251 _CK_SDMMC2, 252 _CK_SRAM1, 253 #if !STM32MP21 254 _CK_SRAM2, 255 #endif /* !STM32MP21 */ 256 _CK_STGEN, 257 _CK_SYSCPU1, 258 _CK_SYSRAM, 259 _CK_UART4, 260 _CK_UART5, 261 _CK_UART7, 262 #if STM32MP25 263 _CK_UART8, 264 _CK_UART9, 265 #endif /* STM32MP25 */ 266 _CK_USART1, 267 _CK_USART2, 268 _CK_USART3, 269 _CK_USART6, 270 #if STM32MP21 271 _CK_USBHEHCI, 272 _CK_USBHOHCI, 273 #else /* STM32MP21 */ 274 _CK_USB2EHCI, 275 _CK_USB2OHCI, 276 #endif /* STM32MP21 */ 277 _CK_USB2PHY1, 278 _CK_USB2PHY2, 279 #if !STM32MP21 280 _CK_USB3DR, 281 _CK_USB3PCIEPHY, 282 _CK_USBTC, 283 #endif /* !STM32MP21 */ 284 285 CK_LAST 286 }; 287 288 static const uint16_t muxsel_src[] = { 289 _CK_HSI, _CK_HSE, _CK_MSI, _CK_0_MHZ 290 }; 291 292 static const uint16_t xbarsel_src[] = { 293 _CK_PLL4, _CK_PLL5, _CK_PLL6, _CK_PLL7, _CK_PLL8, 294 _CK_HSI, _CK_HSE, _CK_MSI, _CK_HSI, _CK_HSE, _CK_MSI, 295 _SPDIFSYMB, _I2SCKIN, _CK_LSI, _CK_LSE 296 }; 297 298 static const uint16_t rtc_src[] = { 299 _CK_0_MHZ, _CK_LSE, _CK_LSI, _CK_HSE_RTC 300 }; 301 302 static const uint16_t usb2phy1_src[] = { 303 _CK_FLEXGEN_57, _CK_HSE 304 }; 305 306 static const uint16_t usb2phy2_src[] = { 307 _CK_FLEXGEN_58, _CK_HSE 308 }; 309 310 #if !STM32MP21 311 static const uint16_t usb3pciphy_src[] = { 312 _CK_FLEXGEN_34, _CK_HSE 313 }; 314 315 static const uint16_t d3per_src[] = { 316 _CK_MSI, _CK_LSI, _CK_LSE 317 }; 318 #endif /* !STM32MP21 */ 319 320 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\ 321 .id_parents = src,\ 322 .num_parents = ARRAY_SIZE(src),\ 323 .mux = &(struct mux_cfg) {\ 324 .offset = (_offset),\ 325 .shift = (_shift),\ 326 .width = (_witdh),\ 327 .bitrdy = UINT8_MAX,\ 328 },\ 329 } 330 331 static const struct parent_cfg parent_mp2[] = { 332 MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2), 333 MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2), 334 MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2), 335 MUX_CONF(MUX_MUXSEL3, muxsel_src, RCC_MUXSELCFGR, 12, 2), 336 MUX_CONF(MUX_MUXSEL4, muxsel_src, RCC_MUXSELCFGR, 16, 2), 337 MUX_CONF(MUX_MUXSEL5, muxsel_src, RCC_MUXSELCFGR, 20, 2), 338 MUX_CONF(MUX_MUXSEL6, muxsel_src, RCC_MUXSELCFGR, 24, 2), 339 MUX_CONF(MUX_MUXSEL7, muxsel_src, RCC_MUXSELCFGR, 28, 2), 340 MUX_CONF(MUX_XBARSEL, xbarsel_src, RCC_XBAR0CFGR, 0, 4), 341 MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2), 342 MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1), 343 MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1), 344 #if !STM32MP21 345 MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1), 346 MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2), 347 #endif /* !STM32MP21 */ 348 }; 349 350 /* GATES */ 351 enum enum_gate_cfg { 352 GATE_ZERO, /* reserved for no gate */ 353 GATE_LSE, 354 GATE_RTCCK, 355 GATE_LSI, 356 GATE_HSI, 357 GATE_MSI, 358 GATE_HSE, 359 GATE_LSI_RDY, 360 GATE_MSI_RDY, 361 GATE_LSE_RDY, 362 GATE_HSE_RDY, 363 GATE_HSI_RDY, 364 GATE_SYSRAM, 365 GATE_RETRAM, 366 GATE_SRAM1, 367 #if !STM32MP21 368 GATE_SRAM2, 369 #endif /* !STM32MP21 */ 370 371 GATE_DDRPHYC, 372 GATE_SYSCPU1, 373 GATE_CRC, 374 #if !STM32MP21 375 GATE_OSPIIOM, 376 #endif /* !STM32MP21 */ 377 GATE_BKPSRAM, 378 #if STM32MP21 379 GATE_HASH1, 380 GATE_HASH2, 381 GATE_RNG1, 382 GATE_RNG2, 383 #else /* STM32MP21 */ 384 GATE_HASH, 385 GATE_RNG, 386 #endif /* STM32MP21 */ 387 GATE_CRYP1, 388 GATE_CRYP2, 389 GATE_SAES, 390 GATE_PKA, 391 392 GATE_GPIOA, 393 GATE_GPIOB, 394 GATE_GPIOC, 395 GATE_GPIOD, 396 GATE_GPIOE, 397 GATE_GPIOF, 398 GATE_GPIOG, 399 GATE_GPIOH, 400 GATE_GPIOI, 401 #if !STM32MP21 402 GATE_GPIOJ, 403 GATE_GPIOK, 404 #endif /* !STM32MP21 */ 405 GATE_GPIOZ, 406 GATE_RTC, 407 408 GATE_DDRCP, 409 410 /* WARNING 2 CLOCKS FOR ONE GATE */ 411 #if STM32MP21 412 GATE_USBHOHCI, 413 GATE_USBHEHCI, 414 #else /* STM32MP21 */ 415 GATE_USB2OHCI, 416 GATE_USB2EHCI, 417 #endif /* STM32MP21 */ 418 419 #if !STM32MP21 420 GATE_USB3DR, 421 #endif /* !STM32MP21 */ 422 423 GATE_BSEC, 424 GATE_IWDG1, 425 GATE_IWDG2, 426 427 GATE_DDRCAPB, 428 GATE_DDR, 429 430 GATE_USART2, 431 GATE_UART4, 432 GATE_USART3, 433 GATE_UART5, 434 GATE_I2C1, 435 GATE_I2C2, 436 #if !STM32MP23 437 GATE_I2C3, 438 #endif /* !STM32MP23 */ 439 #if STM32MP25 440 GATE_I2C5, 441 GATE_I2C4, 442 GATE_I2C6, 443 #endif /* STM32MP25 */ 444 #if !STM32MP21 445 GATE_I2C7, 446 #endif /* !STM32MP21 */ 447 GATE_USART1, 448 GATE_USART6, 449 GATE_UART7, 450 #if STM32MP25 451 GATE_UART8, 452 GATE_UART9, 453 #endif /* STM32MP25 */ 454 GATE_STGEN, 455 #if !STM32MP21 456 GATE_USB3PCIEPHY, 457 GATE_USBTC, 458 GATE_I2C8, 459 #endif /* !STM32MP21 */ 460 GATE_OSPI1, 461 #if !STM32MP21 462 GATE_OSPI2, 463 #endif /* !STM32MP21 */ 464 GATE_FMC, 465 GATE_SDMMC1, 466 GATE_SDMMC2, 467 GATE_USB2PHY1, 468 GATE_USB2PHY2, 469 LAST_GATE 470 }; 471 472 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ 473 .offset = (_offset),\ 474 .bit_idx = (_bit_idx),\ 475 .set_clr = (_offset_clr),\ 476 } 477 478 static const struct gate_cfg gates_mp2[LAST_GATE] = { 479 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 480 #if STM32MP21 481 GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0), 482 #else /* STM32MP21 */ 483 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0), 484 #endif /* STM32MP21 */ 485 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 486 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 487 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 488 #if STM32MP21 489 GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0), 490 #else /* STM32MP21 */ 491 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0), 492 #endif /* STM32MP21 */ 493 494 #if STM32MP21 495 GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0), 496 #else /* STM32MP21 */ 497 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0), 498 #endif /* STM32MP21 */ 499 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 500 #if STM32MP21 501 GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0), 502 #else /* STM32MP21 */ 503 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0), 504 #endif /* STM32MP21 */ 505 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 506 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 507 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0), 508 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0), 509 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0), 510 #if !STM32MP21 511 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0), 512 #endif /* !STM32MP21 */ 513 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0), 514 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0), 515 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 516 #if !STM32MP21 517 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), 518 #endif /* !STM32MP21 */ 519 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0), 520 #if STM32MP21 521 GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0), 522 GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0), 523 GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0), 524 GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0), 525 #else /* STM32MP21 */ 526 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), 527 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), 528 #endif /* STM32MP21 */ 529 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 530 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 531 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 532 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 533 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0), 534 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0), 535 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0), 536 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0), 537 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0), 538 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0), 539 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0), 540 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0), 541 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0), 542 #if !STM32MP21 543 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0), 544 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0), 545 #endif /* !STM32MP21 */ 546 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0), 547 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0), 548 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0), 549 550 /* WARNING 2 CLOCKS FOR ONE GATE */ 551 #if STM32MP21 552 GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0), 553 GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0), 554 #else /* STM32MP21 */ 555 GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0), 556 GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0), 557 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), 558 #endif /* STM32MP21 */ 559 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0), 560 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 561 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 562 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0), 563 GATE_CFG(GATE_DDR, RCC_DDRCFGR, 1, 0), 564 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 565 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 566 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 567 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 568 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 569 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 570 #if !STM32MP23 571 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 572 #endif /* !STM32MP23 */ 573 #if STM32MP25 574 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), 575 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), 576 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), 577 #endif /* STM32MP25 */ 578 #if !STM32MP21 579 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), 580 #endif /* !STM32MP21 */ 581 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 582 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 583 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 584 #if STM32MP25 585 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), 586 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), 587 #endif /* STM32MP25 */ 588 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), 589 #if !STM32MP21 590 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), 591 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0), 592 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), 593 #endif /* !STM32MP21 */ 594 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), 595 #if !STM32MP21 596 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), 597 #endif /* !STM32MP21 */ 598 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0), 599 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 600 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 601 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 602 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 603 }; 604 605 static const struct clk_div_table apb_div_table[] = { 606 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 }, 607 { 5, 16 }, { 6, 16 }, { 7, 16 }, { 0 }, 608 }; 609 610 #undef DIV_CFG 611 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ 612 .offset = _offset,\ 613 .shift = _shift,\ 614 .width = _width,\ 615 .flags = _flags,\ 616 .table = _table,\ 617 .bitrdy = _bitrdy,\ 618 } 619 620 static const struct div_cfg dividers_mp2[] = { 621 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), 622 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), 623 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), 624 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), 625 #if STM32MP21 626 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31), 627 #endif /* STM32MP21 */ 628 DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31), 629 DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31), 630 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0), 631 }; 632 633 enum stm32_osc { 634 OSC_HSI, 635 OSC_HSE, 636 OSC_MSI, 637 OSC_LSI, 638 OSC_LSE, 639 OSC_I2SCKIN, 640 OSC_SPDIFSYMB, 641 NB_OSCILLATOR 642 }; 643 644 static struct clk_oscillator_data stm32mp2_osc_data[] = { 645 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, 646 NULL, NULL, NULL), 647 648 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, 649 NULL, NULL, NULL), 650 651 OSCILLATOR(OSC_MSI, _CK_MSI, "clk-msi", GATE_MSI, GATE_MSI_RDY, 652 NULL, NULL, NULL), 653 654 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, 655 BYPASS(RCC_OCENSETR, 10, 7), 656 CSS(RCC_OCENSETR, 11), 657 NULL), 658 659 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, 660 BYPASS(RCC_BDCR, 1, 3), 661 CSS(RCC_BDCR, 8), 662 DRIVE(RCC_BDCR, 4, 2, 2)), 663 664 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, 665 NULL, NULL, NULL), 666 667 OSCILLATOR(OSC_SPDIFSYMB, _SPDIFSYMB, "spdif_symb", NO_GATE, NO_GATE, 668 NULL, NULL, NULL), 669 }; 670 671 #ifdef IMAGE_BL2 672 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) 673 { 674 if (id < NB_OSCILLATOR) { 675 return stm32mp2_osc_data[id].name; 676 } 677 678 return NULL; 679 } 680 #endif 681 682 enum pll_id { 683 _PLL1, 684 _PLL2, 685 _PLL3, 686 _PLL4, 687 _PLL5, 688 _PLL6, 689 _PLL7, 690 _PLL8, 691 _PLL_NB 692 }; 693 694 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */ 695 #define RCC_OFFSET_PLLXCFGR1 0x00 696 #define RCC_OFFSET_PLLXCFGR2 0x04 697 #define RCC_OFFSET_PLLXCFGR3 0x08 698 #define RCC_OFFSET_PLLXCFGR4 0x0C 699 #define RCC_OFFSET_PLLXCFGR5 0x10 700 #define RCC_OFFSET_PLLXCFGR6 0x18 701 #define RCC_OFFSET_PLLXCFGR7 0x1C 702 703 struct stm32_clk_pll { 704 uint16_t clk_id; 705 uint16_t reg_pllxcfgr1; 706 }; 707 708 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\ 709 [(_idx)] = {\ 710 .clk_id = (_clk_id),\ 711 .reg_pllxcfgr1 = (_reg),\ 712 } 713 714 static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = { 715 CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ), 716 CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1), 717 #if !STM32MP21 718 CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1), 719 #endif /* !STM32MP21 */ 720 CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1), 721 CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1), 722 CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1), 723 CLK_PLL_CFG(_PLL7, _CK_PLL7, RCC_PLL7CFGR1), 724 CLK_PLL_CFG(_PLL8, _CK_PLL8, RCC_PLL8CFGR1), 725 }; 726 727 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 728 { 729 return &stm32mp2_clk_pll[idx]; 730 } 731 732 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv, 733 const struct stm32_clk_pll *pll, 734 unsigned long prate) 735 { 736 unsigned long refclk, fvco; 737 uint32_t fracin, fbdiv, refdiv; 738 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 739 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 740 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 741 742 refclk = prate; 743 744 fracin = mmio_read_32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK; 745 fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> 746 RCC_PLLxCFGR2_FBDIV_SHIFT; 747 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; 748 749 if (fracin != 0U) { 750 uint64_t numerator, denominator; 751 752 numerator = ((uint64_t)fbdiv << 24) + fracin; 753 numerator = refclk * numerator; 754 denominator = (uint64_t)refdiv << 24; 755 fvco = (unsigned long)(numerator / denominator); 756 } else { 757 fvco = (unsigned long)(refclk * fbdiv / refdiv); 758 } 759 760 return fvco; 761 } 762 763 struct stm32_pll_cfg { 764 uint16_t pll_id; 765 }; 766 767 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 768 { 769 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 770 771 return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U); 772 } 773 774 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 775 { 776 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 777 778 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 779 } 780 781 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 782 { 783 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 784 785 /* Stop PLL */ 786 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 787 } 788 789 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, 790 const struct stm32_clk_pll *pll) 791 { 792 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 793 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 794 795 /* Wait PLL lock */ 796 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) { 797 if (timeout_elapsed(timeout)) { 798 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 799 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1, 800 mmio_read_32(pllxcfgr1)); 801 return -ETIMEDOUT; 802 } 803 } 804 805 return 0; 806 } 807 808 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, 809 const struct stm32_clk_pll *pll) 810 { 811 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 812 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 813 814 /* Wait PLL stopped */ 815 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) { 816 if (timeout_elapsed(timeout)) { 817 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 818 pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1)); 819 return -ETIMEDOUT; 820 } 821 } 822 823 return 0; 824 } 825 826 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 827 { 828 if (_clk_stm32_pll_is_enabled(priv, pll)) { 829 return 0; 830 } 831 832 _clk_stm32_pll_set_on(priv, pll); 833 834 return _clk_stm32_pll_wait_ready_on(priv, pll); 835 } 836 837 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 838 { 839 if (!_clk_stm32_pll_is_enabled(priv, pll)) { 840 return; 841 } 842 843 _clk_stm32_pll_set_off(priv, pll); 844 845 _clk_stm32_pll_wait_ready_off(priv, pll); 846 } 847 848 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) 849 { 850 const struct clk_stm32 *clk = _clk_get(priv, id); 851 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 852 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 853 854 return _clk_stm32_pll_is_enabled(priv, pll); 855 } 856 857 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) 858 { 859 const struct clk_stm32 *clk = _clk_get(priv, id); 860 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 861 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 862 863 return _clk_stm32_pll_enable(priv, pll); 864 } 865 866 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) 867 { 868 const struct clk_stm32 *clk = _clk_get(priv, id); 869 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 870 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 871 872 _clk_stm32_pll_disable(priv, pll); 873 } 874 875 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, 876 unsigned long prate) 877 { 878 const struct clk_stm32 *clk = _clk_get(priv, id); 879 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 880 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 881 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 882 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 883 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 884 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 885 unsigned long dfout; 886 uint32_t postdiv1, postdiv2; 887 888 postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; 889 postdiv2 = mmio_read_32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; 890 891 if ((mmio_read_32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) != 0U) { 892 dfout = prate; 893 } else { 894 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 895 dfout = prate; 896 } else { 897 dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2); 898 } 899 } 900 901 return dfout; 902 } 903 904 static const struct stm32_clk_ops clk_stm32_pll_ops = { 905 .recalc_rate = clk_stm32_pll_recalc_rate, 906 .enable = clk_stm32_pll_enable, 907 .disable = clk_stm32_pll_disable, 908 .is_enabled = clk_stm32_pll_is_enabled, 909 }; 910 911 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 912 .binding = _idx,\ 913 .parent = _parent,\ 914 .flags = (_flags),\ 915 .clock_cfg = &(struct stm32_pll_cfg) {\ 916 .pll_id = _pll_id,\ 917 },\ 918 .ops = STM32_PLL_OPS,\ 919 } 920 921 static unsigned long clk_get_pll1_fvco(unsigned long refclk) 922 { 923 uintptr_t pll_freq1_reg = A35SSC_BASE + A35_SS_PLL_FREQ1; 924 uint32_t reg, fbdiv, refdiv; 925 926 reg = mmio_read_32(pll_freq1_reg); 927 928 fbdiv = (reg & A35_SS_PLL_FREQ1_FBDIV_MASK) >> A35_SS_PLL_FREQ1_FBDIV_SHIFT; 929 refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT; 930 931 return (unsigned long)(refclk * fbdiv / refdiv); 932 } 933 934 static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv, 935 int id, unsigned long prate) 936 { 937 uintptr_t pll_freq2_reg = A35SSC_BASE + A35_SS_PLL_FREQ2; 938 uint32_t postdiv1, postdiv2; 939 unsigned long dfout; 940 941 postdiv1 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV1_MASK) >> 942 A35_SS_PLL_FREQ2_POSTDIV1_SHIFT; 943 postdiv2 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV2_MASK) >> 944 A35_SS_PLL_FREQ2_POSTDIV2_SHIFT; 945 946 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 947 dfout = prate; 948 } else { 949 dfout = clk_get_pll1_fvco(prate) / (postdiv1 * postdiv2); 950 } 951 952 return dfout; 953 } 954 955 static const struct stm32_clk_ops clk_stm32_pll1_ops = { 956 .recalc_rate = clk_stm32_pll1_recalc_rate, 957 }; 958 959 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 960 .binding = _idx,\ 961 .parent = _parent,\ 962 .flags = (_flags),\ 963 .clock_cfg = &(struct stm32_pll_cfg) {\ 964 .pll_id = _pll_id,\ 965 },\ 966 .ops = STM32_PLL1_OPS,\ 967 } 968 969 struct stm32_clk_flexgen_cfg { 970 uint8_t id; 971 }; 972 973 static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx, 974 unsigned long prate) 975 { 976 const struct clk_stm32 *clk = _clk_get(priv, idx); 977 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 978 uintptr_t rcc_base = priv->base; 979 uint32_t prediv, findiv; 980 uint8_t channel = cfg->id; 981 unsigned long freq = prate; 982 983 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) & 984 RCC_PREDIVxCFGR_PREDIVx_MASK; 985 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 986 RCC_FINDIVxCFGR_FINDIVx_MASK; 987 988 if (freq == 0UL) { 989 return 0U; 990 } 991 992 switch (prediv) { 993 case 0x0: 994 case 0x1: 995 case 0x3: 996 case 0x3FF: 997 break; 998 999 default: 1000 ERROR("Unsupported PREDIV value (%x)\n", prediv); 1001 panic(); 1002 break; 1003 } 1004 1005 freq /= (prediv + 1U); 1006 freq /= (findiv + 1U); 1007 1008 return freq; 1009 } 1010 1011 static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx) 1012 { 1013 const struct clk_stm32 *clk = _clk_get(priv, idx); 1014 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1015 uint32_t sel; 1016 uint32_t address; 1017 uintptr_t rcc_base = priv->base; 1018 1019 address = RCC_XBAR0CFGR + (cfg->id * 4); 1020 1021 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK; 1022 1023 return sel; 1024 } 1025 1026 static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx) 1027 { 1028 const struct clk_stm32 *clk = _clk_get(priv, idx); 1029 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1030 uintptr_t rcc_base = priv->base; 1031 uint8_t channel = cfg->id; 1032 1033 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1034 RCC_FINDIVxCFGR_FINDIVxEN); 1035 1036 return 0; 1037 } 1038 1039 static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id) 1040 { 1041 const struct clk_stm32 *clk = _clk_get(priv, id); 1042 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1043 uintptr_t rcc_base = priv->base; 1044 uint8_t channel = cfg->id; 1045 1046 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1047 RCC_FINDIVxCFGR_FINDIVxEN); 1048 } 1049 1050 static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id) 1051 { 1052 const struct clk_stm32 *clk = _clk_get(priv, id); 1053 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1054 uintptr_t rcc_base = priv->base; 1055 uint8_t channel = cfg->id; 1056 1057 return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 1058 RCC_FINDIVxCFGR_FINDIVxEN); 1059 } 1060 1061 static const struct stm32_clk_ops clk_stm32_flexgen_ops = { 1062 .recalc_rate = clk_flexgen_recalc, 1063 .get_parent = clk_flexgen_get_parent, 1064 .enable = clk_flexgen_gate_enable, 1065 .disable = clk_flexgen_gate_disable, 1066 .is_enabled = clk_flexgen_gate_is_enabled, 1067 }; 1068 1069 #define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\ 1070 .binding = _idx,\ 1071 .parent = MUX(MUX_XBARSEL),\ 1072 .flags = (_flags),\ 1073 .clock_cfg = &(struct stm32_clk_flexgen_cfg) {\ 1074 .id = _id,\ 1075 },\ 1076 .ops = STM32_FLEXGEN_OPS,\ 1077 } 1078 1079 #define RCC_0_MHZ UL(0) 1080 #define RCC_4_MHZ UL(4000000) 1081 #define RCC_16_MHZ UL(16000000) 1082 1083 #ifdef IMAGE_BL2 1084 #if !STM32MP21 1085 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, 1086 unsigned long prate) 1087 { 1088 uintptr_t address = priv->base + RCC_BDCR; 1089 uint32_t mask = RCC_BDCR_MSIFREQSEL; 1090 int ret = -1; 1091 1092 switch (rate) { 1093 case RCC_4_MHZ: 1094 mmio_clrbits_32(address, mask); 1095 ret = 0; 1096 break; 1097 1098 case RCC_16_MHZ: 1099 mmio_setbits_32(address, mask); 1100 ret = 0; 1101 break; 1102 1103 default: 1104 break; 1105 } 1106 1107 return ret; 1108 } 1109 #endif /* !STM32MP21 */ 1110 #endif /* IMAGE_BL2 */ 1111 1112 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv, 1113 int id __unused, 1114 unsigned long prate __unused) 1115 { 1116 #if STM32MP21 1117 return RCC_16_MHZ; 1118 #else /* STM32MP21 */ 1119 uintptr_t address = priv->base + RCC_BDCR; 1120 1121 if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) { 1122 return RCC_4_MHZ; 1123 } else { 1124 return RCC_16_MHZ; 1125 } 1126 #endif /* STM32MP21 */ 1127 } 1128 1129 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = { 1130 .recalc_rate = clk_stm32_osc_msi_recalc_rate, 1131 .is_enabled = clk_stm32_osc_gate_is_enabled, 1132 .enable = clk_stm32_osc_gate_enable, 1133 .disable = clk_stm32_osc_gate_disable, 1134 .init = clk_stm32_osc_init, 1135 }; 1136 1137 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \ 1138 [(idx)] = (struct clk_stm32){ \ 1139 .binding = (_idx),\ 1140 .parent = (_parent),\ 1141 .flags = CLK_IS_CRITICAL,\ 1142 .clock_cfg = &(struct stm32_osc_cfg){\ 1143 .osc_id = (_osc_id),\ 1144 },\ 1145 .ops = STM32_OSC_MSI_OPS,\ 1146 } 1147 1148 static const struct stm32_clk_ops clk_stm32_rtc_ops = { 1149 .enable = clk_stm32_gate_enable, 1150 .disable = clk_stm32_gate_disable, 1151 .is_enabled = clk_stm32_gate_is_enabled, 1152 }; 1153 1154 #define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\ 1155 .binding = (_binding),\ 1156 .parent = (_parent),\ 1157 .flags = (_flags),\ 1158 .clock_cfg = &(struct clk_stm32_gate_cfg) {\ 1159 .id = (_gate_id),\ 1160 },\ 1161 .ops = STM32_RTC_OPS,\ 1162 } 1163 1164 enum { 1165 STM32_PLL_OPS = STM32_LAST_OPS, 1166 STM32_PLL1_OPS, 1167 STM32_FLEXGEN_OPS, 1168 STM32_OSC_MSI_OPS, 1169 STM32_RTC_OPS, 1170 1171 MP2_LAST_OPS 1172 }; 1173 1174 static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = { 1175 [NO_OPS] = NULL, 1176 [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops, 1177 [GATE_OPS] = &clk_gate_ops, 1178 [STM32_MUX_OPS] = &clk_mux_ops, 1179 [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops, 1180 [STM32_GATE_OPS] = &clk_stm32_gate_ops, 1181 [STM32_TIMER_OPS] = &clk_timer_ops, 1182 [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops, 1183 [STM32_OSC_OPS] = &clk_stm32_osc_ops, 1184 [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops, 1185 1186 [STM32_PLL_OPS] = &clk_stm32_pll_ops, 1187 [STM32_PLL1_OPS] = &clk_stm32_pll1_ops, 1188 [STM32_FLEXGEN_OPS] = &clk_stm32_flexgen_ops, 1189 [STM32_OSC_MSI_OPS] = &clk_stm32_osc_msi_ops, 1190 [STM32_RTC_OPS] = &clk_stm32_rtc_ops 1191 }; 1192 1193 static const struct clk_stm32 stm32mp2_clk[CK_LAST] = { 1194 CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ), 1195 1196 /* ROOT CLOCKS */ 1197 CLK_OSC(_CK_HSE, HSE_CK, CLK_IS_ROOT, OSC_HSE), 1198 CLK_OSC(_CK_LSE, LSE_CK, CLK_IS_ROOT, OSC_LSE), 1199 CLK_OSC(_CK_HSI, HSI_CK, CLK_IS_ROOT, OSC_HSI), 1200 CLK_OSC(_CK_LSI, LSI_CK, CLK_IS_ROOT, OSC_LSI), 1201 CLK_OSC_MSI(_CK_MSI, MSI_CK, CLK_IS_ROOT, OSC_MSI), 1202 1203 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), 1204 CLK_OSC_FIXED(_SPDIFSYMB, _NO_ID, CLK_IS_ROOT, OSC_SPDIFSYMB), 1205 1206 STM32_DIV(_CK_HSE_RTC, _NO_ID, _CK_HSE, 0, DIV_RTC), 1207 1208 CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK), 1209 1210 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0), 1211 1212 CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0), 1213 #if !STM32MP21 1214 CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0), 1215 #endif /* !STM32MP21 */ 1216 CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0), 1217 CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0), 1218 CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0), 1219 CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0), 1220 CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0), 1221 1222 FLEXGEN(_CK_ICN_HS_MCU, CK_ICN_HS_MCU, CLK_IS_CRITICAL, 0), 1223 FLEXGEN(_CK_ICN_SDMMC, CK_ICN_SDMMC, CLK_IS_CRITICAL, 1), 1224 FLEXGEN(_CK_ICN_DDR, CK_ICN_DDR, CLK_IS_CRITICAL, 2), 1225 FLEXGEN(_CK_ICN_HSL, CK_ICN_HSL, CLK_IS_CRITICAL, 4), 1226 FLEXGEN(_CK_ICN_NIC, CK_ICN_NIC, CLK_IS_CRITICAL, 5), 1227 1228 STM32_DIV(_CK_ICN_LS_MCU, CK_ICN_LS_MCU, _CK_ICN_HS_MCU, 0, DIV_LSMCU), 1229 1230 FLEXGEN(_CK_FLEXGEN_07, CK_FLEXGEN_07, 0, 7), 1231 FLEXGEN(_CK_FLEXGEN_08, CK_FLEXGEN_08, 0, 8), 1232 FLEXGEN(_CK_FLEXGEN_09, CK_FLEXGEN_09, 0, 9), 1233 FLEXGEN(_CK_FLEXGEN_10, CK_FLEXGEN_10, 0, 10), 1234 FLEXGEN(_CK_FLEXGEN_11, CK_FLEXGEN_11, 0, 11), 1235 FLEXGEN(_CK_FLEXGEN_12, CK_FLEXGEN_12, 0, 12), 1236 FLEXGEN(_CK_FLEXGEN_13, CK_FLEXGEN_13, 0, 13), 1237 FLEXGEN(_CK_FLEXGEN_14, CK_FLEXGEN_14, 0, 14), 1238 FLEXGEN(_CK_FLEXGEN_15, CK_FLEXGEN_15, 0, 15), 1239 FLEXGEN(_CK_FLEXGEN_16, CK_FLEXGEN_16, 0, 16), 1240 FLEXGEN(_CK_FLEXGEN_17, CK_FLEXGEN_17, 0, 17), 1241 FLEXGEN(_CK_FLEXGEN_18, CK_FLEXGEN_18, 0, 18), 1242 FLEXGEN(_CK_FLEXGEN_19, CK_FLEXGEN_19, 0, 19), 1243 FLEXGEN(_CK_FLEXGEN_20, CK_FLEXGEN_20, 0, 20), 1244 FLEXGEN(_CK_FLEXGEN_21, CK_FLEXGEN_21, 0, 21), 1245 FLEXGEN(_CK_FLEXGEN_22, CK_FLEXGEN_22, 0, 22), 1246 FLEXGEN(_CK_FLEXGEN_23, CK_FLEXGEN_23, 0, 23), 1247 FLEXGEN(_CK_FLEXGEN_24, CK_FLEXGEN_24, 0, 24), 1248 FLEXGEN(_CK_FLEXGEN_25, CK_FLEXGEN_25, 0, 25), 1249 FLEXGEN(_CK_FLEXGEN_26, CK_FLEXGEN_26, 0, 26), 1250 FLEXGEN(_CK_FLEXGEN_27, CK_FLEXGEN_27, 0, 27), 1251 FLEXGEN(_CK_FLEXGEN_28, CK_FLEXGEN_28, 0, 28), 1252 FLEXGEN(_CK_FLEXGEN_29, CK_FLEXGEN_29, 0, 29), 1253 FLEXGEN(_CK_FLEXGEN_30, CK_FLEXGEN_30, 0, 30), 1254 FLEXGEN(_CK_FLEXGEN_31, CK_FLEXGEN_31, 0, 31), 1255 FLEXGEN(_CK_FLEXGEN_32, CK_FLEXGEN_32, 0, 32), 1256 FLEXGEN(_CK_FLEXGEN_33, CK_FLEXGEN_33, 0, 33), 1257 FLEXGEN(_CK_FLEXGEN_34, CK_FLEXGEN_34, 0, 34), 1258 FLEXGEN(_CK_FLEXGEN_35, CK_FLEXGEN_35, 0, 35), 1259 FLEXGEN(_CK_FLEXGEN_36, CK_FLEXGEN_36, 0, 36), 1260 FLEXGEN(_CK_FLEXGEN_37, CK_FLEXGEN_37, 0, 37), 1261 FLEXGEN(_CK_FLEXGEN_38, CK_FLEXGEN_38, 0, 38), 1262 FLEXGEN(_CK_FLEXGEN_39, CK_FLEXGEN_39, 0, 39), 1263 FLEXGEN(_CK_FLEXGEN_40, CK_FLEXGEN_40, 0, 40), 1264 FLEXGEN(_CK_FLEXGEN_41, CK_FLEXGEN_41, 0, 41), 1265 FLEXGEN(_CK_FLEXGEN_42, CK_FLEXGEN_42, 0, 42), 1266 FLEXGEN(_CK_FLEXGEN_43, CK_FLEXGEN_43, 0, 43), 1267 FLEXGEN(_CK_FLEXGEN_44, CK_FLEXGEN_44, 0, 44), 1268 FLEXGEN(_CK_FLEXGEN_45, CK_FLEXGEN_45, 0, 45), 1269 FLEXGEN(_CK_FLEXGEN_46, CK_FLEXGEN_46, 0, 46), 1270 FLEXGEN(_CK_FLEXGEN_47, CK_FLEXGEN_47, 0, 47), 1271 FLEXGEN(_CK_FLEXGEN_48, CK_FLEXGEN_48, 0, 48), 1272 FLEXGEN(_CK_FLEXGEN_49, CK_FLEXGEN_49, 0, 49), 1273 FLEXGEN(_CK_FLEXGEN_50, CK_FLEXGEN_50, 0, 50), 1274 FLEXGEN(_CK_FLEXGEN_51, CK_FLEXGEN_51, 0, 51), 1275 FLEXGEN(_CK_FLEXGEN_52, CK_FLEXGEN_52, 0, 52), 1276 FLEXGEN(_CK_FLEXGEN_53, CK_FLEXGEN_53, 0, 53), 1277 FLEXGEN(_CK_FLEXGEN_54, CK_FLEXGEN_54, 0, 54), 1278 FLEXGEN(_CK_FLEXGEN_55, CK_FLEXGEN_55, 0, 55), 1279 FLEXGEN(_CK_FLEXGEN_56, CK_FLEXGEN_56, 0, 56), 1280 FLEXGEN(_CK_FLEXGEN_57, CK_FLEXGEN_57, 0, 57), 1281 FLEXGEN(_CK_FLEXGEN_58, CK_FLEXGEN_58, 0, 58), 1282 FLEXGEN(_CK_FLEXGEN_59, CK_FLEXGEN_59, 0, 59), 1283 FLEXGEN(_CK_FLEXGEN_60, CK_FLEXGEN_60, 0, 60), 1284 FLEXGEN(_CK_FLEXGEN_61, CK_FLEXGEN_61, 0, 61), 1285 FLEXGEN(_CK_FLEXGEN_62, CK_FLEXGEN_62, 0, 62), 1286 FLEXGEN(_CK_FLEXGEN_63, CK_FLEXGEN_63, 0, 63), 1287 1288 STM32_DIV(_CK_ICN_APB1, CK_ICN_APB1, _CK_ICN_LS_MCU, 0, DIV_APB1), 1289 STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2), 1290 STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3), 1291 STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4), 1292 #if STM32MP21 1293 STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5), 1294 #endif /* STM32MP21 */ 1295 STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG), 1296 1297 /* KERNEL CLOCK */ 1298 STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM), 1299 STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM), 1300 STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1), 1301 #if !STM32MP21 1302 STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2), 1303 #endif /* !STM32MP21 */ 1304 1305 STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC), 1306 STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1), 1307 STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC), 1308 #if !STM32MP21 1309 STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM), 1310 #endif /* !STM32MP21 */ 1311 STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM), 1312 #if STM32MP21 1313 STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1), 1314 STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2), 1315 STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1), 1316 STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2), 1317 #else /* STM32MP21 */ 1318 STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH), 1319 STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG), 1320 #endif /* STM32MP21 */ 1321 STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1), 1322 STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2), 1323 STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES), 1324 STM32_GATE(_CK_PKA, CK_BUS_PKA, _CK_ICN_LS_MCU, 0, GATE_PKA), 1325 1326 STM32_GATE(_CK_GPIOA, CK_BUS_GPIOA, _CK_ICN_LS_MCU, 0, GATE_GPIOA), 1327 STM32_GATE(_CK_GPIOB, CK_BUS_GPIOB, _CK_ICN_LS_MCU, 0, GATE_GPIOB), 1328 STM32_GATE(_CK_GPIOC, CK_BUS_GPIOC, _CK_ICN_LS_MCU, 0, GATE_GPIOC), 1329 STM32_GATE(_CK_GPIOD, CK_BUS_GPIOD, _CK_ICN_LS_MCU, 0, GATE_GPIOD), 1330 STM32_GATE(_CK_GPIOE, CK_BUS_GPIOE, _CK_ICN_LS_MCU, 0, GATE_GPIOE), 1331 STM32_GATE(_CK_GPIOF, CK_BUS_GPIOF, _CK_ICN_LS_MCU, 0, GATE_GPIOF), 1332 STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG), 1333 STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH), 1334 STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI), 1335 #if !STM32MP21 1336 STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ), 1337 STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK), 1338 #endif /* !STM32MP21 */ 1339 STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ), 1340 STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC), 1341 1342 STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP), 1343 1344 /* WARNING 2 CLOCKS FOR ONE GATE */ 1345 #if STM32MP21 1346 STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI), 1347 STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI), 1348 #else /* STM32MP21 */ 1349 STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI), 1350 STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI), 1351 #endif /* STM32MP21 */ 1352 1353 #if !STM32MP21 1354 STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR), 1355 #endif /* !STM32MP21 */ 1356 1357 STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC), 1358 STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1), 1359 STM32_GATE(_CK_IWDG2, CK_BUS_IWDG2, _CK_ICN_APB3, 0, GATE_IWDG2), 1360 1361 STM32_GATE(_CK_DDRCAPB, CK_BUS_DDRC, _CK_ICN_APB4, 0, GATE_DDRCAPB), 1362 STM32_GATE(_CK_DDR, CK_BUS_DDRCFG, _CK_ICN_APB4, 0, GATE_DDR), 1363 1364 STM32_GATE(_CK_USART2, CK_KER_USART2, _CK_FLEXGEN_08, 0, GATE_USART2), 1365 STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4), 1366 STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3), 1367 STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5), 1368 #if STM32MP21 1369 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1), 1370 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2), 1371 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1), 1372 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6), 1373 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7), 1374 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3), 1375 #else /* STM32MP21 */ 1376 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1), 1377 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2), 1378 #if STM32MP25 1379 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3), 1380 STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5), 1381 STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4), 1382 STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6), 1383 #endif /* STM32MP25 */ 1384 STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7), 1385 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1), 1386 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6), 1387 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7), 1388 #if STM32MP25 1389 STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8), 1390 STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9), 1391 #endif /* STM32MP25 */ 1392 #endif /* STM32MP21 */ 1393 STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN), 1394 #if !STM32MP21 1395 STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY), 1396 STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC), 1397 STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8), 1398 #endif /* !STM32MP21 */ 1399 STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1), 1400 #if !STM32MP21 1401 STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2), 1402 #endif /* !STM32MP21 */ 1403 STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC), 1404 STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1), 1405 STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2), 1406 STM32_GATE(_CK_USB2PHY1, CK_KER_USB2PHY1, _CK_FLEXGEN_57, 0, GATE_USB2PHY1), 1407 STM32_GATE(_CK_USB2PHY2, CK_KER_USB2PHY2, _CK_FLEXGEN_58, 0, GATE_USB2PHY2), 1408 }; 1409 1410 enum clksrc_id { 1411 CLKSRC_CA35SS, 1412 CLKSRC_PLL1, 1413 CLKSRC_PLL2, 1414 #if !STM32MP21 1415 CLKSRC_PLL3, 1416 #endif /* !STM32MP21 */ 1417 CLKSRC_PLL4, 1418 CLKSRC_PLL5, 1419 CLKSRC_PLL6, 1420 CLKSRC_PLL7, 1421 CLKSRC_PLL8, 1422 CLKSRC_XBAR_CHANNEL0, 1423 CLKSRC_XBAR_CHANNEL1, 1424 CLKSRC_XBAR_CHANNEL2, 1425 CLKSRC_XBAR_CHANNEL3, 1426 CLKSRC_XBAR_CHANNEL4, 1427 CLKSRC_XBAR_CHANNEL5, 1428 CLKSRC_XBAR_CHANNEL6, 1429 CLKSRC_XBAR_CHANNEL7, 1430 CLKSRC_XBAR_CHANNEL8, 1431 CLKSRC_XBAR_CHANNEL9, 1432 CLKSRC_XBAR_CHANNEL10, 1433 CLKSRC_XBAR_CHANNEL11, 1434 CLKSRC_XBAR_CHANNEL12, 1435 CLKSRC_XBAR_CHANNEL13, 1436 CLKSRC_XBAR_CHANNEL14, 1437 CLKSRC_XBAR_CHANNEL15, 1438 CLKSRC_XBAR_CHANNEL16, 1439 CLKSRC_XBAR_CHANNEL17, 1440 CLKSRC_XBAR_CHANNEL18, 1441 CLKSRC_XBAR_CHANNEL19, 1442 CLKSRC_XBAR_CHANNEL20, 1443 CLKSRC_XBAR_CHANNEL21, 1444 CLKSRC_XBAR_CHANNEL22, 1445 CLKSRC_XBAR_CHANNEL23, 1446 CLKSRC_XBAR_CHANNEL24, 1447 CLKSRC_XBAR_CHANNEL25, 1448 CLKSRC_XBAR_CHANNEL26, 1449 CLKSRC_XBAR_CHANNEL27, 1450 CLKSRC_XBAR_CHANNEL28, 1451 CLKSRC_XBAR_CHANNEL29, 1452 CLKSRC_XBAR_CHANNEL30, 1453 CLKSRC_XBAR_CHANNEL31, 1454 CLKSRC_XBAR_CHANNEL32, 1455 CLKSRC_XBAR_CHANNEL33, 1456 CLKSRC_XBAR_CHANNEL34, 1457 CLKSRC_XBAR_CHANNEL35, 1458 CLKSRC_XBAR_CHANNEL36, 1459 CLKSRC_XBAR_CHANNEL37, 1460 CLKSRC_XBAR_CHANNEL38, 1461 CLKSRC_XBAR_CHANNEL39, 1462 CLKSRC_XBAR_CHANNEL40, 1463 CLKSRC_XBAR_CHANNEL41, 1464 CLKSRC_XBAR_CHANNEL42, 1465 CLKSRC_XBAR_CHANNEL43, 1466 CLKSRC_XBAR_CHANNEL44, 1467 CLKSRC_XBAR_CHANNEL45, 1468 CLKSRC_XBAR_CHANNEL46, 1469 CLKSRC_XBAR_CHANNEL47, 1470 CLKSRC_XBAR_CHANNEL48, 1471 CLKSRC_XBAR_CHANNEL49, 1472 CLKSRC_XBAR_CHANNEL50, 1473 CLKSRC_XBAR_CHANNEL51, 1474 CLKSRC_XBAR_CHANNEL52, 1475 CLKSRC_XBAR_CHANNEL53, 1476 CLKSRC_XBAR_CHANNEL54, 1477 CLKSRC_XBAR_CHANNEL55, 1478 CLKSRC_XBAR_CHANNEL56, 1479 CLKSRC_XBAR_CHANNEL57, 1480 CLKSRC_XBAR_CHANNEL58, 1481 CLKSRC_XBAR_CHANNEL59, 1482 CLKSRC_XBAR_CHANNEL60, 1483 CLKSRC_XBAR_CHANNEL61, 1484 CLKSRC_XBAR_CHANNEL62, 1485 CLKSRC_XBAR_CHANNEL63, 1486 CLKSRC_RTC, 1487 CLKSRC_MCO1, 1488 CLKSRC_MCO2, 1489 CLKSRC_NB 1490 }; 1491 1492 static void stm32mp2_a35_ss_on_hsi(void) 1493 { 1494 uintptr_t a35_ss_address = A35SSC_BASE; 1495 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1496 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1497 uint64_t timeout; 1498 1499 if ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) == 1500 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1501 /* Nothing to do, clock source is already set on bypass clock */ 1502 return; 1503 } 1504 1505 mmio_setbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1506 1507 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1508 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 1509 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1510 if (timeout_elapsed(timeout)) { 1511 EARLY_ERROR("Cannot switch A35 to bypass clock\n"); 1512 panic(); 1513 } 1514 } 1515 1516 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1517 } 1518 1519 #ifdef IMAGE_BL2 1520 static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv) 1521 { 1522 mmio_clrbits_32(priv->base + RCC_MUXSELCFGR, 1523 RCC_MUXSELCFGR_MUXSEL0_MASK | 1524 RCC_MUXSELCFGR_MUXSEL1_MASK | 1525 RCC_MUXSELCFGR_MUXSEL2_MASK | 1526 RCC_MUXSELCFGR_MUXSEL3_MASK | 1527 RCC_MUXSELCFGR_MUXSEL4_MASK | 1528 RCC_MUXSELCFGR_MUXSEL5_MASK | 1529 RCC_MUXSELCFGR_MUXSEL6_MASK | 1530 RCC_MUXSELCFGR_MUXSEL7_MASK); 1531 } 1532 1533 static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv) 1534 { 1535 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; 1536 uint32_t i; 1537 1538 for (i = 0; i < XBAR_CHANNEL_NB; i++) { 1539 mmio_clrsetbits_32(xbar0cfgr + (0x4 * i), 1540 RCC_XBAR0CFGR_XBAR0SEL_MASK, 1541 XBAR_SRC_HSI); 1542 } 1543 } 1544 1545 static int stm32mp2_a35_pll1_start(void) 1546 { 1547 uintptr_t a35_ss_address = A35SSC_BASE; 1548 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1549 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1550 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1551 1552 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 1553 1554 /* Wait PLL lock */ 1555 while ((mmio_read_32(pll_enable_reg) & A35_SS_PLL_ENABLE_LOCKP) == 0U) { 1556 if (timeout_elapsed(timeout)) { 1557 EARLY_ERROR("PLL1 start failed @ 0x%lx: 0x%x\n", 1558 pll_enable_reg, mmio_read_32(pll_enable_reg)); 1559 return -ETIMEDOUT; 1560 } 1561 } 1562 1563 /* De-assert reset on PLL output clock path */ 1564 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1565 1566 /* Switch CPU clock to PLL clock */ 1567 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1568 1569 /* Wait for clock change acknowledge */ 1570 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1571 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 0U) { 1572 if (timeout_elapsed(timeout)) { 1573 EARLY_ERROR("CA35SS switch to PLL1 failed @ 0x%lx: 0x%x\n", 1574 chgclkreq_reg, mmio_read_32(chgclkreq_reg)); 1575 return -ETIMEDOUT; 1576 } 1577 } 1578 1579 return 0; 1580 } 1581 1582 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1, 1583 uint32_t postdiv2) 1584 { 1585 uintptr_t a35_ss_address = A35SSC_BASE; 1586 uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1; 1587 uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2; 1588 1589 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_REFDIV_MASK, 1590 (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) & 1591 A35_SS_PLL_FREQ1_REFDIV_MASK); 1592 1593 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_FBDIV_MASK, 1594 (fbdiv << A35_SS_PLL_FREQ1_FBDIV_SHIFT) & 1595 A35_SS_PLL_FREQ1_FBDIV_MASK); 1596 1597 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV1_MASK, 1598 (postdiv1 << A35_SS_PLL_FREQ2_POSTDIV1_SHIFT) & 1599 A35_SS_PLL_FREQ2_POSTDIV1_MASK); 1600 1601 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV2_MASK, 1602 (postdiv2 << A35_SS_PLL_FREQ2_POSTDIV2_SHIFT) & 1603 A35_SS_PLL_FREQ2_POSTDIV2_MASK); 1604 } 1605 1606 static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv, 1607 const struct stm32_clk_pll *pll, 1608 uint32_t *pllcfg, 1609 uint32_t fracv) 1610 { 1611 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1612 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 1613 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1614 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1615 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 1616 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 1617 unsigned long refclk; 1618 1619 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1620 1621 if (fracv == 0U) { 1622 /* PLL in integer mode */ 1623 1624 /* 1625 * No need to check max clock, as oscillator reference clocks 1626 * will always be less than 1.2GHz 1627 */ 1628 if (refclk < PLL_REFCLK_MIN) { 1629 panic(); 1630 } 1631 1632 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK); 1633 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1634 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1635 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1636 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1637 } else { 1638 /* PLL in frac mode */ 1639 1640 /* 1641 * No need to check max clock, as oscillator reference clocks 1642 * will always be less than 1.2GHz 1643 */ 1644 if (refclk < PLL_FRAC_REFCLK_MIN) { 1645 panic(); 1646 } 1647 1648 mmio_clrsetbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, 1649 fracv & RCC_PLLxCFGR3_FRACIN_MASK); 1650 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1651 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1652 } 1653 1654 assert(pllcfg[REFDIV] != 0U); 1655 1656 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, 1657 (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) & 1658 RCC_PLLxCFGR2_FBDIV_MASK); 1659 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, 1660 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); 1661 mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, 1662 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); 1663 mmio_clrsetbits_32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, 1664 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); 1665 1666 if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) { 1667 /* Bypass mode */ 1668 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1669 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1670 } else { 1671 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1672 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1673 } 1674 1675 return 0; 1676 } 1677 1678 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, 1679 const struct stm32_clk_pll *pll, 1680 uint32_t *csg) 1681 { 1682 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1683 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1684 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1685 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5; 1686 1687 1688 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, 1689 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); 1690 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, 1691 (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) & 1692 RCC_PLLxCFGR5_SPREAD_MASK); 1693 1694 if (csg[DOWNSPREAD] != 0) { 1695 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1696 } else { 1697 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1698 } 1699 1700 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1701 1702 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 1703 udelay(1); 1704 1705 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1706 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1707 } 1708 1709 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data); 1710 1711 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) 1712 { 1713 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1714 struct stm32_clk_platdata *pdata = priv->pdata; 1715 1716 return &pdata->pll[pll_idx]; 1717 } 1718 1719 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx, 1720 struct stm32_pll_dt_cfg *pll_conf) 1721 { 1722 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1723 unsigned long refclk; 1724 int ret = 0; 1725 1726 stm32mp2_a35_ss_on_hsi(); 1727 1728 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1729 if (ret != 0) { 1730 panic(); 1731 } 1732 1733 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1734 1735 /* 1736 * No need to check max clock, as oscillator reference clocks will 1737 * always be less than 1.2 GHz 1738 */ 1739 if (refclk < PLL_REFCLK_MIN) { 1740 EARLY_ERROR("%s: %d\n", __func__, __LINE__); 1741 panic(); 1742 } 1743 1744 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV], 1745 pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]); 1746 1747 ret = stm32mp2_a35_pll1_start(); 1748 if (ret != 0) { 1749 panic(); 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv, 1756 const struct stm32_clk_pll *pll) 1757 { 1758 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1759 uint64_t timeout = timeout_init_us(CLKSRC_TIMEOUT); 1760 1761 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) != 1762 RCC_PLLxCFGR1_CKREFST) { 1763 if (timeout_elapsed(timeout)) { 1764 EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1); 1765 return -ETIMEDOUT; 1766 } 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, 1773 struct stm32_pll_dt_cfg *pll_conf) 1774 { 1775 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1776 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1777 bool spread_spectrum = false; 1778 int ret = 0; 1779 1780 _clk_stm32_pll_disable(priv, pll); 1781 1782 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1783 if (ret != 0) { 1784 panic(); 1785 } 1786 1787 ret = clk_stm32_pll_wait_mux_ready(priv, pll); 1788 if (ret != 0) { 1789 panic(); 1790 } 1791 1792 ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac); 1793 if (ret != 0) { 1794 panic(); 1795 } 1796 1797 if (pll_conf->csg_enabled) { 1798 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); 1799 spread_spectrum = true; 1800 } 1801 1802 _clk_stm32_pll_enable(priv, pll); 1803 1804 if (spread_spectrum) { 1805 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) 1812 { 1813 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); 1814 1815 if (pll_conf->enabled) { 1816 if (pll_idx == _PLL1) { 1817 return _clk_stm32_pll1_init(priv, pll_idx, pll_conf); 1818 } else { 1819 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); 1820 } 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv) 1827 { 1828 enum pll_id i; 1829 int err; 1830 1831 for (i = _PLL1; i < _PLL_NB; i++) { 1832 #if STM32MP21 1833 if (i == _PLL3) { 1834 continue; 1835 } 1836 #endif 1837 err = clk_stm32_pll_init(priv, i); 1838 if (err) { 1839 return err; 1840 } 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int wait_predivsr(uint16_t channel) 1847 { 1848 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1849 uintptr_t rcc_base = priv->base; 1850 uintptr_t previvsr; 1851 uint32_t channel_bit; 1852 uint64_t timeout; 1853 1854 if (channel < __WORD_BIT) { 1855 previvsr = rcc_base + RCC_PREDIVSR1; 1856 channel_bit = BIT(channel); 1857 } else { 1858 previvsr = rcc_base + RCC_PREDIVSR2; 1859 channel_bit = BIT(channel - __WORD_BIT); 1860 } 1861 1862 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1863 while ((mmio_read_32(previvsr) & channel_bit) != 0U) { 1864 if (timeout_elapsed(timeout)) { 1865 EARLY_ERROR("Pre divider status: %x\n", 1866 mmio_read_32(previvsr)); 1867 return -ETIMEDOUT; 1868 } 1869 } 1870 1871 return 0; 1872 } 1873 1874 static int wait_findivsr(uint16_t channel) 1875 { 1876 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1877 uintptr_t rcc_base = priv->base; 1878 uintptr_t finvivsr; 1879 uint32_t channel_bit; 1880 uint64_t timeout; 1881 1882 if (channel < __WORD_BIT) { 1883 finvivsr = rcc_base + RCC_FINDIVSR1; 1884 channel_bit = BIT(channel); 1885 } else { 1886 finvivsr = rcc_base + RCC_FINDIVSR2; 1887 channel_bit = BIT(channel - __WORD_BIT); 1888 } 1889 1890 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1891 while ((mmio_read_32(finvivsr) & channel_bit) != 0U) { 1892 if (timeout_elapsed(timeout)) { 1893 EARLY_ERROR("Final divider status: %x\n", 1894 mmio_read_32(finvivsr)); 1895 return -ETIMEDOUT; 1896 } 1897 } 1898 1899 return 0; 1900 } 1901 1902 static int wait_xbar_sts(uint16_t channel) 1903 { 1904 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1905 uintptr_t rcc_base = priv->base; 1906 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4U * channel); 1907 uint64_t timeout; 1908 1909 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1910 while ((mmio_read_32(xbar_cfgr) & RCC_XBAR0CFGR_XBAR0STS) != 0U) { 1911 if (timeout_elapsed(timeout)) { 1912 EARLY_ERROR("XBAR%uCFGR: %x\n", channel, 1913 mmio_read_32(xbar_cfgr)); 1914 return -ETIMEDOUT; 1915 } 1916 } 1917 1918 return 0; 1919 } 1920 1921 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, 1922 unsigned int prediv, unsigned int findiv) 1923 { 1924 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1925 uintptr_t rcc_base = priv->base; 1926 1927 if (wait_predivsr(channel) != 0) { 1928 panic(); 1929 } 1930 1931 mmio_clrsetbits_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel), 1932 RCC_PREDIV0CFGR_PREDIV0_MASK, 1933 prediv); 1934 1935 if (wait_predivsr(channel) != 0) { 1936 panic(); 1937 } 1938 1939 if (wait_findivsr(channel) != 0) { 1940 panic(); 1941 } 1942 1943 mmio_clrsetbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1944 RCC_FINDIV0CFGR_FINDIV0_MASK, 1945 findiv); 1946 1947 if (wait_findivsr(channel) != 0) { 1948 panic(); 1949 } 1950 1951 if (wait_xbar_sts(channel) != 0) { 1952 panic(); 1953 } 1954 1955 mmio_clrsetbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1956 RCC_XBARxCFGR_XBARxSEL_MASK, 1957 clk_src); 1958 mmio_setbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1959 RCC_XBARxCFGR_XBARxEN); 1960 1961 if (wait_xbar_sts(channel) != 0) { 1962 panic(); 1963 } 1964 } 1965 1966 static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv) 1967 { 1968 struct stm32_clk_platdata *pdata = priv->pdata; 1969 uint32_t i; 1970 1971 for (i = 0U; i < pdata->nflexgen; i++) { 1972 uint32_t val = pdata->flexgen[i]; 1973 uint32_t cmd, cmd_data; 1974 unsigned int channel, clk_src, pdiv, fdiv; 1975 1976 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1977 cmd_data = val & ~CMD_MASK; 1978 1979 if (cmd != CMD_FLEXGEN) { 1980 continue; 1981 } 1982 1983 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 1984 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 1985 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 1986 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 1987 1988 switch (channel) { 1989 case 33U: /* STGEN */ 1990 break; 1991 1992 default: 1993 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 1994 break; 1995 } 1996 } 1997 1998 return 0; 1999 } 2000 2001 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) 2002 { 2003 struct stm32_clk_platdata *pdata = priv->pdata; 2004 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 2005 bool digbyp = osci->digbyp; 2006 bool bypass = osci->bypass; 2007 bool css = osci->css; 2008 2009 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { 2010 return; 2011 } 2012 2013 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); 2014 2015 _clk_stm32_enable(priv, _CK_HSE); 2016 2017 clk_oscillator_set_css(priv, _CK_HSE, css); 2018 } 2019 2020 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) 2021 { 2022 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); 2023 struct stm32_clk_platdata *pdata = priv->pdata; 2024 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 2025 bool digbyp = osci->digbyp; 2026 bool bypass = osci->bypass; 2027 uint8_t drive = osci->drive; 2028 2029 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { 2030 return; 2031 } 2032 2033 /* Do not reconfigure LSE if already enabled */ 2034 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) { 2035 return; 2036 } 2037 2038 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); 2039 2040 clk_oscillator_set_drive(priv, _CK_LSE, drive); 2041 2042 _clk_stm32_gate_enable(priv, osc_data->gate_id); 2043 } 2044 2045 static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv) 2046 { 2047 stm32mp2_a35_ss_on_hsi(); 2048 stm32mp2_clk_muxsel_on_hsi(priv); 2049 stm32mp2_clk_xbar_on_hsi(priv); 2050 2051 return 0; 2052 } 2053 2054 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) 2055 { 2056 int ret = 0; 2057 2058 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { 2059 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); 2060 } 2061 2062 return ret; 2063 } 2064 2065 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv) 2066 { 2067 #if !STM32MP21 2068 struct stm32_clk_platdata *pdata = priv->pdata; 2069 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI]; 2070 int err; 2071 2072 err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0); 2073 if (err != 0) { 2074 EARLY_ERROR("Invalid rate %lu MHz for MSI ! (4 or 16 only)\n", 2075 osci->freq / 1000000U); 2076 panic(); 2077 } 2078 #endif /* !STM32MP21 */ 2079 2080 _clk_stm32_enable(priv, _CK_MSI); 2081 } 2082 2083 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) 2084 { 2085 stm32_enable_oscillator_hse(priv); 2086 stm32_enable_oscillator_lse(priv); 2087 stm32_enable_oscillator_msi(priv); 2088 _clk_stm32_enable(priv, _CK_LSI); 2089 } 2090 2091 static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data) 2092 { 2093 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 2094 int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 2095 2096 return clk_stm32_set_div(priv, div_id, div_n); 2097 } 2098 2099 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) 2100 { 2101 int mux_id = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 2102 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 2103 2104 return clk_mux_set_parent(priv, mux_id, sel); 2105 } 2106 2107 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) 2108 { 2109 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 2110 2111 return clk_get_index(priv, binding_id); 2112 } 2113 2114 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 2115 { 2116 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 2117 bool enable = ((data & CLK_ON_MASK) >> CLK_ON_SHIFT) != 0U; 2118 int clk_id = 0; 2119 int ret = 0; 2120 2121 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); 2122 if (clk_id < 0) { 2123 return clk_id; 2124 } 2125 2126 if (sel != CLK_NOMUX) { 2127 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); 2128 if (ret != 0) { 2129 return ret; 2130 } 2131 } 2132 2133 if (enable) { 2134 clk_stm32_enable_call_ops(priv, clk_id); 2135 } else { 2136 clk_stm32_disable_call_ops(priv, clk_id); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val) 2143 { 2144 uint32_t cmd = (val & CMD_MASK) >> CMD_SHIFT; 2145 uint32_t cmd_data = val & ~CMD_MASK; 2146 int ret = -1; 2147 2148 switch (cmd) { 2149 case CMD_DIV: 2150 ret = stm32_clk_configure_div(priv, cmd_data); 2151 break; 2152 2153 case CMD_MUX: 2154 ret = stm32_clk_configure_mux(priv, cmd_data); 2155 break; 2156 2157 case CMD_CLK: 2158 ret = stm32_clk_configure_clk(priv, cmd_data); 2159 break; 2160 2161 default: 2162 EARLY_ERROR("%s: cmd unknown ! : 0x%x\n", __func__, val); 2163 break; 2164 } 2165 2166 return ret; 2167 } 2168 2169 static int stm32_clk_bus_configure(struct stm32_clk_priv *priv) 2170 { 2171 struct stm32_clk_platdata *pdata = priv->pdata; 2172 uint32_t i; 2173 2174 for (i = 0; i < pdata->nbusclk; i++) { 2175 int ret; 2176 2177 ret = stm32_clk_configure(priv, pdata->busclk[i]); 2178 if (ret != 0) { 2179 return ret; 2180 } 2181 } 2182 2183 return 0; 2184 } 2185 2186 static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv) 2187 { 2188 struct stm32_clk_platdata *pdata = priv->pdata; 2189 uint32_t i; 2190 2191 for (i = 0U; i < pdata->nkernelclk; i++) { 2192 int ret; 2193 2194 ret = stm32_clk_configure(priv, pdata->kernelclk[i]); 2195 if (ret != 0) { 2196 return ret; 2197 } 2198 } 2199 2200 return 0; 2201 } 2202 2203 static int stm32mp2_init_clock_tree(void) 2204 { 2205 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 2206 int ret; 2207 2208 /* Set timer with STGEN without changing its clock source */ 2209 stm32mp_stgen_restore_rate(); 2210 generic_delay_timer_init(); 2211 2212 stm32_clk_oscillators_enable(priv); 2213 2214 /* Come back to HSI */ 2215 ret = stm32mp2_clk_switch_to_hsi(priv); 2216 if (ret != 0) { 2217 panic(); 2218 } 2219 2220 ret = stm32mp2_clk_pll_configure(priv); 2221 if (ret != 0) { 2222 panic(); 2223 } 2224 2225 /* Wait LSE ready before to use it */ 2226 ret = stm32_clk_oscillators_wait_lse_ready(priv); 2227 if (ret != 0) { 2228 panic(); 2229 } 2230 2231 ret = stm32mp2_clk_flexgen_configure(priv); 2232 if (ret != 0) { 2233 panic(); 2234 } 2235 2236 ret = stm32_clk_bus_configure(priv); 2237 if (ret != 0) { 2238 panic(); 2239 } 2240 2241 ret = stm32_clk_kernel_configure(priv); 2242 if (ret != 0) { 2243 panic(); 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, 2250 struct stm32_osci_dt_cfg *osci) 2251 { 2252 int subnode = 0; 2253 2254 /* Default value oscillator not found, freq=0 */ 2255 osci->freq = 0; 2256 2257 fdt_for_each_subnode(subnode, fdt, node) { 2258 const char *cchar = NULL; 2259 const fdt32_t *cuint = NULL; 2260 int ret = 0; 2261 2262 cchar = fdt_get_name(fdt, subnode, &ret); 2263 if (cchar == NULL) { 2264 return ret; 2265 } 2266 2267 if (strncmp(cchar, name, (size_t)ret) || 2268 fdt_get_status(subnode) == DT_DISABLED) { 2269 continue; 2270 } 2271 2272 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 2273 if (cuint == NULL) { 2274 return ret; 2275 } 2276 2277 osci->freq = fdt32_to_cpu(*cuint); 2278 2279 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { 2280 osci->bypass = true; 2281 } 2282 2283 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { 2284 osci->digbyp = true; 2285 } 2286 2287 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { 2288 osci->css = true; 2289 } 2290 2291 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); 2292 2293 return 0; 2294 } 2295 2296 return 0; 2297 } 2298 2299 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) 2300 { 2301 int fdt_err = 0; 2302 uint32_t i = 0; 2303 int node = 0; 2304 2305 node = fdt_path_offset(fdt, "/clocks"); 2306 if (node < 0) { 2307 return -FDT_ERR_NOTFOUND; 2308 } 2309 2310 for (i = 0; i < pdata->nosci; i++) { 2311 const char *name = NULL; 2312 2313 name = clk_stm32_get_oscillator_name((enum stm32_osc)i); 2314 if (name == NULL) { 2315 continue; 2316 } 2317 2318 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); 2319 if (fdt_err < 0) { 2320 panic(); 2321 } 2322 } 2323 2324 return 0; 2325 } 2326 2327 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2328 { 2329 const fdt32_t *cuint = NULL; 2330 int subnode_pll = 0; 2331 uint32_t val = 0; 2332 int err = 0; 2333 2334 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2335 if (!cuint) { 2336 return -FDT_ERR_NOTFOUND; 2337 } 2338 2339 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2340 if (subnode_pll < 0) { 2341 return -FDT_ERR_NOTFOUND; 2342 } 2343 2344 err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg); 2345 if (err != 0) { 2346 return err; 2347 } 2348 2349 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg); 2350 2351 pll->csg_enabled = (err == 0); 2352 2353 if (err == -FDT_ERR_NOTFOUND) { 2354 err = 0; 2355 } 2356 2357 if (err != 0) { 2358 return err; 2359 } 2360 2361 pll->enabled = true; 2362 2363 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); 2364 2365 pll->src = UINT32_MAX; 2366 2367 err = fdt_read_uint32(fdt, subnode_pll, "src", &val); 2368 if (err == 0) { 2369 pll->src = val; 2370 } 2371 2372 return 0; 2373 } 2374 2375 #define RCC_PLL_NAME_SIZE 12 2376 2377 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2378 { 2379 unsigned int i = 0; 2380 2381 for (i = _PLL1; i < pdata->npll; i++) { 2382 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 2383 char name[RCC_PLL_NAME_SIZE]; 2384 int subnode = 0; 2385 int err = 0; 2386 2387 #if STM32MP21 2388 if (i == _PLL3) { 2389 continue; 2390 } 2391 #endif 2392 snprintf(name, sizeof(name), "st,pll-%u", i + 1); 2393 2394 subnode = fdt_subnode_offset(fdt, node, name); 2395 if (!fdt_check_node(subnode)) { 2396 continue; 2397 } 2398 2399 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2400 if (err != 0) { 2401 panic(); 2402 } 2403 } 2404 2405 return 0; 2406 } 2407 2408 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2409 { 2410 void *fdt = NULL; 2411 int node; 2412 int err; 2413 2414 if (fdt_get_address(&fdt) == 0) { 2415 return -ENOENT; 2416 } 2417 2418 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2419 if (node < 0) { 2420 panic(); 2421 } 2422 2423 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); 2424 if (err != 0) { 2425 return err; 2426 } 2427 2428 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2429 if (err != 0) { 2430 return err; 2431 } 2432 2433 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,busclk", pdata->busclk, &pdata->nbusclk); 2434 if (err != 0) { 2435 return err; 2436 } 2437 2438 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,flexgen", pdata->flexgen, 2439 &pdata->nflexgen); 2440 if (err != 0) { 2441 return err; 2442 } 2443 2444 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,kerclk", pdata->kernelclk, 2445 &pdata->nkernelclk); 2446 if (err != 0) { 2447 return err; 2448 } 2449 2450 return 0; 2451 } 2452 #endif /* IMAGE_BL2 */ 2453 2454 static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR]; 2455 2456 static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB]; 2457 2458 #define DT_FLEXGEN_CLK_MAX 64 2459 static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX]; 2460 2461 #if STM32MP21 2462 #define DT_BUS_CLK_MAX 7 2463 #else /* STM32MP21 */ 2464 #define DT_BUS_CLK_MAX 6 2465 #endif /* STM32MP21 */ 2466 static uint32_t mp2_busclk[DT_BUS_CLK_MAX]; 2467 2468 #define DT_KERNEL_CLK_MAX 20 2469 static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX]; 2470 2471 static struct stm32_clk_platdata stm32mp2_pdata = { 2472 .osci = mp2_osci, 2473 .nosci = NB_OSCILLATOR, 2474 .pll = mp2_pll, 2475 .npll = _PLL_NB, 2476 .flexgen = mp2_flexgen, 2477 .nflexgen = DT_FLEXGEN_CLK_MAX, 2478 .busclk = mp2_busclk, 2479 .nbusclk = DT_BUS_CLK_MAX, 2480 .kernelclk = mp2_kernelclk, 2481 .nkernelclk = DT_KERNEL_CLK_MAX, 2482 }; 2483 2484 static uint8_t refcounts_mp2[CK_LAST]; 2485 2486 static struct stm32_clk_priv stm32mp2_clock_data = { 2487 .base = RCC_BASE, 2488 .num = ARRAY_SIZE(stm32mp2_clk), 2489 .clks = stm32mp2_clk, 2490 .parents = parent_mp2, 2491 .nb_parents = ARRAY_SIZE(parent_mp2), 2492 .gates = gates_mp2, 2493 .nb_gates = ARRAY_SIZE(gates_mp2), 2494 .div = dividers_mp2, 2495 .nb_div = ARRAY_SIZE(dividers_mp2), 2496 .osci_data = stm32mp2_osc_data, 2497 .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data), 2498 .gate_refcounts = refcounts_mp2, 2499 .pdata = &stm32mp2_pdata, 2500 .ops_array = ops_array_mp2, 2501 }; 2502 2503 int stm32mp2_clk_init(void) 2504 { 2505 uintptr_t base = RCC_BASE; 2506 int ret; 2507 2508 #ifdef IMAGE_BL2 2509 ret = stm32_clk_parse_fdt(&stm32mp2_pdata); 2510 if (ret != 0) { 2511 return ret; 2512 } 2513 #endif 2514 2515 ret = clk_stm32_init(&stm32mp2_clock_data, base); 2516 if (ret != 0) { 2517 return ret; 2518 } 2519 2520 #ifdef IMAGE_BL2 2521 ret = stm32mp2_init_clock_tree(); 2522 if (ret != 0) { 2523 return ret; 2524 } 2525 2526 clk_stm32_enable_critical_clocks(); 2527 #endif 2528 2529 return 0; 2530 } 2531 2532 int stm32mp2_pll1_disable(void) 2533 { 2534 #ifdef IMAGE_BL2 2535 return -EPERM; 2536 #else 2537 uintptr_t a35_ss_address = A35SSC_BASE; 2538 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 2539 2540 stm32mp2_a35_ss_on_hsi(); 2541 2542 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 2543 2544 return 0; 2545 #endif 2546 } 2547