1 /* 2 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include "clk-stm32-core.h" 13 #include <common/fdt_wrappers.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/st/stm32mp2_clk.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <lib/mmio.h> 20 #include <lib/spinlock.h> 21 #include <lib/utils_def.h> 22 #include <libfdt.h> 23 24 #include <platform_def.h> 25 26 struct stm32_osci_dt_cfg { 27 unsigned long freq; 28 uint32_t drive; 29 bool bypass; 30 bool digbyp; 31 bool css; 32 }; 33 34 struct stm32_pll_dt_cfg { 35 uint32_t src; 36 uint32_t frac; 37 uint32_t cfg[PLLCFG_NB]; 38 uint32_t csg[PLLCSG_NB]; 39 bool csg_enabled; 40 bool enabled; 41 }; 42 43 struct stm32_clk_platdata { 44 uintptr_t rcc_base; 45 uint32_t nosci; 46 struct stm32_osci_dt_cfg *osci; 47 uint32_t npll; 48 struct stm32_pll_dt_cfg *pll; 49 uint32_t nflexgen; 50 uint32_t *flexgen; 51 uint32_t nbusclk; 52 uint32_t *busclk; 53 uint32_t nkernelclk; 54 uint32_t *kernelclk; 55 }; 56 57 /* A35 Sub-System which manages its own PLL (PLL1) */ 58 #define A35_SS_CHGCLKREQ 0x0000 59 #define A35_SS_PLL_FREQ1 0x0080 60 #define A35_SS_PLL_FREQ2 0x0090 61 #define A35_SS_PLL_ENABLE 0x00a0 62 63 #define A35_SS_CHGCLKREQ_ARM_CHGCLKREQ BIT(0) 64 #define A35_SS_CHGCLKREQ_ARM_CHGCLKACK BIT(1) 65 #define A35_SS_CHGCLKREQ_ARM_DIVSEL BIT(16) 66 #define A35_SS_CHGCLKREQ_ARM_DIVSELACK BIT(17) 67 68 #define A35_SS_PLL_FREQ1_FBDIV_MASK GENMASK(11, 0) 69 #define A35_SS_PLL_FREQ1_FBDIV_SHIFT 0 70 #define A35_SS_PLL_FREQ1_REFDIV_MASK GENMASK(21, 16) 71 #define A35_SS_PLL_FREQ1_REFDIV_SHIFT 16 72 73 #define A35_SS_PLL_FREQ2_POSTDIV1_MASK GENMASK(2, 0) 74 #define A35_SS_PLL_FREQ2_POSTDIV1_SHIFT 0 75 #define A35_SS_PLL_FREQ2_POSTDIV2_MASK GENMASK(5, 3) 76 #define A35_SS_PLL_FREQ2_POSTDIV2_SHIFT 3 77 78 #define A35_SS_PLL_ENABLE_PD BIT(0) 79 #define A35_SS_PLL_ENABLE_LOCKP BIT(1) 80 #define A35_SS_PLL_ENABLE_NRESET_SWPLL_FF BIT(2) 81 82 #define TIMEOUT_US_200MS U(200000) 83 #define TIMEOUT_US_1S U(1000000) 84 85 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 86 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 87 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 88 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 89 90 /* PLL minimal frequencies for clock sources */ 91 #define PLL_REFCLK_MIN UL(5000000) 92 #define PLL_FRAC_REFCLK_MIN UL(10000000) 93 94 #define XBAR_CHANNEL_NB 64 95 96 /* Warning, should be start to 1 */ 97 enum clock { 98 _CK_0_MHZ, 99 100 /* ROOT CLOCKS */ 101 _CK_HSI, 102 _CK_HSE, 103 _CK_MSI, 104 _CK_LSI, 105 _CK_LSE, 106 _I2SCKIN, 107 _SPDIFSYMB, 108 _CK_PLL1, 109 _CK_PLL2, 110 #if !STM32MP21 111 _CK_PLL3, 112 #endif /* !STM32MP21 */ 113 _CK_PLL4, 114 _CK_PLL5, 115 _CK_PLL6, 116 _CK_PLL7, 117 _CK_PLL8, 118 _CK_HSE_RTC, 119 _CK_RTCCK, 120 _CK_ICN_HS_MCU, 121 _CK_ICN_SDMMC, 122 _CK_ICN_DDR, 123 _CK_ICN_HSL, 124 _CK_ICN_NIC, 125 _CK_ICN_LS_MCU, 126 _CK_FLEXGEN_07, 127 _CK_FLEXGEN_08, 128 _CK_FLEXGEN_09, 129 _CK_FLEXGEN_10, 130 _CK_FLEXGEN_11, 131 _CK_FLEXGEN_12, 132 _CK_FLEXGEN_13, 133 _CK_FLEXGEN_14, 134 _CK_FLEXGEN_15, 135 _CK_FLEXGEN_16, 136 _CK_FLEXGEN_17, 137 _CK_FLEXGEN_18, 138 _CK_FLEXGEN_19, 139 _CK_FLEXGEN_20, 140 _CK_FLEXGEN_21, 141 _CK_FLEXGEN_22, 142 _CK_FLEXGEN_23, 143 _CK_FLEXGEN_24, 144 _CK_FLEXGEN_25, 145 _CK_FLEXGEN_26, 146 _CK_FLEXGEN_27, 147 _CK_FLEXGEN_28, 148 _CK_FLEXGEN_29, 149 _CK_FLEXGEN_30, 150 _CK_FLEXGEN_31, 151 _CK_FLEXGEN_32, 152 _CK_FLEXGEN_33, 153 _CK_FLEXGEN_34, 154 _CK_FLEXGEN_35, 155 _CK_FLEXGEN_36, 156 _CK_FLEXGEN_37, 157 _CK_FLEXGEN_38, 158 _CK_FLEXGEN_39, 159 _CK_FLEXGEN_40, 160 _CK_FLEXGEN_41, 161 _CK_FLEXGEN_42, 162 _CK_FLEXGEN_43, 163 _CK_FLEXGEN_44, 164 _CK_FLEXGEN_45, 165 _CK_FLEXGEN_46, 166 _CK_FLEXGEN_47, 167 _CK_FLEXGEN_48, 168 _CK_FLEXGEN_49, 169 _CK_FLEXGEN_50, 170 _CK_FLEXGEN_51, 171 _CK_FLEXGEN_52, 172 _CK_FLEXGEN_53, 173 _CK_FLEXGEN_54, 174 _CK_FLEXGEN_55, 175 _CK_FLEXGEN_56, 176 _CK_FLEXGEN_57, 177 _CK_FLEXGEN_58, 178 _CK_FLEXGEN_59, 179 _CK_FLEXGEN_60, 180 _CK_FLEXGEN_61, 181 _CK_FLEXGEN_62, 182 _CK_FLEXGEN_63, 183 _CK_ICN_APB1, 184 _CK_ICN_APB2, 185 _CK_ICN_APB3, 186 _CK_ICN_APB4, 187 #if STM32MP21 188 _CK_ICN_APB5, 189 #endif /* STM32MP21 */ 190 _CK_ICN_APBDBG, 191 _CK_BKPSRAM, 192 _CK_BSEC, 193 _CK_CRC, 194 _CK_CRYP1, 195 _CK_CRYP2, 196 _CK_DDR, 197 _CK_DDRCAPB, 198 _CK_DDRCP, 199 _CK_DDRPHYC, 200 _CK_FMC, 201 _CK_GPIOA, 202 _CK_GPIOB, 203 _CK_GPIOC, 204 _CK_GPIOD, 205 _CK_GPIOE, 206 _CK_GPIOF, 207 _CK_GPIOG, 208 _CK_GPIOH, 209 _CK_GPIOI, 210 #if !STM32MP21 211 _CK_GPIOJ, 212 _CK_GPIOK, 213 #endif /* !STM32MP21 */ 214 _CK_GPIOZ, 215 #if STM32MP21 216 _CK_HASH1, 217 _CK_HASH2, 218 #else /* STM32MP21 */ 219 _CK_HASH, 220 #endif /* STM32MP21 */ 221 _CK_I2C1, 222 _CK_I2C2, 223 #if !STM32MP23 224 _CK_I2C3, 225 #endif /* !STM32MP23 */ 226 #if STM32MP25 227 _CK_I2C4, 228 _CK_I2C5, 229 _CK_I2C6, 230 #endif /* STM32MP25 */ 231 #if !STM32MP21 232 _CK_I2C7, 233 _CK_I2C8, 234 #endif /* !STM32MP21 */ 235 _CK_IWDG1, 236 _CK_IWDG2, 237 _CK_OSPI1, 238 #if !STM32MP21 239 _CK_OSPI2, 240 _CK_OSPIIOM, 241 #endif /* !STM32MP21 */ 242 _CK_PKA, 243 _CK_RETRAM, 244 #if STM32MP21 245 _CK_RNG1, 246 _CK_RNG2, 247 #else /* STM32MP21 */ 248 _CK_RNG, 249 #endif /* STM32MP21 */ 250 _CK_RTC, 251 _CK_SAES, 252 _CK_SDMMC1, 253 _CK_SDMMC2, 254 _CK_SRAM1, 255 #if !STM32MP21 256 _CK_SRAM2, 257 #endif /* !STM32MP21 */ 258 _CK_STGEN, 259 _CK_SYSCPU1, 260 _CK_SYSRAM, 261 _CK_UART4, 262 _CK_UART5, 263 _CK_UART7, 264 #if STM32MP25 265 _CK_UART8, 266 _CK_UART9, 267 #endif /* STM32MP25 */ 268 _CK_USART1, 269 _CK_USART2, 270 _CK_USART3, 271 _CK_USART6, 272 #if STM32MP21 273 _CK_USBHEHCI, 274 _CK_USBHOHCI, 275 #else /* STM32MP21 */ 276 _CK_USB2EHCI, 277 _CK_USB2OHCI, 278 #endif /* STM32MP21 */ 279 _CK_USB2PHY1, 280 _CK_USB2PHY2, 281 #if !STM32MP21 282 _CK_USB3DR, 283 _CK_USB3PCIEPHY, 284 _CK_USBTC, 285 #endif /* !STM32MP21 */ 286 _CK_BUS_RISAF4, 287 288 CK_LAST 289 }; 290 291 static const uint16_t muxsel_src[] = { 292 _CK_HSI, _CK_HSE, _CK_MSI, _CK_0_MHZ 293 }; 294 295 static const uint16_t xbarsel_src[] = { 296 _CK_PLL4, _CK_PLL5, _CK_PLL6, _CK_PLL7, _CK_PLL8, 297 _CK_HSI, _CK_HSE, _CK_MSI, _CK_HSI, _CK_HSE, _CK_MSI, 298 _SPDIFSYMB, _I2SCKIN, _CK_LSI, _CK_LSE 299 }; 300 301 static const uint16_t rtc_src[] = { 302 _CK_0_MHZ, _CK_LSE, _CK_LSI, _CK_HSE_RTC 303 }; 304 305 static const uint16_t usb2phy1_src[] = { 306 _CK_FLEXGEN_57, _CK_HSE 307 }; 308 309 static const uint16_t usb2phy2_src[] = { 310 _CK_FLEXGEN_58, _CK_HSE 311 }; 312 313 #if !STM32MP21 314 static const uint16_t usb3pciphy_src[] = { 315 _CK_FLEXGEN_34, _CK_HSE 316 }; 317 318 static const uint16_t d3per_src[] = { 319 _CK_MSI, _CK_LSI, _CK_LSE 320 }; 321 #endif /* !STM32MP21 */ 322 323 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\ 324 .id_parents = src,\ 325 .num_parents = ARRAY_SIZE(src),\ 326 .mux = &(struct mux_cfg) {\ 327 .offset = (_offset),\ 328 .shift = (_shift),\ 329 .width = (_witdh),\ 330 .bitrdy = UINT8_MAX,\ 331 },\ 332 } 333 334 static const struct parent_cfg parent_mp2[] = { 335 MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2), 336 MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2), 337 MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2), 338 MUX_CONF(MUX_MUXSEL3, muxsel_src, RCC_MUXSELCFGR, 12, 2), 339 MUX_CONF(MUX_MUXSEL4, muxsel_src, RCC_MUXSELCFGR, 16, 2), 340 MUX_CONF(MUX_MUXSEL5, muxsel_src, RCC_MUXSELCFGR, 20, 2), 341 MUX_CONF(MUX_MUXSEL6, muxsel_src, RCC_MUXSELCFGR, 24, 2), 342 MUX_CONF(MUX_MUXSEL7, muxsel_src, RCC_MUXSELCFGR, 28, 2), 343 MUX_CONF(MUX_XBARSEL, xbarsel_src, RCC_XBAR0CFGR, 0, 4), 344 MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2), 345 MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1), 346 MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1), 347 #if !STM32MP21 348 MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1), 349 MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2), 350 #endif /* !STM32MP21 */ 351 }; 352 353 /* GATES */ 354 enum enum_gate_cfg { 355 GATE_ZERO, /* reserved for no gate */ 356 GATE_LSE, 357 GATE_RTCCK, 358 GATE_LSI, 359 GATE_HSI, 360 GATE_MSI, 361 GATE_HSE, 362 GATE_LSI_RDY, 363 GATE_MSI_RDY, 364 GATE_LSE_RDY, 365 GATE_HSE_RDY, 366 GATE_HSI_RDY, 367 GATE_SYSRAM, 368 GATE_RETRAM, 369 GATE_SRAM1, 370 #if !STM32MP21 371 GATE_SRAM2, 372 #endif /* !STM32MP21 */ 373 374 GATE_DDRPHYC, 375 GATE_SYSCPU1, 376 GATE_CRC, 377 #if !STM32MP21 378 GATE_OSPIIOM, 379 #endif /* !STM32MP21 */ 380 GATE_BKPSRAM, 381 #if STM32MP21 382 GATE_HASH1, 383 GATE_HASH2, 384 GATE_RNG1, 385 GATE_RNG2, 386 #else /* STM32MP21 */ 387 GATE_HASH, 388 GATE_RNG, 389 #endif /* STM32MP21 */ 390 GATE_CRYP1, 391 GATE_CRYP2, 392 GATE_SAES, 393 GATE_PKA, 394 395 GATE_GPIOA, 396 GATE_GPIOB, 397 GATE_GPIOC, 398 GATE_GPIOD, 399 GATE_GPIOE, 400 GATE_GPIOF, 401 GATE_GPIOG, 402 GATE_GPIOH, 403 GATE_GPIOI, 404 #if !STM32MP21 405 GATE_GPIOJ, 406 GATE_GPIOK, 407 #endif /* !STM32MP21 */ 408 GATE_GPIOZ, 409 GATE_RTC, 410 411 GATE_DDRCP, 412 413 /* WARNING 2 CLOCKS FOR ONE GATE */ 414 #if STM32MP21 415 GATE_USBHOHCI, 416 GATE_USBHEHCI, 417 #else /* STM32MP21 */ 418 GATE_USB2OHCI, 419 GATE_USB2EHCI, 420 #endif /* STM32MP21 */ 421 422 #if !STM32MP21 423 GATE_USB3DR, 424 #endif /* !STM32MP21 */ 425 426 GATE_BSEC, 427 GATE_IWDG1, 428 GATE_IWDG2, 429 430 GATE_DDRCAPB, 431 GATE_DDR, 432 433 GATE_USART2, 434 GATE_UART4, 435 GATE_USART3, 436 GATE_UART5, 437 GATE_I2C1, 438 GATE_I2C2, 439 #if !STM32MP23 440 GATE_I2C3, 441 #endif /* !STM32MP23 */ 442 #if STM32MP25 443 GATE_I2C5, 444 GATE_I2C4, 445 GATE_I2C6, 446 #endif /* STM32MP25 */ 447 #if !STM32MP21 448 GATE_I2C7, 449 #endif /* !STM32MP21 */ 450 GATE_USART1, 451 GATE_USART6, 452 GATE_UART7, 453 #if STM32MP25 454 GATE_UART8, 455 GATE_UART9, 456 #endif /* STM32MP25 */ 457 GATE_STGEN, 458 #if !STM32MP21 459 GATE_USB3PCIEPHY, 460 GATE_USBTC, 461 GATE_I2C8, 462 #endif /* !STM32MP21 */ 463 GATE_OSPI1, 464 #if !STM32MP21 465 GATE_OSPI2, 466 #endif /* !STM32MP21 */ 467 GATE_FMC, 468 GATE_SDMMC1, 469 GATE_SDMMC2, 470 GATE_USB2PHY1, 471 GATE_USB2PHY2, 472 LAST_GATE 473 }; 474 475 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ 476 .offset = (_offset),\ 477 .bit_idx = (_bit_idx),\ 478 .set_clr = (_offset_clr),\ 479 } 480 481 static const struct gate_cfg gates_mp2[LAST_GATE] = { 482 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 483 #if STM32MP21 484 GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0), 485 #else /* STM32MP21 */ 486 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0), 487 #endif /* STM32MP21 */ 488 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 489 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 490 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 491 #if STM32MP21 492 GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0), 493 #else /* STM32MP21 */ 494 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0), 495 #endif /* STM32MP21 */ 496 497 #if STM32MP21 498 GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0), 499 #else /* STM32MP21 */ 500 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0), 501 #endif /* STM32MP21 */ 502 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 503 #if STM32MP21 504 GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0), 505 #else /* STM32MP21 */ 506 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0), 507 #endif /* STM32MP21 */ 508 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 509 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 510 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0), 511 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0), 512 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0), 513 #if !STM32MP21 514 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0), 515 #endif /* !STM32MP21 */ 516 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0), 517 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0), 518 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 519 #if !STM32MP21 520 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), 521 #endif /* !STM32MP21 */ 522 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0), 523 #if STM32MP21 524 GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0), 525 GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0), 526 GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0), 527 GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0), 528 #else /* STM32MP21 */ 529 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), 530 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), 531 #endif /* STM32MP21 */ 532 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 533 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 534 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 535 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 536 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0), 537 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0), 538 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0), 539 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0), 540 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0), 541 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0), 542 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0), 543 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0), 544 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0), 545 #if !STM32MP21 546 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0), 547 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0), 548 #endif /* !STM32MP21 */ 549 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0), 550 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0), 551 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0), 552 553 /* WARNING 2 CLOCKS FOR ONE GATE */ 554 #if STM32MP21 555 GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0), 556 GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0), 557 #else /* STM32MP21 */ 558 GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0), 559 GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0), 560 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), 561 #endif /* STM32MP21 */ 562 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0), 563 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 564 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 565 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0), 566 GATE_CFG(GATE_DDR, RCC_DDRCFGR, 1, 0), 567 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 568 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 569 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 570 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 571 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 572 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 573 #if !STM32MP23 574 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 575 #endif /* !STM32MP23 */ 576 #if STM32MP25 577 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), 578 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), 579 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), 580 #endif /* STM32MP25 */ 581 #if !STM32MP21 582 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), 583 #endif /* !STM32MP21 */ 584 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 585 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 586 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 587 #if STM32MP25 588 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), 589 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), 590 #endif /* STM32MP25 */ 591 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), 592 #if !STM32MP21 593 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), 594 GATE_CFG(GATE_USBTC, RCC_UCPDCFGR, 1, 0), 595 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), 596 #endif /* !STM32MP21 */ 597 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), 598 #if !STM32MP21 599 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), 600 #endif /* !STM32MP21 */ 601 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0), 602 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 603 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 604 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 605 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 606 }; 607 608 static const struct clk_div_table apb_div_table[] = { 609 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 }, 610 { 5, 16 }, { 6, 16 }, { 7, 16 }, { 0 }, 611 }; 612 613 #undef DIV_CFG 614 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ 615 .offset = _offset,\ 616 .shift = _shift,\ 617 .width = _width,\ 618 .flags = _flags,\ 619 .table = _table,\ 620 .bitrdy = _bitrdy,\ 621 } 622 623 static const struct div_cfg dividers_mp2[] = { 624 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), 625 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), 626 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), 627 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), 628 #if STM32MP21 629 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31), 630 #endif /* STM32MP21 */ 631 DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31), 632 DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31), 633 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0), 634 }; 635 636 enum stm32_osc { 637 OSC_HSI, 638 OSC_HSE, 639 OSC_MSI, 640 OSC_LSI, 641 OSC_LSE, 642 OSC_I2SCKIN, 643 OSC_SPDIFSYMB, 644 NB_OSCILLATOR 645 }; 646 647 static struct clk_oscillator_data stm32mp2_osc_data[] = { 648 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, 649 NULL, NULL, NULL), 650 651 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, 652 NULL, NULL, NULL), 653 654 OSCILLATOR(OSC_MSI, _CK_MSI, "clk-msi", GATE_MSI, GATE_MSI_RDY, 655 NULL, NULL, NULL), 656 657 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, 658 BYPASS(RCC_OCENSETR, 10, 7), 659 CSS(RCC_OCENSETR, 11), 660 NULL), 661 662 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, 663 BYPASS(RCC_BDCR, 1, 3), 664 CSS(RCC_BDCR, 8), 665 DRIVE(RCC_BDCR, 4, 2, 2)), 666 667 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, 668 NULL, NULL, NULL), 669 670 OSCILLATOR(OSC_SPDIFSYMB, _SPDIFSYMB, "spdif_symb", NO_GATE, NO_GATE, 671 NULL, NULL, NULL), 672 }; 673 674 #ifdef IMAGE_BL2 675 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) 676 { 677 if (id < NB_OSCILLATOR) { 678 return stm32mp2_osc_data[id].name; 679 } 680 681 return NULL; 682 } 683 #endif 684 685 enum pll_id { 686 _PLL1, 687 _PLL2, 688 _PLL3, 689 _PLL4, 690 _PLL5, 691 _PLL6, 692 _PLL7, 693 _PLL8, 694 _PLL_NB 695 }; 696 697 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */ 698 #define RCC_OFFSET_PLLXCFGR1 0x00 699 #define RCC_OFFSET_PLLXCFGR2 0x04 700 #define RCC_OFFSET_PLLXCFGR3 0x08 701 #define RCC_OFFSET_PLLXCFGR4 0x0C 702 #define RCC_OFFSET_PLLXCFGR5 0x10 703 #define RCC_OFFSET_PLLXCFGR6 0x18 704 #define RCC_OFFSET_PLLXCFGR7 0x1C 705 706 struct stm32_clk_pll { 707 uint16_t clk_id; 708 uint16_t reg_pllxcfgr1; 709 }; 710 711 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\ 712 [(_idx)] = {\ 713 .clk_id = (_clk_id),\ 714 .reg_pllxcfgr1 = (_reg),\ 715 } 716 717 static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = { 718 CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ), 719 CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1), 720 #if !STM32MP21 721 CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1), 722 #endif /* !STM32MP21 */ 723 CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1), 724 CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1), 725 CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1), 726 CLK_PLL_CFG(_PLL7, _CK_PLL7, RCC_PLL7CFGR1), 727 CLK_PLL_CFG(_PLL8, _CK_PLL8, RCC_PLL8CFGR1), 728 }; 729 730 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 731 { 732 return &stm32mp2_clk_pll[idx]; 733 } 734 735 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv, 736 const struct stm32_clk_pll *pll, 737 unsigned long prate) 738 { 739 unsigned long refclk, fvco; 740 uint32_t fracin, fbdiv, refdiv; 741 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 742 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 743 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 744 745 refclk = prate; 746 747 fracin = mmio_read_32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK; 748 fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> 749 RCC_PLLxCFGR2_FBDIV_SHIFT; 750 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; 751 752 if (fracin != 0U) { 753 uint64_t numerator, denominator; 754 755 numerator = ((uint64_t)fbdiv << 24) + fracin; 756 numerator = refclk * numerator; 757 denominator = (uint64_t)refdiv << 24; 758 fvco = (unsigned long)(numerator / denominator); 759 } else { 760 fvco = (unsigned long)(refclk * fbdiv / refdiv); 761 } 762 763 return fvco; 764 } 765 766 struct stm32_pll_cfg { 767 uint16_t pll_id; 768 }; 769 770 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 771 { 772 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 773 774 return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U); 775 } 776 777 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 778 { 779 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 780 781 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 782 } 783 784 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 785 { 786 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 787 788 /* Stop PLL */ 789 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 790 } 791 792 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, 793 const struct stm32_clk_pll *pll) 794 { 795 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 796 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 797 798 /* Wait PLL lock */ 799 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) { 800 if (timeout_elapsed(timeout)) { 801 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 802 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1, 803 mmio_read_32(pllxcfgr1)); 804 return -ETIMEDOUT; 805 } 806 } 807 808 return 0; 809 } 810 811 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, 812 const struct stm32_clk_pll *pll) 813 { 814 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 815 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 816 817 /* Wait PLL stopped */ 818 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) { 819 if (timeout_elapsed(timeout)) { 820 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 821 pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1)); 822 return -ETIMEDOUT; 823 } 824 } 825 826 return 0; 827 } 828 829 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 830 { 831 if (_clk_stm32_pll_is_enabled(priv, pll)) { 832 return 0; 833 } 834 835 _clk_stm32_pll_set_on(priv, pll); 836 837 return _clk_stm32_pll_wait_ready_on(priv, pll); 838 } 839 840 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 841 { 842 if (!_clk_stm32_pll_is_enabled(priv, pll)) { 843 return; 844 } 845 846 _clk_stm32_pll_set_off(priv, pll); 847 848 _clk_stm32_pll_wait_ready_off(priv, pll); 849 } 850 851 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) 852 { 853 const struct clk_stm32 *clk = _clk_get(priv, id); 854 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 855 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 856 857 return _clk_stm32_pll_is_enabled(priv, pll); 858 } 859 860 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) 861 { 862 const struct clk_stm32 *clk = _clk_get(priv, id); 863 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 864 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 865 866 return _clk_stm32_pll_enable(priv, pll); 867 } 868 869 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) 870 { 871 const struct clk_stm32 *clk = _clk_get(priv, id); 872 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 873 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 874 875 _clk_stm32_pll_disable(priv, pll); 876 } 877 878 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, 879 unsigned long prate) 880 { 881 const struct clk_stm32 *clk = _clk_get(priv, id); 882 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 883 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 884 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 885 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 886 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 887 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 888 unsigned long dfout; 889 uint32_t postdiv1, postdiv2; 890 891 postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; 892 postdiv2 = mmio_read_32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; 893 894 if ((mmio_read_32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) != 0U) { 895 dfout = prate; 896 } else { 897 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 898 dfout = prate; 899 } else { 900 dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2); 901 } 902 } 903 904 return dfout; 905 } 906 907 static const struct stm32_clk_ops clk_stm32_pll_ops = { 908 .recalc_rate = clk_stm32_pll_recalc_rate, 909 .enable = clk_stm32_pll_enable, 910 .disable = clk_stm32_pll_disable, 911 .is_enabled = clk_stm32_pll_is_enabled, 912 }; 913 914 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 915 .binding = _idx,\ 916 .parent = _parent,\ 917 .flags = (_flags),\ 918 .clock_cfg = &(struct stm32_pll_cfg) {\ 919 .pll_id = _pll_id,\ 920 },\ 921 .ops = STM32_PLL_OPS,\ 922 } 923 924 static unsigned long clk_get_pll1_fvco(unsigned long refclk) 925 { 926 uintptr_t pll_freq1_reg = A35SSC_BASE + A35_SS_PLL_FREQ1; 927 uint32_t reg, fbdiv, refdiv; 928 929 reg = mmio_read_32(pll_freq1_reg); 930 931 fbdiv = (reg & A35_SS_PLL_FREQ1_FBDIV_MASK) >> A35_SS_PLL_FREQ1_FBDIV_SHIFT; 932 refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT; 933 934 return (unsigned long)(refclk * fbdiv / refdiv); 935 } 936 937 static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv, 938 int id, unsigned long prate) 939 { 940 uintptr_t pll_freq2_reg = A35SSC_BASE + A35_SS_PLL_FREQ2; 941 uint32_t postdiv1, postdiv2; 942 unsigned long dfout; 943 944 postdiv1 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV1_MASK) >> 945 A35_SS_PLL_FREQ2_POSTDIV1_SHIFT; 946 postdiv2 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV2_MASK) >> 947 A35_SS_PLL_FREQ2_POSTDIV2_SHIFT; 948 949 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 950 dfout = prate; 951 } else { 952 dfout = clk_get_pll1_fvco(prate) / (postdiv1 * postdiv2); 953 } 954 955 return dfout; 956 } 957 958 static const struct stm32_clk_ops clk_stm32_pll1_ops = { 959 .recalc_rate = clk_stm32_pll1_recalc_rate, 960 }; 961 962 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 963 .binding = _idx,\ 964 .parent = _parent,\ 965 .flags = (_flags),\ 966 .clock_cfg = &(struct stm32_pll_cfg) {\ 967 .pll_id = _pll_id,\ 968 },\ 969 .ops = STM32_PLL1_OPS,\ 970 } 971 972 struct stm32_clk_flexgen_cfg { 973 uint8_t id; 974 }; 975 976 static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx, 977 unsigned long prate) 978 { 979 const struct clk_stm32 *clk = _clk_get(priv, idx); 980 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 981 uintptr_t rcc_base = priv->base; 982 uint32_t prediv, findiv; 983 uint8_t channel = cfg->id; 984 unsigned long freq = prate; 985 986 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) & 987 RCC_PREDIVxCFGR_PREDIVx_MASK; 988 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 989 RCC_FINDIVxCFGR_FINDIVx_MASK; 990 991 if (freq == 0UL) { 992 return 0U; 993 } 994 995 switch (prediv) { 996 case 0x0: 997 case 0x1: 998 case 0x3: 999 case 0x3FF: 1000 break; 1001 1002 default: 1003 ERROR("Unsupported PREDIV value (%x)\n", prediv); 1004 panic(); 1005 break; 1006 } 1007 1008 freq /= (prediv + 1U); 1009 freq /= (findiv + 1U); 1010 1011 return freq; 1012 } 1013 1014 static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx) 1015 { 1016 const struct clk_stm32 *clk = _clk_get(priv, idx); 1017 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1018 uint32_t sel; 1019 uint32_t address; 1020 uintptr_t rcc_base = priv->base; 1021 1022 address = RCC_XBAR0CFGR + (cfg->id * 4); 1023 1024 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK; 1025 1026 return sel; 1027 } 1028 1029 static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx) 1030 { 1031 const struct clk_stm32 *clk = _clk_get(priv, idx); 1032 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1033 uintptr_t rcc_base = priv->base; 1034 uint8_t channel = cfg->id; 1035 1036 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1037 RCC_FINDIVxCFGR_FINDIVxEN); 1038 1039 return 0; 1040 } 1041 1042 static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id) 1043 { 1044 const struct clk_stm32 *clk = _clk_get(priv, id); 1045 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1046 uintptr_t rcc_base = priv->base; 1047 uint8_t channel = cfg->id; 1048 1049 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1050 RCC_FINDIVxCFGR_FINDIVxEN); 1051 } 1052 1053 static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id) 1054 { 1055 const struct clk_stm32 *clk = _clk_get(priv, id); 1056 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 1057 uintptr_t rcc_base = priv->base; 1058 uint8_t channel = cfg->id; 1059 1060 return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 1061 RCC_FINDIVxCFGR_FINDIVxEN); 1062 } 1063 1064 static const struct stm32_clk_ops clk_stm32_flexgen_ops = { 1065 .recalc_rate = clk_flexgen_recalc, 1066 .get_parent = clk_flexgen_get_parent, 1067 .enable = clk_flexgen_gate_enable, 1068 .disable = clk_flexgen_gate_disable, 1069 .is_enabled = clk_flexgen_gate_is_enabled, 1070 }; 1071 1072 #define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\ 1073 .binding = _idx,\ 1074 .parent = MUX(MUX_XBARSEL),\ 1075 .flags = (_flags),\ 1076 .clock_cfg = &(struct stm32_clk_flexgen_cfg) {\ 1077 .id = _id,\ 1078 },\ 1079 .ops = STM32_FLEXGEN_OPS,\ 1080 } 1081 1082 #define RCC_0_MHZ UL(0) 1083 #define RCC_4_MHZ UL(4000000) 1084 #define RCC_16_MHZ UL(16000000) 1085 1086 #ifdef IMAGE_BL2 1087 #if !STM32MP21 1088 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, 1089 unsigned long prate) 1090 { 1091 uintptr_t address = priv->base + RCC_BDCR; 1092 uint32_t mask = RCC_BDCR_MSIFREQSEL; 1093 int ret = -1; 1094 1095 switch (rate) { 1096 case RCC_4_MHZ: 1097 mmio_clrbits_32(address, mask); 1098 ret = 0; 1099 break; 1100 1101 case RCC_16_MHZ: 1102 mmio_setbits_32(address, mask); 1103 ret = 0; 1104 break; 1105 1106 default: 1107 break; 1108 } 1109 1110 return ret; 1111 } 1112 #endif /* !STM32MP21 */ 1113 #endif /* IMAGE_BL2 */ 1114 1115 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv, 1116 int id __unused, 1117 unsigned long prate __unused) 1118 { 1119 #if STM32MP21 1120 return RCC_16_MHZ; 1121 #else /* STM32MP21 */ 1122 uintptr_t address = priv->base + RCC_BDCR; 1123 1124 if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) { 1125 return RCC_4_MHZ; 1126 } else { 1127 return RCC_16_MHZ; 1128 } 1129 #endif /* STM32MP21 */ 1130 } 1131 1132 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = { 1133 .recalc_rate = clk_stm32_osc_msi_recalc_rate, 1134 .is_enabled = clk_stm32_osc_gate_is_enabled, 1135 .enable = clk_stm32_osc_gate_enable, 1136 .disable = clk_stm32_osc_gate_disable, 1137 .init = clk_stm32_osc_init, 1138 }; 1139 1140 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \ 1141 [(idx)] = (struct clk_stm32){ \ 1142 .binding = (_idx),\ 1143 .parent = (_parent),\ 1144 .flags = CLK_IS_CRITICAL,\ 1145 .clock_cfg = &(struct stm32_osc_cfg){\ 1146 .osc_id = (_osc_id),\ 1147 },\ 1148 .ops = STM32_OSC_MSI_OPS,\ 1149 } 1150 1151 static const struct stm32_clk_ops clk_stm32_rtc_ops = { 1152 .enable = clk_stm32_gate_enable, 1153 .disable = clk_stm32_gate_disable, 1154 .is_enabled = clk_stm32_gate_is_enabled, 1155 }; 1156 1157 #define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\ 1158 .binding = (_binding),\ 1159 .parent = (_parent),\ 1160 .flags = (_flags),\ 1161 .clock_cfg = &(struct clk_stm32_gate_cfg) {\ 1162 .id = (_gate_id),\ 1163 },\ 1164 .ops = STM32_RTC_OPS,\ 1165 } 1166 1167 enum { 1168 STM32_PLL_OPS = STM32_LAST_OPS, 1169 STM32_PLL1_OPS, 1170 STM32_FLEXGEN_OPS, 1171 STM32_OSC_MSI_OPS, 1172 STM32_RTC_OPS, 1173 1174 MP2_LAST_OPS 1175 }; 1176 1177 static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = { 1178 [NO_OPS] = NULL, 1179 [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops, 1180 [GATE_OPS] = &clk_gate_ops, 1181 [STM32_MUX_OPS] = &clk_mux_ops, 1182 [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops, 1183 [STM32_GATE_OPS] = &clk_stm32_gate_ops, 1184 [STM32_TIMER_OPS] = &clk_timer_ops, 1185 [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops, 1186 [STM32_OSC_OPS] = &clk_stm32_osc_ops, 1187 [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops, 1188 1189 [STM32_PLL_OPS] = &clk_stm32_pll_ops, 1190 [STM32_PLL1_OPS] = &clk_stm32_pll1_ops, 1191 [STM32_FLEXGEN_OPS] = &clk_stm32_flexgen_ops, 1192 [STM32_OSC_MSI_OPS] = &clk_stm32_osc_msi_ops, 1193 [STM32_RTC_OPS] = &clk_stm32_rtc_ops 1194 }; 1195 1196 static const struct clk_stm32 stm32mp2_clk[CK_LAST] = { 1197 CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ), 1198 1199 /* ROOT CLOCKS */ 1200 CLK_OSC(_CK_HSE, HSE_CK, CLK_IS_ROOT, OSC_HSE), 1201 CLK_OSC(_CK_LSE, LSE_CK, CLK_IS_ROOT, OSC_LSE), 1202 CLK_OSC(_CK_HSI, HSI_CK, CLK_IS_ROOT, OSC_HSI), 1203 CLK_OSC(_CK_LSI, LSI_CK, CLK_IS_ROOT, OSC_LSI), 1204 CLK_OSC_MSI(_CK_MSI, MSI_CK, CLK_IS_ROOT, OSC_MSI), 1205 1206 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), 1207 CLK_OSC_FIXED(_SPDIFSYMB, _NO_ID, CLK_IS_ROOT, OSC_SPDIFSYMB), 1208 1209 STM32_DIV(_CK_HSE_RTC, _NO_ID, _CK_HSE, 0, DIV_RTC), 1210 1211 CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK), 1212 1213 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0), 1214 1215 CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0), 1216 #if !STM32MP21 1217 CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0), 1218 #endif /* !STM32MP21 */ 1219 CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0), 1220 CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0), 1221 CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0), 1222 CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0), 1223 CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0), 1224 1225 FLEXGEN(_CK_ICN_HS_MCU, CK_ICN_HS_MCU, CLK_IS_CRITICAL, 0), 1226 FLEXGEN(_CK_ICN_SDMMC, CK_ICN_SDMMC, CLK_IS_CRITICAL, 1), 1227 FLEXGEN(_CK_ICN_DDR, CK_ICN_DDR, CLK_IS_CRITICAL, 2), 1228 FLEXGEN(_CK_ICN_HSL, CK_ICN_HSL, CLK_IS_CRITICAL, 4), 1229 FLEXGEN(_CK_ICN_NIC, CK_ICN_NIC, CLK_IS_CRITICAL, 5), 1230 1231 STM32_DIV(_CK_ICN_LS_MCU, CK_ICN_LS_MCU, _CK_ICN_HS_MCU, 0, DIV_LSMCU), 1232 1233 FLEXGEN(_CK_FLEXGEN_07, CK_FLEXGEN_07, 0, 7), 1234 FLEXGEN(_CK_FLEXGEN_08, CK_FLEXGEN_08, 0, 8), 1235 FLEXGEN(_CK_FLEXGEN_09, CK_FLEXGEN_09, 0, 9), 1236 FLEXGEN(_CK_FLEXGEN_10, CK_FLEXGEN_10, 0, 10), 1237 FLEXGEN(_CK_FLEXGEN_11, CK_FLEXGEN_11, 0, 11), 1238 FLEXGEN(_CK_FLEXGEN_12, CK_FLEXGEN_12, 0, 12), 1239 FLEXGEN(_CK_FLEXGEN_13, CK_FLEXGEN_13, 0, 13), 1240 FLEXGEN(_CK_FLEXGEN_14, CK_FLEXGEN_14, 0, 14), 1241 FLEXGEN(_CK_FLEXGEN_15, CK_FLEXGEN_15, 0, 15), 1242 FLEXGEN(_CK_FLEXGEN_16, CK_FLEXGEN_16, 0, 16), 1243 FLEXGEN(_CK_FLEXGEN_17, CK_FLEXGEN_17, 0, 17), 1244 FLEXGEN(_CK_FLEXGEN_18, CK_FLEXGEN_18, 0, 18), 1245 FLEXGEN(_CK_FLEXGEN_19, CK_FLEXGEN_19, 0, 19), 1246 FLEXGEN(_CK_FLEXGEN_20, CK_FLEXGEN_20, 0, 20), 1247 FLEXGEN(_CK_FLEXGEN_21, CK_FLEXGEN_21, 0, 21), 1248 FLEXGEN(_CK_FLEXGEN_22, CK_FLEXGEN_22, 0, 22), 1249 FLEXGEN(_CK_FLEXGEN_23, CK_FLEXGEN_23, 0, 23), 1250 FLEXGEN(_CK_FLEXGEN_24, CK_FLEXGEN_24, 0, 24), 1251 FLEXGEN(_CK_FLEXGEN_25, CK_FLEXGEN_25, 0, 25), 1252 FLEXGEN(_CK_FLEXGEN_26, CK_FLEXGEN_26, 0, 26), 1253 FLEXGEN(_CK_FLEXGEN_27, CK_FLEXGEN_27, 0, 27), 1254 FLEXGEN(_CK_FLEXGEN_28, CK_FLEXGEN_28, 0, 28), 1255 FLEXGEN(_CK_FLEXGEN_29, CK_FLEXGEN_29, 0, 29), 1256 FLEXGEN(_CK_FLEXGEN_30, CK_FLEXGEN_30, 0, 30), 1257 FLEXGEN(_CK_FLEXGEN_31, CK_FLEXGEN_31, 0, 31), 1258 FLEXGEN(_CK_FLEXGEN_32, CK_FLEXGEN_32, 0, 32), 1259 FLEXGEN(_CK_FLEXGEN_33, CK_FLEXGEN_33, 0, 33), 1260 FLEXGEN(_CK_FLEXGEN_34, CK_FLEXGEN_34, 0, 34), 1261 FLEXGEN(_CK_FLEXGEN_35, CK_FLEXGEN_35, 0, 35), 1262 FLEXGEN(_CK_FLEXGEN_36, CK_FLEXGEN_36, 0, 36), 1263 FLEXGEN(_CK_FLEXGEN_37, CK_FLEXGEN_37, 0, 37), 1264 FLEXGEN(_CK_FLEXGEN_38, CK_FLEXGEN_38, 0, 38), 1265 FLEXGEN(_CK_FLEXGEN_39, CK_FLEXGEN_39, 0, 39), 1266 FLEXGEN(_CK_FLEXGEN_40, CK_FLEXGEN_40, 0, 40), 1267 FLEXGEN(_CK_FLEXGEN_41, CK_FLEXGEN_41, 0, 41), 1268 FLEXGEN(_CK_FLEXGEN_42, CK_FLEXGEN_42, 0, 42), 1269 FLEXGEN(_CK_FLEXGEN_43, CK_FLEXGEN_43, 0, 43), 1270 FLEXGEN(_CK_FLEXGEN_44, CK_FLEXGEN_44, 0, 44), 1271 FLEXGEN(_CK_FLEXGEN_45, CK_FLEXGEN_45, 0, 45), 1272 FLEXGEN(_CK_FLEXGEN_46, CK_FLEXGEN_46, 0, 46), 1273 FLEXGEN(_CK_FLEXGEN_47, CK_FLEXGEN_47, 0, 47), 1274 FLEXGEN(_CK_FLEXGEN_48, CK_FLEXGEN_48, 0, 48), 1275 FLEXGEN(_CK_FLEXGEN_49, CK_FLEXGEN_49, 0, 49), 1276 FLEXGEN(_CK_FLEXGEN_50, CK_FLEXGEN_50, 0, 50), 1277 FLEXGEN(_CK_FLEXGEN_51, CK_FLEXGEN_51, 0, 51), 1278 FLEXGEN(_CK_FLEXGEN_52, CK_FLEXGEN_52, 0, 52), 1279 FLEXGEN(_CK_FLEXGEN_53, CK_FLEXGEN_53, 0, 53), 1280 FLEXGEN(_CK_FLEXGEN_54, CK_FLEXGEN_54, 0, 54), 1281 FLEXGEN(_CK_FLEXGEN_55, CK_FLEXGEN_55, 0, 55), 1282 FLEXGEN(_CK_FLEXGEN_56, CK_FLEXGEN_56, 0, 56), 1283 FLEXGEN(_CK_FLEXGEN_57, CK_FLEXGEN_57, 0, 57), 1284 FLEXGEN(_CK_FLEXGEN_58, CK_FLEXGEN_58, 0, 58), 1285 FLEXGEN(_CK_FLEXGEN_59, CK_FLEXGEN_59, 0, 59), 1286 FLEXGEN(_CK_FLEXGEN_60, CK_FLEXGEN_60, 0, 60), 1287 FLEXGEN(_CK_FLEXGEN_61, CK_FLEXGEN_61, 0, 61), 1288 FLEXGEN(_CK_FLEXGEN_62, CK_FLEXGEN_62, 0, 62), 1289 FLEXGEN(_CK_FLEXGEN_63, CK_FLEXGEN_63, 0, 63), 1290 1291 STM32_DIV(_CK_ICN_APB1, CK_ICN_APB1, _CK_ICN_LS_MCU, 0, DIV_APB1), 1292 STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2), 1293 STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3), 1294 STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4), 1295 #if STM32MP21 1296 STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5), 1297 #endif /* STM32MP21 */ 1298 STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG), 1299 1300 /* KERNEL CLOCK */ 1301 STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM), 1302 STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM), 1303 STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1), 1304 #if !STM32MP21 1305 STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2), 1306 #endif /* !STM32MP21 */ 1307 1308 STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC), 1309 STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1), 1310 STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC), 1311 #if !STM32MP21 1312 STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM), 1313 #endif /* !STM32MP21 */ 1314 STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM), 1315 #if STM32MP21 1316 STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1), 1317 STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2), 1318 STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1), 1319 STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2), 1320 #else /* STM32MP21 */ 1321 STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH), 1322 STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG), 1323 #endif /* STM32MP21 */ 1324 STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1), 1325 STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2), 1326 STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES), 1327 STM32_GATE(_CK_PKA, CK_BUS_PKA, _CK_ICN_LS_MCU, 0, GATE_PKA), 1328 1329 STM32_GATE(_CK_GPIOA, CK_BUS_GPIOA, _CK_ICN_LS_MCU, 0, GATE_GPIOA), 1330 STM32_GATE(_CK_GPIOB, CK_BUS_GPIOB, _CK_ICN_LS_MCU, 0, GATE_GPIOB), 1331 STM32_GATE(_CK_GPIOC, CK_BUS_GPIOC, _CK_ICN_LS_MCU, 0, GATE_GPIOC), 1332 STM32_GATE(_CK_GPIOD, CK_BUS_GPIOD, _CK_ICN_LS_MCU, 0, GATE_GPIOD), 1333 STM32_GATE(_CK_GPIOE, CK_BUS_GPIOE, _CK_ICN_LS_MCU, 0, GATE_GPIOE), 1334 STM32_GATE(_CK_GPIOF, CK_BUS_GPIOF, _CK_ICN_LS_MCU, 0, GATE_GPIOF), 1335 STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG), 1336 STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH), 1337 STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI), 1338 #if !STM32MP21 1339 STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ), 1340 STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK), 1341 #endif /* !STM32MP21 */ 1342 STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ), 1343 STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC), 1344 1345 STM32_GATE(_CK_BUS_RISAF4, CK_BUS_RISAF4, _CK_ICN_LS_MCU, CLK_IS_CRITICAL, GATE_DDRCP), 1346 STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, CLK_IS_CRITICAL, GATE_DDRCP), 1347 1348 /* WARNING 2 CLOCKS FOR ONE GATE */ 1349 #if STM32MP21 1350 STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI), 1351 STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI), 1352 #else /* STM32MP21 */ 1353 STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI), 1354 STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI), 1355 #endif /* STM32MP21 */ 1356 1357 #if !STM32MP21 1358 STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR), 1359 #endif /* !STM32MP21 */ 1360 1361 STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC), 1362 STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1), 1363 STM32_GATE(_CK_IWDG2, CK_BUS_IWDG2, _CK_ICN_APB3, 0, GATE_IWDG2), 1364 1365 STM32_GATE(_CK_DDRCAPB, CK_BUS_DDRC, _CK_ICN_APB4, 0, GATE_DDRCAPB), 1366 STM32_GATE(_CK_DDR, CK_BUS_DDRCFG, _CK_ICN_APB4, 0, GATE_DDR), 1367 1368 STM32_GATE(_CK_USART2, CK_KER_USART2, _CK_FLEXGEN_08, 0, GATE_USART2), 1369 STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4), 1370 STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3), 1371 STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5), 1372 #if STM32MP21 1373 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1), 1374 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2), 1375 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1), 1376 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6), 1377 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7), 1378 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3), 1379 #else /* STM32MP21 */ 1380 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1), 1381 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2), 1382 #if STM32MP25 1383 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3), 1384 STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5), 1385 STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4), 1386 STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6), 1387 #endif /* STM32MP25 */ 1388 STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7), 1389 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1), 1390 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6), 1391 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7), 1392 #if STM32MP25 1393 STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8), 1394 STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9), 1395 #endif /* STM32MP25 */ 1396 #endif /* STM32MP21 */ 1397 STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN), 1398 #if !STM32MP21 1399 STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY), 1400 STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC), 1401 STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8), 1402 #endif /* !STM32MP21 */ 1403 STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1), 1404 #if !STM32MP21 1405 STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2), 1406 #endif /* !STM32MP21 */ 1407 STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC), 1408 STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1), 1409 STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2), 1410 STM32_GATE(_CK_USB2PHY1, CK_KER_USB2PHY1, _CK_FLEXGEN_57, 0, GATE_USB2PHY1), 1411 STM32_GATE(_CK_USB2PHY2, CK_KER_USB2PHY2, _CK_FLEXGEN_58, 0, GATE_USB2PHY2), 1412 }; 1413 1414 enum clksrc_id { 1415 CLKSRC_CA35SS, 1416 CLKSRC_PLL1, 1417 CLKSRC_PLL2, 1418 #if !STM32MP21 1419 CLKSRC_PLL3, 1420 #endif /* !STM32MP21 */ 1421 CLKSRC_PLL4, 1422 CLKSRC_PLL5, 1423 CLKSRC_PLL6, 1424 CLKSRC_PLL7, 1425 CLKSRC_PLL8, 1426 CLKSRC_XBAR_CHANNEL0, 1427 CLKSRC_XBAR_CHANNEL1, 1428 CLKSRC_XBAR_CHANNEL2, 1429 CLKSRC_XBAR_CHANNEL3, 1430 CLKSRC_XBAR_CHANNEL4, 1431 CLKSRC_XBAR_CHANNEL5, 1432 CLKSRC_XBAR_CHANNEL6, 1433 CLKSRC_XBAR_CHANNEL7, 1434 CLKSRC_XBAR_CHANNEL8, 1435 CLKSRC_XBAR_CHANNEL9, 1436 CLKSRC_XBAR_CHANNEL10, 1437 CLKSRC_XBAR_CHANNEL11, 1438 CLKSRC_XBAR_CHANNEL12, 1439 CLKSRC_XBAR_CHANNEL13, 1440 CLKSRC_XBAR_CHANNEL14, 1441 CLKSRC_XBAR_CHANNEL15, 1442 CLKSRC_XBAR_CHANNEL16, 1443 CLKSRC_XBAR_CHANNEL17, 1444 CLKSRC_XBAR_CHANNEL18, 1445 CLKSRC_XBAR_CHANNEL19, 1446 CLKSRC_XBAR_CHANNEL20, 1447 CLKSRC_XBAR_CHANNEL21, 1448 CLKSRC_XBAR_CHANNEL22, 1449 CLKSRC_XBAR_CHANNEL23, 1450 CLKSRC_XBAR_CHANNEL24, 1451 CLKSRC_XBAR_CHANNEL25, 1452 CLKSRC_XBAR_CHANNEL26, 1453 CLKSRC_XBAR_CHANNEL27, 1454 CLKSRC_XBAR_CHANNEL28, 1455 CLKSRC_XBAR_CHANNEL29, 1456 CLKSRC_XBAR_CHANNEL30, 1457 CLKSRC_XBAR_CHANNEL31, 1458 CLKSRC_XBAR_CHANNEL32, 1459 CLKSRC_XBAR_CHANNEL33, 1460 CLKSRC_XBAR_CHANNEL34, 1461 CLKSRC_XBAR_CHANNEL35, 1462 CLKSRC_XBAR_CHANNEL36, 1463 CLKSRC_XBAR_CHANNEL37, 1464 CLKSRC_XBAR_CHANNEL38, 1465 CLKSRC_XBAR_CHANNEL39, 1466 CLKSRC_XBAR_CHANNEL40, 1467 CLKSRC_XBAR_CHANNEL41, 1468 CLKSRC_XBAR_CHANNEL42, 1469 CLKSRC_XBAR_CHANNEL43, 1470 CLKSRC_XBAR_CHANNEL44, 1471 CLKSRC_XBAR_CHANNEL45, 1472 CLKSRC_XBAR_CHANNEL46, 1473 CLKSRC_XBAR_CHANNEL47, 1474 CLKSRC_XBAR_CHANNEL48, 1475 CLKSRC_XBAR_CHANNEL49, 1476 CLKSRC_XBAR_CHANNEL50, 1477 CLKSRC_XBAR_CHANNEL51, 1478 CLKSRC_XBAR_CHANNEL52, 1479 CLKSRC_XBAR_CHANNEL53, 1480 CLKSRC_XBAR_CHANNEL54, 1481 CLKSRC_XBAR_CHANNEL55, 1482 CLKSRC_XBAR_CHANNEL56, 1483 CLKSRC_XBAR_CHANNEL57, 1484 CLKSRC_XBAR_CHANNEL58, 1485 CLKSRC_XBAR_CHANNEL59, 1486 CLKSRC_XBAR_CHANNEL60, 1487 CLKSRC_XBAR_CHANNEL61, 1488 CLKSRC_XBAR_CHANNEL62, 1489 CLKSRC_XBAR_CHANNEL63, 1490 CLKSRC_RTC, 1491 CLKSRC_MCO1, 1492 CLKSRC_MCO2, 1493 CLKSRC_NB 1494 }; 1495 1496 static void stm32mp2_a35_ss_on_hsi(void) 1497 { 1498 uintptr_t a35_ss_address = A35SSC_BASE; 1499 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1500 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1501 uint32_t chgclkreq; 1502 uint64_t timeout; 1503 1504 chgclkreq = mmio_read_32(chgclkreq_reg); 1505 if ((chgclkreq & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) == A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1506 /* Nothing to do, clock source is already set on bypass clock */ 1507 return; 1508 } 1509 1510 /* for clkext2f frequency at 400MHZ, default flexgen63 config, divider by 2 is required */ 1511 if ((chgclkreq & A35_SS_CHGCLKREQ_ARM_DIVSEL) == A35_SS_CHGCLKREQ_ARM_DIVSEL) { 1512 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_DIVSEL); 1513 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1514 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_DIVSELACK) == 1515 A35_SS_CHGCLKREQ_ARM_DIVSELACK) { 1516 if (timeout_elapsed(timeout)) { 1517 EARLY_ERROR("Cannot set div on A35 bypass clock\n"); 1518 panic(); 1519 } 1520 } 1521 } 1522 1523 mmio_setbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1524 1525 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1526 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 1527 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1528 if (timeout_elapsed(timeout)) { 1529 EARLY_ERROR("Cannot switch A35 to bypass clock\n"); 1530 panic(); 1531 } 1532 } 1533 1534 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1535 } 1536 1537 #ifdef IMAGE_BL2 1538 static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv) 1539 { 1540 mmio_clrbits_32(priv->base + RCC_MUXSELCFGR, 1541 RCC_MUXSELCFGR_MUXSEL0_MASK | 1542 RCC_MUXSELCFGR_MUXSEL1_MASK | 1543 RCC_MUXSELCFGR_MUXSEL2_MASK | 1544 RCC_MUXSELCFGR_MUXSEL3_MASK | 1545 RCC_MUXSELCFGR_MUXSEL4_MASK | 1546 RCC_MUXSELCFGR_MUXSEL5_MASK | 1547 RCC_MUXSELCFGR_MUXSEL6_MASK | 1548 RCC_MUXSELCFGR_MUXSEL7_MASK); 1549 } 1550 1551 static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv) 1552 { 1553 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; 1554 uint32_t i; 1555 1556 for (i = 0; i < XBAR_CHANNEL_NB; i++) { 1557 mmio_clrsetbits_32(xbar0cfgr + (0x4 * i), 1558 RCC_XBAR0CFGR_XBAR0SEL_MASK, 1559 XBAR_SRC_HSI); 1560 } 1561 } 1562 1563 static int stm32mp2_a35_pll1_start(void) 1564 { 1565 uintptr_t a35_ss_address = A35SSC_BASE; 1566 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1567 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1568 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1569 1570 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 1571 1572 /* Wait PLL lock */ 1573 while ((mmio_read_32(pll_enable_reg) & A35_SS_PLL_ENABLE_LOCKP) == 0U) { 1574 if (timeout_elapsed(timeout)) { 1575 EARLY_ERROR("PLL1 start failed @ 0x%lx: 0x%x\n", 1576 pll_enable_reg, mmio_read_32(pll_enable_reg)); 1577 return -ETIMEDOUT; 1578 } 1579 } 1580 1581 /* De-assert reset on PLL output clock path */ 1582 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1583 1584 /* Switch CPU clock to PLL clock */ 1585 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1586 1587 /* Wait for clock change acknowledge */ 1588 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1589 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 0U) { 1590 if (timeout_elapsed(timeout)) { 1591 EARLY_ERROR("CA35SS switch to PLL1 failed @ 0x%lx: 0x%x\n", 1592 chgclkreq_reg, mmio_read_32(chgclkreq_reg)); 1593 return -ETIMEDOUT; 1594 } 1595 } 1596 1597 return 0; 1598 } 1599 1600 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1, 1601 uint32_t postdiv2) 1602 { 1603 uintptr_t a35_ss_address = A35SSC_BASE; 1604 uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1; 1605 uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2; 1606 1607 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_REFDIV_MASK, 1608 (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) & 1609 A35_SS_PLL_FREQ1_REFDIV_MASK); 1610 1611 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_FBDIV_MASK, 1612 (fbdiv << A35_SS_PLL_FREQ1_FBDIV_SHIFT) & 1613 A35_SS_PLL_FREQ1_FBDIV_MASK); 1614 1615 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV1_MASK, 1616 (postdiv1 << A35_SS_PLL_FREQ2_POSTDIV1_SHIFT) & 1617 A35_SS_PLL_FREQ2_POSTDIV1_MASK); 1618 1619 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV2_MASK, 1620 (postdiv2 << A35_SS_PLL_FREQ2_POSTDIV2_SHIFT) & 1621 A35_SS_PLL_FREQ2_POSTDIV2_MASK); 1622 } 1623 1624 static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv, 1625 const struct stm32_clk_pll *pll, 1626 uint32_t *pllcfg, 1627 uint32_t fracv) 1628 { 1629 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1630 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 1631 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1632 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1633 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 1634 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 1635 unsigned long refclk; 1636 1637 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1638 1639 if (fracv == 0U) { 1640 /* PLL in integer mode */ 1641 1642 /* 1643 * No need to check max clock, as oscillator reference clocks 1644 * will always be less than 1.2GHz 1645 */ 1646 if (refclk < PLL_REFCLK_MIN) { 1647 panic(); 1648 } 1649 1650 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK); 1651 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1652 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1653 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1654 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1655 } else { 1656 /* PLL in frac mode */ 1657 1658 /* 1659 * No need to check max clock, as oscillator reference clocks 1660 * will always be less than 1.2GHz 1661 */ 1662 if (refclk < PLL_FRAC_REFCLK_MIN) { 1663 panic(); 1664 } 1665 1666 mmio_clrsetbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, 1667 fracv & RCC_PLLxCFGR3_FRACIN_MASK); 1668 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1669 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1670 } 1671 1672 assert(pllcfg[REFDIV] != 0U); 1673 1674 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, 1675 (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) & 1676 RCC_PLLxCFGR2_FBDIV_MASK); 1677 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, 1678 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); 1679 mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, 1680 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); 1681 mmio_clrsetbits_32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, 1682 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); 1683 1684 if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) { 1685 /* Bypass mode */ 1686 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1687 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1688 } else { 1689 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1690 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1691 } 1692 1693 return 0; 1694 } 1695 1696 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, 1697 const struct stm32_clk_pll *pll, 1698 uint32_t *csg) 1699 { 1700 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1701 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1702 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1703 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5; 1704 1705 1706 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, 1707 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); 1708 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, 1709 (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) & 1710 RCC_PLLxCFGR5_SPREAD_MASK); 1711 1712 if (csg[DOWNSPREAD] != 0) { 1713 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1714 } else { 1715 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1716 } 1717 1718 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1719 1720 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 1721 udelay(1); 1722 1723 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1724 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1725 } 1726 1727 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data); 1728 1729 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) 1730 { 1731 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1732 struct stm32_clk_platdata *pdata = priv->pdata; 1733 1734 return &pdata->pll[pll_idx]; 1735 } 1736 1737 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx, 1738 struct stm32_pll_dt_cfg *pll_conf) 1739 { 1740 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1741 unsigned long refclk; 1742 int ret = 0; 1743 1744 stm32mp2_a35_ss_on_hsi(); 1745 1746 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1747 if (ret != 0) { 1748 panic(); 1749 } 1750 1751 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1752 1753 /* 1754 * No need to check max clock, as oscillator reference clocks will 1755 * always be less than 1.2 GHz 1756 */ 1757 if (refclk < PLL_REFCLK_MIN) { 1758 EARLY_ERROR("%s: %d\n", __func__, __LINE__); 1759 panic(); 1760 } 1761 1762 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV], 1763 pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]); 1764 1765 ret = stm32mp2_a35_pll1_start(); 1766 if (ret != 0) { 1767 panic(); 1768 } 1769 1770 return 0; 1771 } 1772 1773 static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv, 1774 const struct stm32_clk_pll *pll) 1775 { 1776 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1777 uint64_t timeout = timeout_init_us(CLKSRC_TIMEOUT); 1778 1779 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) != 1780 RCC_PLLxCFGR1_CKREFST) { 1781 if (timeout_elapsed(timeout)) { 1782 EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1); 1783 return -ETIMEDOUT; 1784 } 1785 } 1786 1787 return 0; 1788 } 1789 1790 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, 1791 struct stm32_pll_dt_cfg *pll_conf) 1792 { 1793 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1794 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1795 bool spread_spectrum = false; 1796 int ret = 0; 1797 1798 _clk_stm32_pll_disable(priv, pll); 1799 1800 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1801 if (ret != 0) { 1802 panic(); 1803 } 1804 1805 ret = clk_stm32_pll_wait_mux_ready(priv, pll); 1806 if (ret != 0) { 1807 panic(); 1808 } 1809 1810 ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac); 1811 if (ret != 0) { 1812 panic(); 1813 } 1814 1815 if (pll_conf->csg_enabled) { 1816 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); 1817 spread_spectrum = true; 1818 } 1819 1820 _clk_stm32_pll_enable(priv, pll); 1821 1822 if (spread_spectrum) { 1823 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1824 } 1825 1826 return 0; 1827 } 1828 1829 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) 1830 { 1831 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); 1832 1833 if (pll_conf->enabled) { 1834 if (pll_idx == _PLL1) { 1835 return _clk_stm32_pll1_init(priv, pll_idx, pll_conf); 1836 } else { 1837 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); 1838 } 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv) 1845 { 1846 enum pll_id i; 1847 int err; 1848 1849 for (i = _PLL1; i < _PLL_NB; i++) { 1850 #if STM32MP21 1851 if (i == _PLL3) { 1852 continue; 1853 } 1854 #endif 1855 err = clk_stm32_pll_init(priv, i); 1856 if (err) { 1857 return err; 1858 } 1859 } 1860 1861 return 0; 1862 } 1863 1864 static int wait_predivsr(uint16_t channel) 1865 { 1866 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1867 uintptr_t rcc_base = priv->base; 1868 uintptr_t previvsr; 1869 uint32_t channel_bit; 1870 uint64_t timeout; 1871 1872 if (channel < __WORD_BIT) { 1873 previvsr = rcc_base + RCC_PREDIVSR1; 1874 channel_bit = BIT(channel); 1875 } else { 1876 previvsr = rcc_base + RCC_PREDIVSR2; 1877 channel_bit = BIT(channel - __WORD_BIT); 1878 } 1879 1880 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1881 while ((mmio_read_32(previvsr) & channel_bit) != 0U) { 1882 if (timeout_elapsed(timeout)) { 1883 EARLY_ERROR("Pre divider status: %x\n", 1884 mmio_read_32(previvsr)); 1885 return -ETIMEDOUT; 1886 } 1887 } 1888 1889 return 0; 1890 } 1891 1892 static int wait_findivsr(uint16_t channel) 1893 { 1894 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1895 uintptr_t rcc_base = priv->base; 1896 uintptr_t finvivsr; 1897 uint32_t channel_bit; 1898 uint64_t timeout; 1899 1900 if (channel < __WORD_BIT) { 1901 finvivsr = rcc_base + RCC_FINDIVSR1; 1902 channel_bit = BIT(channel); 1903 } else { 1904 finvivsr = rcc_base + RCC_FINDIVSR2; 1905 channel_bit = BIT(channel - __WORD_BIT); 1906 } 1907 1908 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1909 while ((mmio_read_32(finvivsr) & channel_bit) != 0U) { 1910 if (timeout_elapsed(timeout)) { 1911 EARLY_ERROR("Final divider status: %x\n", 1912 mmio_read_32(finvivsr)); 1913 return -ETIMEDOUT; 1914 } 1915 } 1916 1917 return 0; 1918 } 1919 1920 static int wait_xbar_sts(uint16_t channel) 1921 { 1922 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1923 uintptr_t rcc_base = priv->base; 1924 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4U * channel); 1925 uint64_t timeout; 1926 1927 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1928 while ((mmio_read_32(xbar_cfgr) & RCC_XBAR0CFGR_XBAR0STS) != 0U) { 1929 if (timeout_elapsed(timeout)) { 1930 EARLY_ERROR("XBAR%uCFGR: %x\n", channel, 1931 mmio_read_32(xbar_cfgr)); 1932 return -ETIMEDOUT; 1933 } 1934 } 1935 1936 return 0; 1937 } 1938 1939 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, 1940 unsigned int prediv, unsigned int findiv) 1941 { 1942 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1943 uintptr_t rcc_base = priv->base; 1944 1945 if (wait_predivsr(channel) != 0) { 1946 panic(); 1947 } 1948 1949 mmio_clrsetbits_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel), 1950 RCC_PREDIV0CFGR_PREDIV0_MASK, 1951 prediv); 1952 1953 if (wait_predivsr(channel) != 0) { 1954 panic(); 1955 } 1956 1957 if (wait_findivsr(channel) != 0) { 1958 panic(); 1959 } 1960 1961 mmio_clrsetbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1962 RCC_FINDIV0CFGR_FINDIV0_MASK, 1963 findiv); 1964 1965 if (wait_findivsr(channel) != 0) { 1966 panic(); 1967 } 1968 1969 if (wait_xbar_sts(channel) != 0) { 1970 panic(); 1971 } 1972 1973 mmio_clrsetbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1974 RCC_XBARxCFGR_XBARxSEL_MASK, 1975 clk_src); 1976 mmio_setbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1977 RCC_XBARxCFGR_XBARxEN); 1978 1979 if (wait_xbar_sts(channel) != 0) { 1980 panic(); 1981 } 1982 } 1983 1984 static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv) 1985 { 1986 struct stm32_clk_platdata *pdata = priv->pdata; 1987 uint32_t i; 1988 1989 for (i = 0U; i < pdata->nflexgen; i++) { 1990 uint32_t val = pdata->flexgen[i]; 1991 uint32_t cmd, cmd_data; 1992 unsigned int channel, clk_src, pdiv, fdiv; 1993 1994 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1995 cmd_data = val & ~CMD_MASK; 1996 1997 if (cmd != CMD_FLEXGEN) { 1998 continue; 1999 } 2000 2001 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 2002 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 2003 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 2004 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 2005 2006 switch (channel) { 2007 case 33U: /* STGEN */ 2008 break; 2009 2010 default: 2011 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 2012 break; 2013 } 2014 } 2015 2016 return 0; 2017 } 2018 2019 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) 2020 { 2021 struct stm32_clk_platdata *pdata = priv->pdata; 2022 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 2023 bool digbyp = osci->digbyp; 2024 bool bypass = osci->bypass; 2025 bool css = osci->css; 2026 2027 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { 2028 return; 2029 } 2030 2031 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); 2032 2033 _clk_stm32_enable(priv, _CK_HSE); 2034 2035 clk_oscillator_set_css(priv, _CK_HSE, css); 2036 } 2037 2038 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) 2039 { 2040 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); 2041 struct stm32_clk_platdata *pdata = priv->pdata; 2042 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 2043 bool digbyp = osci->digbyp; 2044 bool bypass = osci->bypass; 2045 uint8_t drive = osci->drive; 2046 2047 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { 2048 return; 2049 } 2050 2051 /* Do not reconfigure LSE if already enabled */ 2052 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) { 2053 return; 2054 } 2055 2056 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); 2057 2058 clk_oscillator_set_drive(priv, _CK_LSE, drive); 2059 2060 _clk_stm32_gate_enable(priv, osc_data->gate_id); 2061 } 2062 2063 static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv) 2064 { 2065 stm32mp2_a35_ss_on_hsi(); 2066 stm32mp2_clk_muxsel_on_hsi(priv); 2067 stm32mp2_clk_xbar_on_hsi(priv); 2068 2069 return 0; 2070 } 2071 2072 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) 2073 { 2074 int ret = 0; 2075 2076 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { 2077 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); 2078 } 2079 2080 return ret; 2081 } 2082 2083 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv) 2084 { 2085 #if !STM32MP21 2086 struct stm32_clk_platdata *pdata = priv->pdata; 2087 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI]; 2088 int err; 2089 2090 err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0); 2091 if (err != 0) { 2092 EARLY_ERROR("Invalid rate %lu MHz for MSI ! (4 or 16 only)\n", 2093 osci->freq / 1000000U); 2094 panic(); 2095 } 2096 #endif /* !STM32MP21 */ 2097 2098 _clk_stm32_enable(priv, _CK_MSI); 2099 } 2100 2101 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) 2102 { 2103 stm32_enable_oscillator_hse(priv); 2104 stm32_enable_oscillator_lse(priv); 2105 stm32_enable_oscillator_msi(priv); 2106 _clk_stm32_enable(priv, _CK_LSI); 2107 } 2108 2109 static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data) 2110 { 2111 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 2112 int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 2113 2114 return clk_stm32_set_div(priv, div_id, div_n); 2115 } 2116 2117 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) 2118 { 2119 int mux_id = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 2120 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 2121 2122 return clk_mux_set_parent(priv, mux_id, sel); 2123 } 2124 2125 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) 2126 { 2127 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 2128 2129 return clk_get_index(priv, binding_id); 2130 } 2131 2132 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 2133 { 2134 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 2135 bool enable = ((data & CLK_ON_MASK) >> CLK_ON_SHIFT) != 0U; 2136 int clk_id = 0; 2137 int ret = 0; 2138 2139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); 2140 if (clk_id < 0) { 2141 return clk_id; 2142 } 2143 2144 if (sel != CLK_NOMUX) { 2145 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); 2146 if (ret != 0) { 2147 return ret; 2148 } 2149 } 2150 2151 if (enable) { 2152 clk_stm32_enable_call_ops(priv, clk_id); 2153 } else { 2154 clk_stm32_disable_call_ops(priv, clk_id); 2155 } 2156 2157 return 0; 2158 } 2159 2160 static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val) 2161 { 2162 uint32_t cmd = (val & CMD_MASK) >> CMD_SHIFT; 2163 uint32_t cmd_data = val & ~CMD_MASK; 2164 int ret = -1; 2165 2166 switch (cmd) { 2167 case CMD_DIV: 2168 ret = stm32_clk_configure_div(priv, cmd_data); 2169 break; 2170 2171 case CMD_MUX: 2172 ret = stm32_clk_configure_mux(priv, cmd_data); 2173 break; 2174 2175 case CMD_CLK: 2176 ret = stm32_clk_configure_clk(priv, cmd_data); 2177 break; 2178 2179 default: 2180 EARLY_ERROR("%s: cmd unknown ! : 0x%x\n", __func__, val); 2181 break; 2182 } 2183 2184 return ret; 2185 } 2186 2187 static int stm32_clk_bus_configure(struct stm32_clk_priv *priv) 2188 { 2189 struct stm32_clk_platdata *pdata = priv->pdata; 2190 uint32_t i; 2191 2192 for (i = 0; i < pdata->nbusclk; i++) { 2193 int ret; 2194 2195 ret = stm32_clk_configure(priv, pdata->busclk[i]); 2196 if (ret != 0) { 2197 return ret; 2198 } 2199 } 2200 2201 return 0; 2202 } 2203 2204 static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv) 2205 { 2206 struct stm32_clk_platdata *pdata = priv->pdata; 2207 uint32_t i; 2208 2209 for (i = 0U; i < pdata->nkernelclk; i++) { 2210 int ret; 2211 2212 ret = stm32_clk_configure(priv, pdata->kernelclk[i]); 2213 if (ret != 0) { 2214 return ret; 2215 } 2216 } 2217 2218 return 0; 2219 } 2220 2221 static int stm32mp2_init_clock_tree(void) 2222 { 2223 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 2224 int ret; 2225 2226 /* Set timer with STGEN without changing its clock source */ 2227 stm32mp_stgen_restore_rate(); 2228 generic_delay_timer_init(); 2229 2230 stm32_clk_oscillators_enable(priv); 2231 2232 /* Come back to HSI */ 2233 ret = stm32mp2_clk_switch_to_hsi(priv); 2234 if (ret != 0) { 2235 panic(); 2236 } 2237 2238 ret = stm32mp2_clk_pll_configure(priv); 2239 if (ret != 0) { 2240 panic(); 2241 } 2242 2243 /* Wait LSE ready before to use it */ 2244 ret = stm32_clk_oscillators_wait_lse_ready(priv); 2245 if (ret != 0) { 2246 panic(); 2247 } 2248 2249 ret = stm32mp2_clk_flexgen_configure(priv); 2250 if (ret != 0) { 2251 panic(); 2252 } 2253 2254 ret = stm32_clk_bus_configure(priv); 2255 if (ret != 0) { 2256 panic(); 2257 } 2258 2259 ret = stm32_clk_kernel_configure(priv); 2260 if (ret != 0) { 2261 panic(); 2262 } 2263 2264 return 0; 2265 } 2266 2267 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, 2268 struct stm32_osci_dt_cfg *osci) 2269 { 2270 int subnode = 0; 2271 2272 /* Default value oscillator not found, freq=0 */ 2273 osci->freq = 0; 2274 2275 fdt_for_each_subnode(subnode, fdt, node) { 2276 const char *cchar = NULL; 2277 const fdt32_t *cuint = NULL; 2278 int ret = 0; 2279 2280 cchar = fdt_get_name(fdt, subnode, &ret); 2281 if (cchar == NULL) { 2282 return ret; 2283 } 2284 2285 if (strncmp(cchar, name, (size_t)ret) || 2286 fdt_get_status(subnode) == DT_DISABLED) { 2287 continue; 2288 } 2289 2290 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 2291 if (cuint == NULL) { 2292 return ret; 2293 } 2294 2295 osci->freq = fdt32_to_cpu(*cuint); 2296 2297 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { 2298 osci->bypass = true; 2299 } 2300 2301 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { 2302 osci->digbyp = true; 2303 } 2304 2305 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { 2306 osci->css = true; 2307 } 2308 2309 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); 2310 2311 return 0; 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) 2318 { 2319 int fdt_err = 0; 2320 uint32_t i = 0; 2321 int node = 0; 2322 2323 node = fdt_path_offset(fdt, "/clocks"); 2324 if (node < 0) { 2325 return -FDT_ERR_NOTFOUND; 2326 } 2327 2328 for (i = 0; i < pdata->nosci; i++) { 2329 const char *name = NULL; 2330 2331 name = clk_stm32_get_oscillator_name((enum stm32_osc)i); 2332 if (name == NULL) { 2333 continue; 2334 } 2335 2336 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); 2337 if (fdt_err < 0) { 2338 panic(); 2339 } 2340 } 2341 2342 return 0; 2343 } 2344 2345 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2346 { 2347 const fdt32_t *cuint = NULL; 2348 int subnode_pll = 0; 2349 uint32_t val = 0; 2350 int err = 0; 2351 2352 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2353 if (!cuint) { 2354 return -FDT_ERR_NOTFOUND; 2355 } 2356 2357 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2358 if (subnode_pll < 0) { 2359 return -FDT_ERR_NOTFOUND; 2360 } 2361 2362 err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg); 2363 if (err != 0) { 2364 return err; 2365 } 2366 2367 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg); 2368 2369 pll->csg_enabled = (err == 0); 2370 2371 if (err == -FDT_ERR_NOTFOUND) { 2372 err = 0; 2373 } 2374 2375 if (err != 0) { 2376 return err; 2377 } 2378 2379 pll->enabled = true; 2380 2381 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); 2382 2383 pll->src = UINT32_MAX; 2384 2385 err = fdt_read_uint32(fdt, subnode_pll, "src", &val); 2386 if (err == 0) { 2387 pll->src = val; 2388 } 2389 2390 return 0; 2391 } 2392 2393 #define RCC_PLL_NAME_SIZE 12 2394 2395 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2396 { 2397 unsigned int i = 0; 2398 2399 for (i = _PLL1; i < pdata->npll; i++) { 2400 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 2401 char name[RCC_PLL_NAME_SIZE]; 2402 int subnode = 0; 2403 int err = 0; 2404 2405 #if STM32MP21 2406 if (i == _PLL3) { 2407 continue; 2408 } 2409 #endif 2410 snprintf(name, sizeof(name), "st,pll-%u", i + 1); 2411 2412 subnode = fdt_subnode_offset(fdt, node, name); 2413 if (!fdt_check_node(subnode)) { 2414 continue; 2415 } 2416 2417 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2418 if (err != 0) { 2419 panic(); 2420 } 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2427 { 2428 void *fdt = NULL; 2429 int node; 2430 int err; 2431 2432 if (fdt_get_address(&fdt) == 0) { 2433 return -ENOENT; 2434 } 2435 2436 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2437 if (node < 0) { 2438 panic(); 2439 } 2440 2441 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); 2442 if (err != 0) { 2443 return err; 2444 } 2445 2446 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2447 if (err != 0) { 2448 return err; 2449 } 2450 2451 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,busclk", pdata->busclk, &pdata->nbusclk); 2452 if (err != 0) { 2453 return err; 2454 } 2455 2456 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,flexgen", pdata->flexgen, 2457 &pdata->nflexgen); 2458 if (err != 0) { 2459 return err; 2460 } 2461 2462 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,kerclk", pdata->kernelclk, 2463 &pdata->nkernelclk); 2464 if (err != 0) { 2465 return err; 2466 } 2467 2468 return 0; 2469 } 2470 #endif /* IMAGE_BL2 */ 2471 2472 static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR]; 2473 2474 static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB]; 2475 2476 #define DT_FLEXGEN_CLK_MAX 64 2477 static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX]; 2478 2479 #if STM32MP21 2480 #define DT_BUS_CLK_MAX 7 2481 #else /* STM32MP21 */ 2482 #define DT_BUS_CLK_MAX 6 2483 #endif /* STM32MP21 */ 2484 static uint32_t mp2_busclk[DT_BUS_CLK_MAX]; 2485 2486 #define DT_KERNEL_CLK_MAX 20 2487 static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX]; 2488 2489 static struct stm32_clk_platdata stm32mp2_pdata = { 2490 .osci = mp2_osci, 2491 .nosci = NB_OSCILLATOR, 2492 .pll = mp2_pll, 2493 .npll = _PLL_NB, 2494 .flexgen = mp2_flexgen, 2495 .nflexgen = DT_FLEXGEN_CLK_MAX, 2496 .busclk = mp2_busclk, 2497 .nbusclk = DT_BUS_CLK_MAX, 2498 .kernelclk = mp2_kernelclk, 2499 .nkernelclk = DT_KERNEL_CLK_MAX, 2500 }; 2501 2502 static uint8_t refcounts_mp2[CK_LAST]; 2503 2504 static struct stm32_clk_priv stm32mp2_clock_data = { 2505 .base = RCC_BASE, 2506 .num = ARRAY_SIZE(stm32mp2_clk), 2507 .clks = stm32mp2_clk, 2508 .parents = parent_mp2, 2509 .nb_parents = ARRAY_SIZE(parent_mp2), 2510 .gates = gates_mp2, 2511 .nb_gates = ARRAY_SIZE(gates_mp2), 2512 .div = dividers_mp2, 2513 .nb_div = ARRAY_SIZE(dividers_mp2), 2514 .osci_data = stm32mp2_osc_data, 2515 .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data), 2516 .gate_refcounts = refcounts_mp2, 2517 .pdata = &stm32mp2_pdata, 2518 .ops_array = ops_array_mp2, 2519 }; 2520 2521 int stm32mp2_clk_init(void) 2522 { 2523 uintptr_t base = RCC_BASE; 2524 int ret; 2525 2526 #ifdef IMAGE_BL2 2527 ret = stm32_clk_parse_fdt(&stm32mp2_pdata); 2528 if (ret != 0) { 2529 return ret; 2530 } 2531 #endif 2532 2533 ret = clk_stm32_init(&stm32mp2_clock_data, base); 2534 if (ret != 0) { 2535 return ret; 2536 } 2537 2538 #ifdef IMAGE_BL2 2539 ret = stm32mp2_init_clock_tree(); 2540 if (ret != 0) { 2541 return ret; 2542 } 2543 2544 clk_stm32_enable_critical_clocks(); 2545 #endif 2546 2547 return 0; 2548 } 2549 2550 int stm32mp2_pll1_disable(void) 2551 { 2552 #ifdef IMAGE_BL2 2553 return -EPERM; 2554 #else 2555 uintptr_t a35_ss_address = A35SSC_BASE; 2556 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 2557 2558 stm32mp2_a35_ss_on_hsi(); 2559 2560 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 2561 2562 return 0; 2563 #endif 2564 } 2565