1 /* 2 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include "clk-stm32-core.h" 13 #include <common/fdt_wrappers.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/st/stm32mp2_clk.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <lib/mmio.h> 20 #include <lib/spinlock.h> 21 #include <lib/utils_def.h> 22 #include <libfdt.h> 23 24 #include <platform_def.h> 25 26 struct stm32_osci_dt_cfg { 27 unsigned long freq; 28 uint32_t drive; 29 bool bypass; 30 bool digbyp; 31 bool css; 32 }; 33 34 struct stm32_pll_dt_cfg { 35 uint32_t src; 36 uint32_t frac; 37 uint32_t cfg[PLLCFG_NB]; 38 uint32_t csg[PLLCSG_NB]; 39 bool csg_enabled; 40 bool enabled; 41 }; 42 43 struct stm32_clk_platdata { 44 uintptr_t rcc_base; 45 uint32_t nosci; 46 struct stm32_osci_dt_cfg *osci; 47 uint32_t npll; 48 struct stm32_pll_dt_cfg *pll; 49 uint32_t nflexgen; 50 uint32_t *flexgen; 51 uint32_t nbusclk; 52 uint32_t *busclk; 53 uint32_t nkernelclk; 54 uint32_t *kernelclk; 55 }; 56 57 /* A35 Sub-System which manages its own PLL (PLL1) */ 58 #define A35_SS_CHGCLKREQ 0x0000 59 #define A35_SS_PLL_FREQ1 0x0080 60 #define A35_SS_PLL_FREQ2 0x0090 61 #define A35_SS_PLL_ENABLE 0x00a0 62 63 #define A35_SS_CHGCLKREQ_ARM_CHGCLKREQ BIT(0) 64 #define A35_SS_CHGCLKREQ_ARM_CHGCLKACK BIT(1) 65 66 #define A35_SS_PLL_FREQ1_FBDIV_MASK GENMASK(11, 0) 67 #define A35_SS_PLL_FREQ1_FBDIV_SHIFT 0 68 #define A35_SS_PLL_FREQ1_REFDIV_MASK GENMASK(21, 16) 69 #define A35_SS_PLL_FREQ1_REFDIV_SHIFT 16 70 71 #define A35_SS_PLL_FREQ2_POSTDIV1_MASK GENMASK(2, 0) 72 #define A35_SS_PLL_FREQ2_POSTDIV1_SHIFT 0 73 #define A35_SS_PLL_FREQ2_POSTDIV2_MASK GENMASK(5, 3) 74 #define A35_SS_PLL_FREQ2_POSTDIV2_SHIFT 3 75 76 #define A35_SS_PLL_ENABLE_PD BIT(0) 77 #define A35_SS_PLL_ENABLE_LOCKP BIT(1) 78 #define A35_SS_PLL_ENABLE_NRESET_SWPLL_FF BIT(2) 79 80 #define TIMEOUT_US_200MS U(200000) 81 #define TIMEOUT_US_1S U(1000000) 82 83 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 84 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 85 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 86 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 87 88 /* PLL minimal frequencies for clock sources */ 89 #define PLL_REFCLK_MIN UL(5000000) 90 #define PLL_FRAC_REFCLK_MIN UL(10000000) 91 92 #define XBAR_CHANNEL_NB 64 93 94 /* Warning, should be start to 1 */ 95 enum clock { 96 _CK_0_MHZ, 97 98 /* ROOT CLOCKS */ 99 _CK_HSI, 100 _CK_HSE, 101 _CK_MSI, 102 _CK_LSI, 103 _CK_LSE, 104 _I2SCKIN, 105 _SPDIFSYMB, 106 _CK_PLL1, 107 _CK_PLL2, 108 _CK_PLL3, 109 _CK_PLL4, 110 _CK_PLL5, 111 _CK_PLL6, 112 _CK_PLL7, 113 _CK_PLL8, 114 _CK_HSE_RTC, 115 _CK_RTCCK, 116 _CK_ICN_HS_MCU, 117 _CK_ICN_SDMMC, 118 _CK_ICN_DDR, 119 _CK_ICN_HSL, 120 _CK_ICN_NIC, 121 _CK_ICN_LS_MCU, 122 _CK_FLEXGEN_07, 123 _CK_FLEXGEN_08, 124 _CK_FLEXGEN_09, 125 _CK_FLEXGEN_10, 126 _CK_FLEXGEN_11, 127 _CK_FLEXGEN_12, 128 _CK_FLEXGEN_13, 129 _CK_FLEXGEN_14, 130 _CK_FLEXGEN_15, 131 _CK_FLEXGEN_16, 132 _CK_FLEXGEN_17, 133 _CK_FLEXGEN_18, 134 _CK_FLEXGEN_19, 135 _CK_FLEXGEN_20, 136 _CK_FLEXGEN_21, 137 _CK_FLEXGEN_22, 138 _CK_FLEXGEN_23, 139 _CK_FLEXGEN_24, 140 _CK_FLEXGEN_25, 141 _CK_FLEXGEN_26, 142 _CK_FLEXGEN_27, 143 _CK_FLEXGEN_28, 144 _CK_FLEXGEN_29, 145 _CK_FLEXGEN_30, 146 _CK_FLEXGEN_31, 147 _CK_FLEXGEN_32, 148 _CK_FLEXGEN_33, 149 _CK_FLEXGEN_34, 150 _CK_FLEXGEN_35, 151 _CK_FLEXGEN_36, 152 _CK_FLEXGEN_37, 153 _CK_FLEXGEN_38, 154 _CK_FLEXGEN_39, 155 _CK_FLEXGEN_40, 156 _CK_FLEXGEN_41, 157 _CK_FLEXGEN_42, 158 _CK_FLEXGEN_43, 159 _CK_FLEXGEN_44, 160 _CK_FLEXGEN_45, 161 _CK_FLEXGEN_46, 162 _CK_FLEXGEN_47, 163 _CK_FLEXGEN_48, 164 _CK_FLEXGEN_49, 165 _CK_FLEXGEN_50, 166 _CK_FLEXGEN_51, 167 _CK_FLEXGEN_52, 168 _CK_FLEXGEN_53, 169 _CK_FLEXGEN_54, 170 _CK_FLEXGEN_55, 171 _CK_FLEXGEN_56, 172 _CK_FLEXGEN_57, 173 _CK_FLEXGEN_58, 174 _CK_FLEXGEN_59, 175 _CK_FLEXGEN_60, 176 _CK_FLEXGEN_61, 177 _CK_FLEXGEN_62, 178 _CK_FLEXGEN_63, 179 _CK_ICN_APB1, 180 _CK_ICN_APB2, 181 _CK_ICN_APB3, 182 _CK_ICN_APB4, 183 _CK_ICN_APBDBG, 184 _CK_BKPSRAM, 185 _CK_BSEC, 186 _CK_CRC, 187 _CK_CRYP1, 188 _CK_CRYP2, 189 _CK_DDR, 190 _CK_DDRCAPB, 191 _CK_DDRCP, 192 _CK_DDRPHYC, 193 _CK_FMC, 194 _CK_GPIOA, 195 _CK_GPIOB, 196 _CK_GPIOC, 197 _CK_GPIOD, 198 _CK_GPIOE, 199 _CK_GPIOF, 200 _CK_GPIOG, 201 _CK_GPIOH, 202 _CK_GPIOI, 203 _CK_GPIOJ, 204 _CK_GPIOK, 205 _CK_GPIOZ, 206 _CK_HASH, 207 _CK_I2C1, 208 _CK_I2C2, 209 _CK_I2C3, 210 _CK_I2C4, 211 _CK_I2C5, 212 _CK_I2C6, 213 _CK_I2C7, 214 _CK_I2C8, 215 _CK_IWDG1, 216 _CK_IWDG2, 217 _CK_OSPI1, 218 _CK_OSPI2, 219 _CK_OSPIIOM, 220 _CK_PKA, 221 _CK_RETRAM, 222 _CK_RNG, 223 _CK_RTC, 224 _CK_SAES, 225 _CK_SDMMC1, 226 _CK_SDMMC2, 227 _CK_SRAM1, 228 _CK_SRAM2, 229 _CK_STGEN, 230 _CK_SYSCPU1, 231 _CK_SYSRAM, 232 _CK_UART4, 233 _CK_UART5, 234 _CK_UART7, 235 _CK_UART8, 236 _CK_UART9, 237 _CK_USART1, 238 _CK_USART2, 239 _CK_USART3, 240 _CK_USART6, 241 _CK_USB2EHCI, 242 _CK_USB2OHCI, 243 _CK_USB2PHY1, 244 _CK_USB2PHY2, 245 _CK_USB3DR, 246 _CK_USB3PCIEPHY, 247 _CK_USBTC, 248 249 CK_LAST 250 }; 251 252 static const uint16_t muxsel_src[] = { 253 _CK_HSI, _CK_HSE, _CK_MSI, _CK_0_MHZ 254 }; 255 256 static const uint16_t xbarsel_src[] = { 257 _CK_PLL4, _CK_PLL5, _CK_PLL6, _CK_PLL7, _CK_PLL8, 258 _CK_HSI, _CK_HSE, _CK_MSI, _CK_HSI, _CK_HSE, _CK_MSI, 259 _SPDIFSYMB, _I2SCKIN, _CK_LSI, _CK_LSE 260 }; 261 262 static const uint16_t rtc_src[] = { 263 _CK_0_MHZ, _CK_LSE, _CK_LSI, _CK_HSE_RTC 264 }; 265 266 static const uint16_t usb2phy1_src[] = { 267 _CK_FLEXGEN_57, _CK_HSE 268 }; 269 270 static const uint16_t usb2phy2_src[] = { 271 _CK_FLEXGEN_58, _CK_HSE 272 }; 273 274 static const uint16_t usb3pciphy_src[] = { 275 _CK_FLEXGEN_34, _CK_HSE 276 }; 277 278 static const uint16_t d3per_src[] = { 279 _CK_MSI, _CK_LSI, _CK_LSE 280 }; 281 282 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\ 283 .id_parents = src,\ 284 .num_parents = ARRAY_SIZE(src),\ 285 .mux = &(struct mux_cfg) {\ 286 .offset = (_offset),\ 287 .shift = (_shift),\ 288 .width = (_witdh),\ 289 .bitrdy = UINT8_MAX,\ 290 },\ 291 } 292 293 static const struct parent_cfg parent_mp25[] = { 294 MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2), 295 MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2), 296 MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2), 297 MUX_CONF(MUX_MUXSEL3, muxsel_src, RCC_MUXSELCFGR, 12, 2), 298 MUX_CONF(MUX_MUXSEL4, muxsel_src, RCC_MUXSELCFGR, 16, 2), 299 MUX_CONF(MUX_MUXSEL5, muxsel_src, RCC_MUXSELCFGR, 20, 2), 300 MUX_CONF(MUX_MUXSEL6, muxsel_src, RCC_MUXSELCFGR, 24, 2), 301 MUX_CONF(MUX_MUXSEL7, muxsel_src, RCC_MUXSELCFGR, 28, 2), 302 MUX_CONF(MUX_XBARSEL, xbarsel_src, RCC_XBAR0CFGR, 0, 4), 303 MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2), 304 MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1), 305 MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1), 306 MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1), 307 MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2), 308 }; 309 310 /* GATES */ 311 enum enum_gate_cfg { 312 GATE_ZERO, /* reserved for no gate */ 313 GATE_LSE, 314 GATE_RTCCK, 315 GATE_LSI, 316 GATE_HSI, 317 GATE_MSI, 318 GATE_HSE, 319 GATE_LSI_RDY, 320 GATE_MSI_RDY, 321 GATE_LSE_RDY, 322 GATE_HSE_RDY, 323 GATE_HSI_RDY, 324 GATE_SYSRAM, 325 GATE_RETRAM, 326 GATE_SRAM1, 327 GATE_SRAM2, 328 329 GATE_DDRPHYC, 330 GATE_SYSCPU1, 331 GATE_CRC, 332 GATE_OSPIIOM, 333 GATE_BKPSRAM, 334 GATE_HASH, 335 GATE_RNG, 336 GATE_CRYP1, 337 GATE_CRYP2, 338 GATE_SAES, 339 GATE_PKA, 340 341 GATE_GPIOA, 342 GATE_GPIOB, 343 GATE_GPIOC, 344 GATE_GPIOD, 345 GATE_GPIOE, 346 GATE_GPIOF, 347 GATE_GPIOG, 348 GATE_GPIOH, 349 GATE_GPIOI, 350 GATE_GPIOJ, 351 GATE_GPIOK, 352 GATE_GPIOZ, 353 GATE_RTC, 354 355 GATE_DDRCP, 356 357 /* WARNING 2 CLOCKS FOR ONE GATE */ 358 GATE_USB2OHCI, 359 GATE_USB2EHCI, 360 361 GATE_USB3DR, 362 363 GATE_BSEC, 364 GATE_IWDG1, 365 GATE_IWDG2, 366 367 GATE_DDRCAPB, 368 GATE_DDR, 369 370 GATE_USART2, 371 GATE_UART4, 372 GATE_USART3, 373 GATE_UART5, 374 GATE_I2C1, 375 GATE_I2C2, 376 GATE_I2C3, 377 GATE_I2C5, 378 GATE_I2C4, 379 GATE_I2C6, 380 GATE_I2C7, 381 GATE_USART1, 382 GATE_USART6, 383 GATE_UART7, 384 GATE_UART8, 385 GATE_UART9, 386 GATE_STGEN, 387 GATE_USB3PCIEPHY, 388 GATE_USBTC, 389 GATE_I2C8, 390 GATE_OSPI1, 391 GATE_OSPI2, 392 GATE_FMC, 393 GATE_SDMMC1, 394 GATE_SDMMC2, 395 GATE_USB2PHY1, 396 GATE_USB2PHY2, 397 LAST_GATE 398 }; 399 400 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ 401 .offset = (_offset),\ 402 .bit_idx = (_bit_idx),\ 403 .set_clr = (_offset_clr),\ 404 } 405 406 static const struct gate_cfg gates_mp25[LAST_GATE] = { 407 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 408 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0), 409 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 410 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 411 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 412 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0), 413 414 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0), 415 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 416 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0), 417 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 418 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 419 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0), 420 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0), 421 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0), 422 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0), 423 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0), 424 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0), 425 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 426 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), 427 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0), 428 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), 429 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), 430 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 431 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 432 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 433 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 434 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0), 435 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0), 436 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0), 437 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0), 438 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0), 439 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0), 440 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0), 441 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0), 442 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0), 443 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0), 444 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0), 445 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0), 446 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0), 447 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0), 448 449 /* WARNING 2 CLOCKS FOR ONE GATE */ 450 GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0), 451 GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0), 452 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), 453 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0), 454 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 455 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 456 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0), 457 GATE_CFG(GATE_DDR, RCC_DDRCFGR, 1, 0), 458 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 459 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 460 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 461 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 462 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 463 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 464 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 465 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), 466 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), 467 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), 468 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), 469 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 470 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 471 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 472 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), 473 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), 474 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), 475 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), 476 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0), 477 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), 478 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), 479 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), 480 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0), 481 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 482 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 483 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 484 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 485 }; 486 487 static const struct clk_div_table apb_div_table[] = { 488 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 }, 489 { 5, 16 }, { 6, 16 }, { 7, 16 }, { 0 }, 490 }; 491 492 #undef DIV_CFG 493 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ 494 .offset = _offset,\ 495 .shift = _shift,\ 496 .width = _width,\ 497 .flags = _flags,\ 498 .table = _table,\ 499 .bitrdy = _bitrdy,\ 500 } 501 502 static const struct div_cfg dividers_mp25[] = { 503 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), 504 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), 505 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), 506 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), 507 DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31), 508 DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31), 509 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0), 510 }; 511 512 enum stm32_osc { 513 OSC_HSI, 514 OSC_HSE, 515 OSC_MSI, 516 OSC_LSI, 517 OSC_LSE, 518 OSC_I2SCKIN, 519 OSC_SPDIFSYMB, 520 NB_OSCILLATOR 521 }; 522 523 static struct clk_oscillator_data stm32mp25_osc_data[] = { 524 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, 525 NULL, NULL, NULL), 526 527 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, 528 NULL, NULL, NULL), 529 530 OSCILLATOR(OSC_MSI, _CK_MSI, "clk-msi", GATE_MSI, GATE_MSI_RDY, 531 NULL, NULL, NULL), 532 533 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, 534 BYPASS(RCC_OCENSETR, 10, 7), 535 CSS(RCC_OCENSETR, 11), 536 NULL), 537 538 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, 539 BYPASS(RCC_BDCR, 1, 3), 540 CSS(RCC_BDCR, 8), 541 DRIVE(RCC_BDCR, 4, 2, 2)), 542 543 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, 544 NULL, NULL, NULL), 545 546 OSCILLATOR(OSC_SPDIFSYMB, _SPDIFSYMB, "spdif_symb", NO_GATE, NO_GATE, 547 NULL, NULL, NULL), 548 }; 549 550 #ifdef IMAGE_BL2 551 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) 552 { 553 if (id < NB_OSCILLATOR) { 554 return stm32mp25_osc_data[id].name; 555 } 556 557 return NULL; 558 } 559 #endif 560 561 enum pll_id { 562 _PLL1, 563 _PLL2, 564 _PLL3, 565 _PLL4, 566 _PLL5, 567 _PLL6, 568 _PLL7, 569 _PLL8, 570 _PLL_NB 571 }; 572 573 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */ 574 #define RCC_OFFSET_PLLXCFGR1 0x00 575 #define RCC_OFFSET_PLLXCFGR2 0x04 576 #define RCC_OFFSET_PLLXCFGR3 0x08 577 #define RCC_OFFSET_PLLXCFGR4 0x0C 578 #define RCC_OFFSET_PLLXCFGR5 0x10 579 #define RCC_OFFSET_PLLXCFGR6 0x18 580 #define RCC_OFFSET_PLLXCFGR7 0x1C 581 582 struct stm32_clk_pll { 583 uint16_t clk_id; 584 uint16_t reg_pllxcfgr1; 585 }; 586 587 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\ 588 [(_idx)] = {\ 589 .clk_id = (_clk_id),\ 590 .reg_pllxcfgr1 = (_reg),\ 591 } 592 593 static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = { 594 CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ), 595 CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1), 596 CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1), 597 CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1), 598 CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1), 599 CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1), 600 CLK_PLL_CFG(_PLL7, _CK_PLL7, RCC_PLL7CFGR1), 601 CLK_PLL_CFG(_PLL8, _CK_PLL8, RCC_PLL8CFGR1), 602 }; 603 604 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 605 { 606 return &stm32mp25_clk_pll[idx]; 607 } 608 609 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv, 610 const struct stm32_clk_pll *pll, 611 unsigned long prate) 612 { 613 unsigned long refclk, fvco; 614 uint32_t fracin, fbdiv, refdiv; 615 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 616 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 617 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 618 619 refclk = prate; 620 621 fracin = mmio_read_32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK; 622 fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> 623 RCC_PLLxCFGR2_FBDIV_SHIFT; 624 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; 625 626 if (fracin != 0U) { 627 uint64_t numerator, denominator; 628 629 numerator = ((uint64_t)fbdiv << 24) + fracin; 630 numerator = refclk * numerator; 631 denominator = (uint64_t)refdiv << 24; 632 fvco = (unsigned long)(numerator / denominator); 633 } else { 634 fvco = (unsigned long)(refclk * fbdiv / refdiv); 635 } 636 637 return fvco; 638 } 639 640 struct stm32_pll_cfg { 641 uint16_t pll_id; 642 }; 643 644 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 645 { 646 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 647 648 return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U); 649 } 650 651 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 652 { 653 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 654 655 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 656 } 657 658 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 659 { 660 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 661 662 /* Stop PLL */ 663 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 664 } 665 666 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, 667 const struct stm32_clk_pll *pll) 668 { 669 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 670 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 671 672 /* Wait PLL lock */ 673 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) { 674 if (timeout_elapsed(timeout)) { 675 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 676 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1, 677 mmio_read_32(pllxcfgr1)); 678 return -ETIMEDOUT; 679 } 680 } 681 682 return 0; 683 } 684 685 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, 686 const struct stm32_clk_pll *pll) 687 { 688 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 689 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 690 691 /* Wait PLL stopped */ 692 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) { 693 if (timeout_elapsed(timeout)) { 694 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 695 pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1)); 696 return -ETIMEDOUT; 697 } 698 } 699 700 return 0; 701 } 702 703 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 704 { 705 if (_clk_stm32_pll_is_enabled(priv, pll)) { 706 return 0; 707 } 708 709 _clk_stm32_pll_set_on(priv, pll); 710 711 return _clk_stm32_pll_wait_ready_on(priv, pll); 712 } 713 714 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 715 { 716 if (!_clk_stm32_pll_is_enabled(priv, pll)) { 717 return; 718 } 719 720 _clk_stm32_pll_set_off(priv, pll); 721 722 _clk_stm32_pll_wait_ready_off(priv, pll); 723 } 724 725 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) 726 { 727 const struct clk_stm32 *clk = _clk_get(priv, id); 728 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 729 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 730 731 return _clk_stm32_pll_is_enabled(priv, pll); 732 } 733 734 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) 735 { 736 const struct clk_stm32 *clk = _clk_get(priv, id); 737 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 738 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 739 740 return _clk_stm32_pll_enable(priv, pll); 741 } 742 743 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) 744 { 745 const struct clk_stm32 *clk = _clk_get(priv, id); 746 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 747 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 748 749 _clk_stm32_pll_disable(priv, pll); 750 } 751 752 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, 753 unsigned long prate) 754 { 755 const struct clk_stm32 *clk = _clk_get(priv, id); 756 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 757 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id); 758 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 759 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 760 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 761 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 762 unsigned long dfout; 763 uint32_t postdiv1, postdiv2; 764 765 postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; 766 postdiv2 = mmio_read_32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; 767 768 if ((mmio_read_32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) != 0U) { 769 dfout = prate; 770 } else { 771 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 772 dfout = prate; 773 } else { 774 dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2); 775 } 776 } 777 778 return dfout; 779 } 780 781 static const struct stm32_clk_ops clk_stm32_pll_ops = { 782 .recalc_rate = clk_stm32_pll_recalc_rate, 783 .enable = clk_stm32_pll_enable, 784 .disable = clk_stm32_pll_disable, 785 .is_enabled = clk_stm32_pll_is_enabled, 786 }; 787 788 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 789 .binding = _idx,\ 790 .parent = _parent,\ 791 .flags = (_flags),\ 792 .clock_cfg = &(struct stm32_pll_cfg) {\ 793 .pll_id = _pll_id,\ 794 },\ 795 .ops = STM32_PLL_OPS,\ 796 } 797 798 static unsigned long clk_get_pll1_fvco(unsigned long refclk) 799 { 800 uintptr_t pll_freq1_reg = A35SSC_BASE + A35_SS_PLL_FREQ1; 801 uint32_t reg, fbdiv, refdiv; 802 803 reg = mmio_read_32(pll_freq1_reg); 804 805 fbdiv = (reg & A35_SS_PLL_FREQ1_FBDIV_MASK) >> A35_SS_PLL_FREQ1_FBDIV_SHIFT; 806 refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT; 807 808 return (unsigned long)(refclk * fbdiv / refdiv); 809 } 810 811 static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv, 812 int id, unsigned long prate) 813 { 814 uintptr_t pll_freq2_reg = A35SSC_BASE + A35_SS_PLL_FREQ2; 815 uint32_t postdiv1, postdiv2; 816 unsigned long dfout; 817 818 postdiv1 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV1_MASK) >> 819 A35_SS_PLL_FREQ2_POSTDIV1_SHIFT; 820 postdiv2 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV2_MASK) >> 821 A35_SS_PLL_FREQ2_POSTDIV2_SHIFT; 822 823 if ((postdiv1 == 0U) || (postdiv2 == 0U)) { 824 dfout = prate; 825 } else { 826 dfout = clk_get_pll1_fvco(prate) / (postdiv1 * postdiv2); 827 } 828 829 return dfout; 830 } 831 832 static const struct stm32_clk_ops clk_stm32_pll1_ops = { 833 .recalc_rate = clk_stm32_pll1_recalc_rate, 834 }; 835 836 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ 837 .binding = _idx,\ 838 .parent = _parent,\ 839 .flags = (_flags),\ 840 .clock_cfg = &(struct stm32_pll_cfg) {\ 841 .pll_id = _pll_id,\ 842 },\ 843 .ops = STM32_PLL1_OPS,\ 844 } 845 846 struct stm32_clk_flexgen_cfg { 847 uint8_t id; 848 }; 849 850 static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx, 851 unsigned long prate) 852 { 853 const struct clk_stm32 *clk = _clk_get(priv, idx); 854 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 855 uintptr_t rcc_base = priv->base; 856 uint32_t prediv, findiv; 857 uint8_t channel = cfg->id; 858 unsigned long freq = prate; 859 860 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) & 861 RCC_PREDIVxCFGR_PREDIVx_MASK; 862 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 863 RCC_FINDIVxCFGR_FINDIVx_MASK; 864 865 if (freq == 0UL) { 866 return 0U; 867 } 868 869 switch (prediv) { 870 case 0x0: 871 case 0x1: 872 case 0x3: 873 case 0x3FF: 874 break; 875 876 default: 877 ERROR("Unsupported PREDIV value (%x)\n", prediv); 878 panic(); 879 break; 880 } 881 882 freq /= (prediv + 1U); 883 freq /= (findiv + 1U); 884 885 return freq; 886 } 887 888 static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx) 889 { 890 const struct clk_stm32 *clk = _clk_get(priv, idx); 891 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 892 uint32_t sel; 893 uint32_t address; 894 uintptr_t rcc_base = priv->base; 895 896 address = RCC_XBAR0CFGR + (cfg->id * 4); 897 898 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK; 899 900 return sel; 901 } 902 903 static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx) 904 { 905 const struct clk_stm32 *clk = _clk_get(priv, idx); 906 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 907 uintptr_t rcc_base = priv->base; 908 uint8_t channel = cfg->id; 909 910 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 911 RCC_FINDIVxCFGR_FINDIVxEN); 912 913 return 0; 914 } 915 916 static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id) 917 { 918 const struct clk_stm32 *clk = _clk_get(priv, id); 919 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 920 uintptr_t rcc_base = priv->base; 921 uint8_t channel = cfg->id; 922 923 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 924 RCC_FINDIVxCFGR_FINDIVxEN); 925 } 926 927 static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id) 928 { 929 const struct clk_stm32 *clk = _clk_get(priv, id); 930 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg; 931 uintptr_t rcc_base = priv->base; 932 uint8_t channel = cfg->id; 933 934 return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & 935 RCC_FINDIVxCFGR_FINDIVxEN); 936 } 937 938 static const struct stm32_clk_ops clk_stm32_flexgen_ops = { 939 .recalc_rate = clk_flexgen_recalc, 940 .get_parent = clk_flexgen_get_parent, 941 .enable = clk_flexgen_gate_enable, 942 .disable = clk_flexgen_gate_disable, 943 .is_enabled = clk_flexgen_gate_is_enabled, 944 }; 945 946 #define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\ 947 .binding = _idx,\ 948 .parent = MUX(MUX_XBARSEL),\ 949 .flags = (_flags),\ 950 .clock_cfg = &(struct stm32_clk_flexgen_cfg) {\ 951 .id = _id,\ 952 },\ 953 .ops = STM32_FLEXGEN_OPS,\ 954 } 955 956 #define RCC_0_MHZ UL(0) 957 #define RCC_4_MHZ UL(4000000) 958 #define RCC_16_MHZ UL(16000000) 959 960 #ifdef IMAGE_BL2 961 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, 962 unsigned long prate) 963 { 964 uintptr_t address = priv->base + RCC_BDCR; 965 uint32_t mask = RCC_BDCR_MSIFREQSEL; 966 int ret = -1; 967 968 switch (rate) { 969 case RCC_4_MHZ: 970 mmio_clrbits_32(address, mask); 971 ret = 0; 972 break; 973 974 case RCC_16_MHZ: 975 mmio_setbits_32(address, mask); 976 ret = 0; 977 break; 978 979 default: 980 break; 981 } 982 983 return ret; 984 } 985 #endif /* IMAGE_BL2 */ 986 987 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv, 988 int id __unused, 989 unsigned long prate __unused) 990 { 991 uintptr_t address = priv->base + RCC_BDCR; 992 993 if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) { 994 return RCC_4_MHZ; 995 } else { 996 return RCC_16_MHZ; 997 } 998 } 999 1000 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = { 1001 .recalc_rate = clk_stm32_osc_msi_recalc_rate, 1002 .is_enabled = clk_stm32_osc_gate_is_enabled, 1003 .enable = clk_stm32_osc_gate_enable, 1004 .disable = clk_stm32_osc_gate_disable, 1005 .init = clk_stm32_osc_init, 1006 }; 1007 1008 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \ 1009 [(idx)] = (struct clk_stm32){ \ 1010 .binding = (_idx),\ 1011 .parent = (_parent),\ 1012 .flags = CLK_IS_CRITICAL,\ 1013 .clock_cfg = &(struct stm32_osc_cfg){\ 1014 .osc_id = (_osc_id),\ 1015 },\ 1016 .ops = STM32_OSC_MSI_OPS,\ 1017 } 1018 1019 static const struct stm32_clk_ops clk_stm32_rtc_ops = { 1020 .enable = clk_stm32_gate_enable, 1021 .disable = clk_stm32_gate_disable, 1022 .is_enabled = clk_stm32_gate_is_enabled, 1023 }; 1024 1025 #define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\ 1026 .binding = (_binding),\ 1027 .parent = (_parent),\ 1028 .flags = (_flags),\ 1029 .clock_cfg = &(struct clk_stm32_gate_cfg) {\ 1030 .id = (_gate_id),\ 1031 },\ 1032 .ops = STM32_RTC_OPS,\ 1033 } 1034 1035 enum { 1036 STM32_PLL_OPS = STM32_LAST_OPS, 1037 STM32_PLL1_OPS, 1038 STM32_FLEXGEN_OPS, 1039 STM32_OSC_MSI_OPS, 1040 STM32_RTC_OPS, 1041 1042 MP25_LAST_OPS 1043 }; 1044 1045 static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = { 1046 [NO_OPS] = NULL, 1047 [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops, 1048 [GATE_OPS] = &clk_gate_ops, 1049 [STM32_MUX_OPS] = &clk_mux_ops, 1050 [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops, 1051 [STM32_GATE_OPS] = &clk_stm32_gate_ops, 1052 [STM32_TIMER_OPS] = &clk_timer_ops, 1053 [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops, 1054 [STM32_OSC_OPS] = &clk_stm32_osc_ops, 1055 [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops, 1056 1057 [STM32_PLL_OPS] = &clk_stm32_pll_ops, 1058 [STM32_PLL1_OPS] = &clk_stm32_pll1_ops, 1059 [STM32_FLEXGEN_OPS] = &clk_stm32_flexgen_ops, 1060 [STM32_OSC_MSI_OPS] = &clk_stm32_osc_msi_ops, 1061 [STM32_RTC_OPS] = &clk_stm32_rtc_ops 1062 }; 1063 1064 static const struct clk_stm32 stm32mp25_clk[CK_LAST] = { 1065 CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ), 1066 1067 /* ROOT CLOCKS */ 1068 CLK_OSC(_CK_HSE, HSE_CK, CLK_IS_ROOT, OSC_HSE), 1069 CLK_OSC(_CK_LSE, LSE_CK, CLK_IS_ROOT, OSC_LSE), 1070 CLK_OSC(_CK_HSI, HSI_CK, CLK_IS_ROOT, OSC_HSI), 1071 CLK_OSC(_CK_LSI, LSI_CK, CLK_IS_ROOT, OSC_LSI), 1072 CLK_OSC_MSI(_CK_MSI, MSI_CK, CLK_IS_ROOT, OSC_MSI), 1073 1074 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), 1075 CLK_OSC_FIXED(_SPDIFSYMB, _NO_ID, CLK_IS_ROOT, OSC_SPDIFSYMB), 1076 1077 STM32_DIV(_CK_HSE_RTC, _NO_ID, _CK_HSE, 0, DIV_RTC), 1078 1079 CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK), 1080 1081 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0), 1082 1083 CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0), 1084 CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0), 1085 CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0), 1086 CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0), 1087 CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0), 1088 CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0), 1089 CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0), 1090 1091 FLEXGEN(_CK_ICN_HS_MCU, CK_ICN_HS_MCU, CLK_IS_CRITICAL, 0), 1092 FLEXGEN(_CK_ICN_SDMMC, CK_ICN_SDMMC, CLK_IS_CRITICAL, 1), 1093 FLEXGEN(_CK_ICN_DDR, CK_ICN_DDR, CLK_IS_CRITICAL, 2), 1094 FLEXGEN(_CK_ICN_HSL, CK_ICN_HSL, CLK_IS_CRITICAL, 4), 1095 FLEXGEN(_CK_ICN_NIC, CK_ICN_NIC, CLK_IS_CRITICAL, 5), 1096 1097 STM32_DIV(_CK_ICN_LS_MCU, CK_ICN_LS_MCU, _CK_ICN_HS_MCU, 0, DIV_LSMCU), 1098 1099 FLEXGEN(_CK_FLEXGEN_07, CK_FLEXGEN_07, 0, 7), 1100 FLEXGEN(_CK_FLEXGEN_08, CK_FLEXGEN_08, 0, 8), 1101 FLEXGEN(_CK_FLEXGEN_09, CK_FLEXGEN_09, 0, 9), 1102 FLEXGEN(_CK_FLEXGEN_10, CK_FLEXGEN_10, 0, 10), 1103 FLEXGEN(_CK_FLEXGEN_11, CK_FLEXGEN_11, 0, 11), 1104 FLEXGEN(_CK_FLEXGEN_12, CK_FLEXGEN_12, 0, 12), 1105 FLEXGEN(_CK_FLEXGEN_13, CK_FLEXGEN_13, 0, 13), 1106 FLEXGEN(_CK_FLEXGEN_14, CK_FLEXGEN_14, 0, 14), 1107 FLEXGEN(_CK_FLEXGEN_15, CK_FLEXGEN_15, 0, 15), 1108 FLEXGEN(_CK_FLEXGEN_16, CK_FLEXGEN_16, 0, 16), 1109 FLEXGEN(_CK_FLEXGEN_17, CK_FLEXGEN_17, 0, 17), 1110 FLEXGEN(_CK_FLEXGEN_18, CK_FLEXGEN_18, 0, 18), 1111 FLEXGEN(_CK_FLEXGEN_19, CK_FLEXGEN_19, 0, 19), 1112 FLEXGEN(_CK_FLEXGEN_20, CK_FLEXGEN_20, 0, 20), 1113 FLEXGEN(_CK_FLEXGEN_21, CK_FLEXGEN_21, 0, 21), 1114 FLEXGEN(_CK_FLEXGEN_22, CK_FLEXGEN_22, 0, 22), 1115 FLEXGEN(_CK_FLEXGEN_23, CK_FLEXGEN_23, 0, 23), 1116 FLEXGEN(_CK_FLEXGEN_24, CK_FLEXGEN_24, 0, 24), 1117 FLEXGEN(_CK_FLEXGEN_25, CK_FLEXGEN_25, 0, 25), 1118 FLEXGEN(_CK_FLEXGEN_26, CK_FLEXGEN_26, 0, 26), 1119 FLEXGEN(_CK_FLEXGEN_27, CK_FLEXGEN_27, 0, 27), 1120 FLEXGEN(_CK_FLEXGEN_28, CK_FLEXGEN_28, 0, 28), 1121 FLEXGEN(_CK_FLEXGEN_29, CK_FLEXGEN_29, 0, 29), 1122 FLEXGEN(_CK_FLEXGEN_30, CK_FLEXGEN_30, 0, 30), 1123 FLEXGEN(_CK_FLEXGEN_31, CK_FLEXGEN_31, 0, 31), 1124 FLEXGEN(_CK_FLEXGEN_32, CK_FLEXGEN_32, 0, 32), 1125 FLEXGEN(_CK_FLEXGEN_33, CK_FLEXGEN_33, 0, 33), 1126 FLEXGEN(_CK_FLEXGEN_34, CK_FLEXGEN_34, 0, 34), 1127 FLEXGEN(_CK_FLEXGEN_35, CK_FLEXGEN_35, 0, 35), 1128 FLEXGEN(_CK_FLEXGEN_36, CK_FLEXGEN_36, 0, 36), 1129 FLEXGEN(_CK_FLEXGEN_37, CK_FLEXGEN_37, 0, 37), 1130 FLEXGEN(_CK_FLEXGEN_38, CK_FLEXGEN_38, 0, 38), 1131 FLEXGEN(_CK_FLEXGEN_39, CK_FLEXGEN_39, 0, 39), 1132 FLEXGEN(_CK_FLEXGEN_40, CK_FLEXGEN_40, 0, 40), 1133 FLEXGEN(_CK_FLEXGEN_41, CK_FLEXGEN_41, 0, 41), 1134 FLEXGEN(_CK_FLEXGEN_42, CK_FLEXGEN_42, 0, 42), 1135 FLEXGEN(_CK_FLEXGEN_43, CK_FLEXGEN_43, 0, 43), 1136 FLEXGEN(_CK_FLEXGEN_44, CK_FLEXGEN_44, 0, 44), 1137 FLEXGEN(_CK_FLEXGEN_45, CK_FLEXGEN_45, 0, 45), 1138 FLEXGEN(_CK_FLEXGEN_46, CK_FLEXGEN_46, 0, 46), 1139 FLEXGEN(_CK_FLEXGEN_47, CK_FLEXGEN_47, 0, 47), 1140 FLEXGEN(_CK_FLEXGEN_48, CK_FLEXGEN_48, 0, 48), 1141 FLEXGEN(_CK_FLEXGEN_49, CK_FLEXGEN_49, 0, 49), 1142 FLEXGEN(_CK_FLEXGEN_50, CK_FLEXGEN_50, 0, 50), 1143 FLEXGEN(_CK_FLEXGEN_51, CK_FLEXGEN_51, 0, 51), 1144 FLEXGEN(_CK_FLEXGEN_52, CK_FLEXGEN_52, 0, 52), 1145 FLEXGEN(_CK_FLEXGEN_53, CK_FLEXGEN_53, 0, 53), 1146 FLEXGEN(_CK_FLEXGEN_54, CK_FLEXGEN_54, 0, 54), 1147 FLEXGEN(_CK_FLEXGEN_55, CK_FLEXGEN_55, 0, 55), 1148 FLEXGEN(_CK_FLEXGEN_56, CK_FLEXGEN_56, 0, 56), 1149 FLEXGEN(_CK_FLEXGEN_57, CK_FLEXGEN_57, 0, 57), 1150 FLEXGEN(_CK_FLEXGEN_58, CK_FLEXGEN_58, 0, 58), 1151 FLEXGEN(_CK_FLEXGEN_59, CK_FLEXGEN_59, 0, 59), 1152 FLEXGEN(_CK_FLEXGEN_60, CK_FLEXGEN_60, 0, 60), 1153 FLEXGEN(_CK_FLEXGEN_61, CK_FLEXGEN_61, 0, 61), 1154 FLEXGEN(_CK_FLEXGEN_62, CK_FLEXGEN_62, 0, 62), 1155 FLEXGEN(_CK_FLEXGEN_63, CK_FLEXGEN_63, 0, 63), 1156 1157 STM32_DIV(_CK_ICN_APB1, CK_ICN_APB1, _CK_ICN_LS_MCU, 0, DIV_APB1), 1158 STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2), 1159 STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3), 1160 STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4), 1161 STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG), 1162 1163 /* KERNEL CLOCK */ 1164 STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM), 1165 STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM), 1166 STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1), 1167 STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2), 1168 1169 STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC), 1170 STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1), 1171 STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC), 1172 STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM), 1173 STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM), 1174 STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH), 1175 STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG), 1176 STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1), 1177 STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2), 1178 STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES), 1179 STM32_GATE(_CK_PKA, CK_BUS_PKA, _CK_ICN_LS_MCU, 0, GATE_PKA), 1180 1181 STM32_GATE(_CK_GPIOA, CK_BUS_GPIOA, _CK_ICN_LS_MCU, 0, GATE_GPIOA), 1182 STM32_GATE(_CK_GPIOB, CK_BUS_GPIOB, _CK_ICN_LS_MCU, 0, GATE_GPIOB), 1183 STM32_GATE(_CK_GPIOC, CK_BUS_GPIOC, _CK_ICN_LS_MCU, 0, GATE_GPIOC), 1184 STM32_GATE(_CK_GPIOD, CK_BUS_GPIOD, _CK_ICN_LS_MCU, 0, GATE_GPIOD), 1185 STM32_GATE(_CK_GPIOE, CK_BUS_GPIOE, _CK_ICN_LS_MCU, 0, GATE_GPIOE), 1186 STM32_GATE(_CK_GPIOF, CK_BUS_GPIOF, _CK_ICN_LS_MCU, 0, GATE_GPIOF), 1187 STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG), 1188 STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH), 1189 STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI), 1190 STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ), 1191 STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK), 1192 STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ), 1193 STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC), 1194 1195 STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP), 1196 1197 /* WARNING 2 CLOCKS FOR ONE GATE */ 1198 STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI), 1199 STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI), 1200 1201 STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR), 1202 1203 STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC), 1204 STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1), 1205 STM32_GATE(_CK_IWDG2, CK_BUS_IWDG2, _CK_ICN_APB3, 0, GATE_IWDG2), 1206 1207 STM32_GATE(_CK_DDRCAPB, CK_BUS_DDRC, _CK_ICN_APB4, 0, GATE_DDRCAPB), 1208 STM32_GATE(_CK_DDR, CK_BUS_DDRCFG, _CK_ICN_APB4, 0, GATE_DDR), 1209 1210 STM32_GATE(_CK_USART2, CK_KER_USART2, _CK_FLEXGEN_08, 0, GATE_USART2), 1211 STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4), 1212 STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3), 1213 STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5), 1214 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1), 1215 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2), 1216 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3), 1217 STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5), 1218 STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4), 1219 STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6), 1220 STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7), 1221 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1), 1222 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6), 1223 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7), 1224 STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8), 1225 STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9), 1226 STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN), 1227 STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY), 1228 STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC), 1229 STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8), 1230 STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1), 1231 STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2), 1232 STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC), 1233 STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1), 1234 STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2), 1235 STM32_GATE(_CK_USB2PHY1, CK_KER_USB2PHY1, _CK_FLEXGEN_57, 0, GATE_USB2PHY1), 1236 STM32_GATE(_CK_USB2PHY2, CK_KER_USB2PHY2, _CK_FLEXGEN_58, 0, GATE_USB2PHY2), 1237 }; 1238 1239 enum clksrc_id { 1240 CLKSRC_CA35SS, 1241 CLKSRC_PLL1, 1242 CLKSRC_PLL2, 1243 CLKSRC_PLL3, 1244 CLKSRC_PLL4, 1245 CLKSRC_PLL5, 1246 CLKSRC_PLL6, 1247 CLKSRC_PLL7, 1248 CLKSRC_PLL8, 1249 CLKSRC_XBAR_CHANNEL0, 1250 CLKSRC_XBAR_CHANNEL1, 1251 CLKSRC_XBAR_CHANNEL2, 1252 CLKSRC_XBAR_CHANNEL3, 1253 CLKSRC_XBAR_CHANNEL4, 1254 CLKSRC_XBAR_CHANNEL5, 1255 CLKSRC_XBAR_CHANNEL6, 1256 CLKSRC_XBAR_CHANNEL7, 1257 CLKSRC_XBAR_CHANNEL8, 1258 CLKSRC_XBAR_CHANNEL9, 1259 CLKSRC_XBAR_CHANNEL10, 1260 CLKSRC_XBAR_CHANNEL11, 1261 CLKSRC_XBAR_CHANNEL12, 1262 CLKSRC_XBAR_CHANNEL13, 1263 CLKSRC_XBAR_CHANNEL14, 1264 CLKSRC_XBAR_CHANNEL15, 1265 CLKSRC_XBAR_CHANNEL16, 1266 CLKSRC_XBAR_CHANNEL17, 1267 CLKSRC_XBAR_CHANNEL18, 1268 CLKSRC_XBAR_CHANNEL19, 1269 CLKSRC_XBAR_CHANNEL20, 1270 CLKSRC_XBAR_CHANNEL21, 1271 CLKSRC_XBAR_CHANNEL22, 1272 CLKSRC_XBAR_CHANNEL23, 1273 CLKSRC_XBAR_CHANNEL24, 1274 CLKSRC_XBAR_CHANNEL25, 1275 CLKSRC_XBAR_CHANNEL26, 1276 CLKSRC_XBAR_CHANNEL27, 1277 CLKSRC_XBAR_CHANNEL28, 1278 CLKSRC_XBAR_CHANNEL29, 1279 CLKSRC_XBAR_CHANNEL30, 1280 CLKSRC_XBAR_CHANNEL31, 1281 CLKSRC_XBAR_CHANNEL32, 1282 CLKSRC_XBAR_CHANNEL33, 1283 CLKSRC_XBAR_CHANNEL34, 1284 CLKSRC_XBAR_CHANNEL35, 1285 CLKSRC_XBAR_CHANNEL36, 1286 CLKSRC_XBAR_CHANNEL37, 1287 CLKSRC_XBAR_CHANNEL38, 1288 CLKSRC_XBAR_CHANNEL39, 1289 CLKSRC_XBAR_CHANNEL40, 1290 CLKSRC_XBAR_CHANNEL41, 1291 CLKSRC_XBAR_CHANNEL42, 1292 CLKSRC_XBAR_CHANNEL43, 1293 CLKSRC_XBAR_CHANNEL44, 1294 CLKSRC_XBAR_CHANNEL45, 1295 CLKSRC_XBAR_CHANNEL46, 1296 CLKSRC_XBAR_CHANNEL47, 1297 CLKSRC_XBAR_CHANNEL48, 1298 CLKSRC_XBAR_CHANNEL49, 1299 CLKSRC_XBAR_CHANNEL50, 1300 CLKSRC_XBAR_CHANNEL51, 1301 CLKSRC_XBAR_CHANNEL52, 1302 CLKSRC_XBAR_CHANNEL53, 1303 CLKSRC_XBAR_CHANNEL54, 1304 CLKSRC_XBAR_CHANNEL55, 1305 CLKSRC_XBAR_CHANNEL56, 1306 CLKSRC_XBAR_CHANNEL57, 1307 CLKSRC_XBAR_CHANNEL58, 1308 CLKSRC_XBAR_CHANNEL59, 1309 CLKSRC_XBAR_CHANNEL60, 1310 CLKSRC_XBAR_CHANNEL61, 1311 CLKSRC_XBAR_CHANNEL62, 1312 CLKSRC_XBAR_CHANNEL63, 1313 CLKSRC_RTC, 1314 CLKSRC_MCO1, 1315 CLKSRC_MCO2, 1316 CLKSRC_NB 1317 }; 1318 1319 static void stm32mp2_a35_ss_on_hsi(void) 1320 { 1321 uintptr_t a35_ss_address = A35SSC_BASE; 1322 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1323 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1324 uint64_t timeout; 1325 1326 if ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) == 1327 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1328 /* Nothing to do, clock source is already set on bypass clock */ 1329 return; 1330 } 1331 1332 mmio_setbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1333 1334 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1335 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 1336 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) { 1337 if (timeout_elapsed(timeout)) { 1338 EARLY_ERROR("Cannot switch A35 to bypass clock\n"); 1339 panic(); 1340 } 1341 } 1342 1343 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1344 } 1345 1346 #ifdef IMAGE_BL2 1347 static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv) 1348 { 1349 mmio_clrbits_32(priv->base + RCC_MUXSELCFGR, 1350 RCC_MUXSELCFGR_MUXSEL0_MASK | 1351 RCC_MUXSELCFGR_MUXSEL1_MASK | 1352 RCC_MUXSELCFGR_MUXSEL2_MASK | 1353 RCC_MUXSELCFGR_MUXSEL3_MASK | 1354 RCC_MUXSELCFGR_MUXSEL4_MASK | 1355 RCC_MUXSELCFGR_MUXSEL5_MASK | 1356 RCC_MUXSELCFGR_MUXSEL6_MASK | 1357 RCC_MUXSELCFGR_MUXSEL7_MASK); 1358 } 1359 1360 static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv) 1361 { 1362 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; 1363 uint32_t i; 1364 1365 for (i = 0; i < XBAR_CHANNEL_NB; i++) { 1366 mmio_clrsetbits_32(xbar0cfgr + (0x4 * i), 1367 RCC_XBAR0CFGR_XBAR0SEL_MASK, 1368 XBAR_SRC_HSI); 1369 } 1370 } 1371 1372 static int stm32mp2_a35_pll1_start(void) 1373 { 1374 uintptr_t a35_ss_address = A35SSC_BASE; 1375 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 1376 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ; 1377 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1378 1379 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 1380 1381 /* Wait PLL lock */ 1382 while ((mmio_read_32(pll_enable_reg) & A35_SS_PLL_ENABLE_LOCKP) == 0U) { 1383 if (timeout_elapsed(timeout)) { 1384 EARLY_ERROR("PLL1 start failed @ 0x%lx: 0x%x\n", 1385 pll_enable_reg, mmio_read_32(pll_enable_reg)); 1386 return -ETIMEDOUT; 1387 } 1388 } 1389 1390 /* De-assert reset on PLL output clock path */ 1391 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF); 1392 1393 /* Switch CPU clock to PLL clock */ 1394 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ); 1395 1396 /* Wait for clock change acknowledge */ 1397 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1398 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 0U) { 1399 if (timeout_elapsed(timeout)) { 1400 EARLY_ERROR("CA35SS switch to PLL1 failed @ 0x%lx: 0x%x\n", 1401 chgclkreq_reg, mmio_read_32(chgclkreq_reg)); 1402 return -ETIMEDOUT; 1403 } 1404 } 1405 1406 return 0; 1407 } 1408 1409 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1, 1410 uint32_t postdiv2) 1411 { 1412 uintptr_t a35_ss_address = A35SSC_BASE; 1413 uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1; 1414 uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2; 1415 1416 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_REFDIV_MASK, 1417 (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) & 1418 A35_SS_PLL_FREQ1_REFDIV_MASK); 1419 1420 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_FBDIV_MASK, 1421 (fbdiv << A35_SS_PLL_FREQ1_FBDIV_SHIFT) & 1422 A35_SS_PLL_FREQ1_FBDIV_MASK); 1423 1424 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV1_MASK, 1425 (postdiv1 << A35_SS_PLL_FREQ2_POSTDIV1_SHIFT) & 1426 A35_SS_PLL_FREQ2_POSTDIV1_MASK); 1427 1428 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV2_MASK, 1429 (postdiv2 << A35_SS_PLL_FREQ2_POSTDIV2_SHIFT) & 1430 A35_SS_PLL_FREQ2_POSTDIV2_MASK); 1431 } 1432 1433 static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv, 1434 const struct stm32_clk_pll *pll, 1435 uint32_t *pllcfg, 1436 uint32_t fracv) 1437 { 1438 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1439 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 1440 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1441 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1442 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 1443 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 1444 unsigned long refclk; 1445 1446 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1447 1448 if (fracv == 0U) { 1449 /* PLL in integer mode */ 1450 1451 /* 1452 * No need to check max clock, as oscillator reference clocks 1453 * will always be less than 1.2GHz 1454 */ 1455 if (refclk < PLL_REFCLK_MIN) { 1456 panic(); 1457 } 1458 1459 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK); 1460 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1461 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1462 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1463 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1464 } else { 1465 /* PLL in frac mode */ 1466 1467 /* 1468 * No need to check max clock, as oscillator reference clocks 1469 * will always be less than 1.2GHz 1470 */ 1471 if (refclk < PLL_FRAC_REFCLK_MIN) { 1472 panic(); 1473 } 1474 1475 mmio_clrsetbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, 1476 fracv & RCC_PLLxCFGR3_FRACIN_MASK); 1477 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1478 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1479 } 1480 1481 assert(pllcfg[REFDIV] != 0U); 1482 1483 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, 1484 (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) & 1485 RCC_PLLxCFGR2_FBDIV_MASK); 1486 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, 1487 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); 1488 mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, 1489 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); 1490 mmio_clrsetbits_32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, 1491 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); 1492 1493 if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) { 1494 /* Bypass mode */ 1495 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1496 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1497 } else { 1498 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1499 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1500 } 1501 1502 return 0; 1503 } 1504 1505 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, 1506 const struct stm32_clk_pll *pll, 1507 uint32_t *csg) 1508 { 1509 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1510 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1511 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1512 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5; 1513 1514 1515 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, 1516 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); 1517 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, 1518 (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) & 1519 RCC_PLLxCFGR5_SPREAD_MASK); 1520 1521 if (csg[DOWNSPREAD] != 0) { 1522 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1523 } else { 1524 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1525 } 1526 1527 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1528 1529 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 1530 udelay(1); 1531 1532 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1533 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1534 } 1535 1536 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data); 1537 1538 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) 1539 { 1540 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1541 struct stm32_clk_platdata *pdata = priv->pdata; 1542 1543 return &pdata->pll[pll_idx]; 1544 } 1545 1546 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx, 1547 struct stm32_pll_dt_cfg *pll_conf) 1548 { 1549 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1550 unsigned long refclk; 1551 int ret = 0; 1552 1553 stm32mp2_a35_ss_on_hsi(); 1554 1555 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1556 if (ret != 0) { 1557 panic(); 1558 } 1559 1560 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1561 1562 /* 1563 * No need to check max clock, as oscillator reference clocks will 1564 * always be less than 1.2 GHz 1565 */ 1566 if (refclk < PLL_REFCLK_MIN) { 1567 EARLY_ERROR("%s: %d\n", __func__, __LINE__); 1568 panic(); 1569 } 1570 1571 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV], 1572 pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]); 1573 1574 ret = stm32mp2_a35_pll1_start(); 1575 if (ret != 0) { 1576 panic(); 1577 } 1578 1579 return 0; 1580 } 1581 1582 static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv, 1583 const struct stm32_clk_pll *pll) 1584 { 1585 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1586 uint64_t timeout = timeout_init_us(CLKSRC_TIMEOUT); 1587 1588 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) != 1589 RCC_PLLxCFGR1_CKREFST) { 1590 if (timeout_elapsed(timeout)) { 1591 EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1); 1592 return -ETIMEDOUT; 1593 } 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, 1600 struct stm32_pll_dt_cfg *pll_conf) 1601 { 1602 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1603 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1604 bool spread_spectrum = false; 1605 int ret = 0; 1606 1607 _clk_stm32_pll_disable(priv, pll); 1608 1609 ret = stm32_clk_configure_mux(priv, pll_conf->src); 1610 if (ret != 0) { 1611 panic(); 1612 } 1613 1614 ret = clk_stm32_pll_wait_mux_ready(priv, pll); 1615 if (ret != 0) { 1616 panic(); 1617 } 1618 1619 ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac); 1620 if (ret != 0) { 1621 panic(); 1622 } 1623 1624 if (pll_conf->csg_enabled) { 1625 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); 1626 spread_spectrum = true; 1627 } 1628 1629 _clk_stm32_pll_enable(priv, pll); 1630 1631 if (spread_spectrum) { 1632 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) 1639 { 1640 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); 1641 1642 if (pll_conf->enabled) { 1643 if (pll_idx == _PLL1) { 1644 return _clk_stm32_pll1_init(priv, pll_idx, pll_conf); 1645 } else { 1646 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); 1647 } 1648 } 1649 1650 return 0; 1651 } 1652 1653 static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv) 1654 { 1655 enum pll_id i; 1656 int err; 1657 1658 for (i = _PLL1; i < _PLL_NB; i++) { 1659 err = clk_stm32_pll_init(priv, i); 1660 if (err) { 1661 return err; 1662 } 1663 } 1664 1665 return 0; 1666 } 1667 1668 static int wait_predivsr(uint16_t channel) 1669 { 1670 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1671 uintptr_t rcc_base = priv->base; 1672 uintptr_t previvsr; 1673 uint32_t channel_bit; 1674 uint64_t timeout; 1675 1676 if (channel < __WORD_BIT) { 1677 previvsr = rcc_base + RCC_PREDIVSR1; 1678 channel_bit = BIT(channel); 1679 } else { 1680 previvsr = rcc_base + RCC_PREDIVSR2; 1681 channel_bit = BIT(channel - __WORD_BIT); 1682 } 1683 1684 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1685 while ((mmio_read_32(previvsr) & channel_bit) != 0U) { 1686 if (timeout_elapsed(timeout)) { 1687 EARLY_ERROR("Pre divider status: %x\n", 1688 mmio_read_32(previvsr)); 1689 return -ETIMEDOUT; 1690 } 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int wait_findivsr(uint16_t channel) 1697 { 1698 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1699 uintptr_t rcc_base = priv->base; 1700 uintptr_t finvivsr; 1701 uint32_t channel_bit; 1702 uint64_t timeout; 1703 1704 if (channel < __WORD_BIT) { 1705 finvivsr = rcc_base + RCC_FINDIVSR1; 1706 channel_bit = BIT(channel); 1707 } else { 1708 finvivsr = rcc_base + RCC_FINDIVSR2; 1709 channel_bit = BIT(channel - __WORD_BIT); 1710 } 1711 1712 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1713 while ((mmio_read_32(finvivsr) & channel_bit) != 0U) { 1714 if (timeout_elapsed(timeout)) { 1715 EARLY_ERROR("Final divider status: %x\n", 1716 mmio_read_32(finvivsr)); 1717 return -ETIMEDOUT; 1718 } 1719 } 1720 1721 return 0; 1722 } 1723 1724 static int wait_xbar_sts(uint16_t channel) 1725 { 1726 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1727 uintptr_t rcc_base = priv->base; 1728 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4U * channel); 1729 uint64_t timeout; 1730 1731 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1732 while ((mmio_read_32(xbar_cfgr) & RCC_XBAR0CFGR_XBAR0STS) != 0U) { 1733 if (timeout_elapsed(timeout)) { 1734 EARLY_ERROR("XBAR%uCFGR: %x\n", channel, 1735 mmio_read_32(xbar_cfgr)); 1736 return -ETIMEDOUT; 1737 } 1738 } 1739 1740 return 0; 1741 } 1742 1743 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, 1744 unsigned int prediv, unsigned int findiv) 1745 { 1746 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1747 uintptr_t rcc_base = priv->base; 1748 1749 if (wait_predivsr(channel) != 0) { 1750 panic(); 1751 } 1752 1753 mmio_clrsetbits_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel), 1754 RCC_PREDIV0CFGR_PREDIV0_MASK, 1755 prediv); 1756 1757 if (wait_predivsr(channel) != 0) { 1758 panic(); 1759 } 1760 1761 if (wait_findivsr(channel) != 0) { 1762 panic(); 1763 } 1764 1765 mmio_clrsetbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), 1766 RCC_FINDIV0CFGR_FINDIV0_MASK, 1767 findiv); 1768 1769 if (wait_findivsr(channel) != 0) { 1770 panic(); 1771 } 1772 1773 if (wait_xbar_sts(channel) != 0) { 1774 panic(); 1775 } 1776 1777 mmio_clrsetbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1778 RCC_XBARxCFGR_XBARxSEL_MASK, 1779 clk_src); 1780 mmio_setbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel), 1781 RCC_XBARxCFGR_XBARxEN); 1782 1783 if (wait_xbar_sts(channel) != 0) { 1784 panic(); 1785 } 1786 } 1787 1788 static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv) 1789 { 1790 struct stm32_clk_platdata *pdata = priv->pdata; 1791 uint32_t i; 1792 1793 for (i = 0U; i < pdata->nflexgen; i++) { 1794 uint32_t val = pdata->flexgen[i]; 1795 uint32_t cmd, cmd_data; 1796 unsigned int channel, clk_src, pdiv, fdiv; 1797 1798 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1799 cmd_data = val & ~CMD_MASK; 1800 1801 if (cmd != CMD_FLEXGEN) { 1802 continue; 1803 } 1804 1805 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 1806 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 1807 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 1808 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 1809 1810 switch (channel) { 1811 case 33U: /* STGEN */ 1812 break; 1813 1814 default: 1815 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 1816 break; 1817 } 1818 } 1819 1820 return 0; 1821 } 1822 1823 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) 1824 { 1825 struct stm32_clk_platdata *pdata = priv->pdata; 1826 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 1827 bool digbyp = osci->digbyp; 1828 bool bypass = osci->bypass; 1829 bool css = osci->css; 1830 1831 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { 1832 return; 1833 } 1834 1835 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); 1836 1837 _clk_stm32_enable(priv, _CK_HSE); 1838 1839 clk_oscillator_set_css(priv, _CK_HSE, css); 1840 } 1841 1842 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) 1843 { 1844 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); 1845 struct stm32_clk_platdata *pdata = priv->pdata; 1846 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 1847 bool digbyp = osci->digbyp; 1848 bool bypass = osci->bypass; 1849 uint8_t drive = osci->drive; 1850 1851 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { 1852 return; 1853 } 1854 1855 /* Do not reconfigure LSE if already enabled */ 1856 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) { 1857 return; 1858 } 1859 1860 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); 1861 1862 clk_oscillator_set_drive(priv, _CK_LSE, drive); 1863 1864 _clk_stm32_gate_enable(priv, osc_data->gate_id); 1865 } 1866 1867 static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv) 1868 { 1869 stm32mp2_a35_ss_on_hsi(); 1870 stm32mp2_clk_muxsel_on_hsi(priv); 1871 stm32mp2_clk_xbar_on_hsi(priv); 1872 1873 return 0; 1874 } 1875 1876 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) 1877 { 1878 int ret = 0; 1879 1880 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { 1881 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); 1882 } 1883 1884 return ret; 1885 } 1886 1887 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv) 1888 { 1889 struct stm32_clk_platdata *pdata = priv->pdata; 1890 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI]; 1891 int err; 1892 1893 err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0); 1894 if (err != 0) { 1895 EARLY_ERROR("Invalid rate %lu MHz for MSI ! (4 or 16 only)\n", 1896 osci->freq / 1000000U); 1897 panic(); 1898 } 1899 1900 _clk_stm32_enable(priv, _CK_MSI); 1901 } 1902 1903 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) 1904 { 1905 stm32_enable_oscillator_hse(priv); 1906 stm32_enable_oscillator_lse(priv); 1907 stm32_enable_oscillator_msi(priv); 1908 _clk_stm32_enable(priv, _CK_LSI); 1909 } 1910 1911 static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data) 1912 { 1913 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 1914 int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 1915 1916 return clk_stm32_set_div(priv, div_id, div_n); 1917 } 1918 1919 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) 1920 { 1921 int mux_id = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 1922 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1923 1924 return clk_mux_set_parent(priv, mux_id, sel); 1925 } 1926 1927 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) 1928 { 1929 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 1930 1931 return clk_get_index(priv, binding_id); 1932 } 1933 1934 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 1935 { 1936 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 1937 bool enable = ((data & CLK_ON_MASK) >> CLK_ON_SHIFT) != 0U; 1938 int clk_id = 0; 1939 int ret = 0; 1940 1941 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); 1942 if (clk_id < 0) { 1943 return clk_id; 1944 } 1945 1946 if (sel != CLK_NOMUX) { 1947 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); 1948 if (ret != 0) { 1949 return ret; 1950 } 1951 } 1952 1953 if (enable) { 1954 clk_stm32_enable_call_ops(priv, clk_id); 1955 } else { 1956 clk_stm32_disable_call_ops(priv, clk_id); 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val) 1963 { 1964 uint32_t cmd = (val & CMD_MASK) >> CMD_SHIFT; 1965 uint32_t cmd_data = val & ~CMD_MASK; 1966 int ret = -1; 1967 1968 switch (cmd) { 1969 case CMD_DIV: 1970 ret = stm32_clk_configure_div(priv, cmd_data); 1971 break; 1972 1973 case CMD_MUX: 1974 ret = stm32_clk_configure_mux(priv, cmd_data); 1975 break; 1976 1977 case CMD_CLK: 1978 ret = stm32_clk_configure_clk(priv, cmd_data); 1979 break; 1980 1981 default: 1982 EARLY_ERROR("%s: cmd unknown ! : 0x%x\n", __func__, val); 1983 break; 1984 } 1985 1986 return ret; 1987 } 1988 1989 static int stm32_clk_bus_configure(struct stm32_clk_priv *priv) 1990 { 1991 struct stm32_clk_platdata *pdata = priv->pdata; 1992 uint32_t i; 1993 1994 for (i = 0; i < pdata->nbusclk; i++) { 1995 int ret; 1996 1997 ret = stm32_clk_configure(priv, pdata->busclk[i]); 1998 if (ret != 0) { 1999 return ret; 2000 } 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv) 2007 { 2008 struct stm32_clk_platdata *pdata = priv->pdata; 2009 uint32_t i; 2010 2011 for (i = 0U; i < pdata->nkernelclk; i++) { 2012 int ret; 2013 2014 ret = stm32_clk_configure(priv, pdata->kernelclk[i]); 2015 if (ret != 0) { 2016 return ret; 2017 } 2018 } 2019 2020 return 0; 2021 } 2022 2023 static int stm32mp2_init_clock_tree(void) 2024 { 2025 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 2026 int ret; 2027 2028 /* Set timer with STGEN without changing its clock source */ 2029 stm32mp_stgen_restore_rate(); 2030 generic_delay_timer_init(); 2031 2032 stm32_clk_oscillators_enable(priv); 2033 2034 /* Come back to HSI */ 2035 ret = stm32mp2_clk_switch_to_hsi(priv); 2036 if (ret != 0) { 2037 panic(); 2038 } 2039 2040 ret = stm32mp2_clk_pll_configure(priv); 2041 if (ret != 0) { 2042 panic(); 2043 } 2044 2045 /* Wait LSE ready before to use it */ 2046 ret = stm32_clk_oscillators_wait_lse_ready(priv); 2047 if (ret != 0) { 2048 panic(); 2049 } 2050 2051 ret = stm32mp2_clk_flexgen_configure(priv); 2052 if (ret != 0) { 2053 panic(); 2054 } 2055 2056 ret = stm32_clk_bus_configure(priv); 2057 if (ret != 0) { 2058 panic(); 2059 } 2060 2061 ret = stm32_clk_kernel_configure(priv); 2062 if (ret != 0) { 2063 panic(); 2064 } 2065 2066 return 0; 2067 } 2068 2069 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, 2070 struct stm32_osci_dt_cfg *osci) 2071 { 2072 int subnode = 0; 2073 2074 /* Default value oscillator not found, freq=0 */ 2075 osci->freq = 0; 2076 2077 fdt_for_each_subnode(subnode, fdt, node) { 2078 const char *cchar = NULL; 2079 const fdt32_t *cuint = NULL; 2080 int ret = 0; 2081 2082 cchar = fdt_get_name(fdt, subnode, &ret); 2083 if (cchar == NULL) { 2084 return ret; 2085 } 2086 2087 if (strncmp(cchar, name, (size_t)ret) || 2088 fdt_get_status(subnode) == DT_DISABLED) { 2089 continue; 2090 } 2091 2092 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 2093 if (cuint == NULL) { 2094 return ret; 2095 } 2096 2097 osci->freq = fdt32_to_cpu(*cuint); 2098 2099 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { 2100 osci->bypass = true; 2101 } 2102 2103 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { 2104 osci->digbyp = true; 2105 } 2106 2107 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { 2108 osci->css = true; 2109 } 2110 2111 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); 2112 2113 return 0; 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) 2120 { 2121 int fdt_err = 0; 2122 uint32_t i = 0; 2123 int node = 0; 2124 2125 node = fdt_path_offset(fdt, "/clocks"); 2126 if (node < 0) { 2127 return -FDT_ERR_NOTFOUND; 2128 } 2129 2130 for (i = 0; i < pdata->nosci; i++) { 2131 const char *name = NULL; 2132 2133 name = clk_stm32_get_oscillator_name((enum stm32_osc)i); 2134 if (name == NULL) { 2135 continue; 2136 } 2137 2138 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); 2139 if (fdt_err < 0) { 2140 panic(); 2141 } 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2148 { 2149 const fdt32_t *cuint = NULL; 2150 int subnode_pll = 0; 2151 uint32_t val = 0; 2152 int err = 0; 2153 2154 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2155 if (!cuint) { 2156 return -FDT_ERR_NOTFOUND; 2157 } 2158 2159 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2160 if (subnode_pll < 0) { 2161 return -FDT_ERR_NOTFOUND; 2162 } 2163 2164 err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg); 2165 if (err != 0) { 2166 return err; 2167 } 2168 2169 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg); 2170 2171 pll->csg_enabled = (err == 0); 2172 2173 if (err == -FDT_ERR_NOTFOUND) { 2174 err = 0; 2175 } 2176 2177 if (err != 0) { 2178 return err; 2179 } 2180 2181 pll->enabled = true; 2182 2183 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); 2184 2185 pll->src = UINT32_MAX; 2186 2187 err = fdt_read_uint32(fdt, subnode_pll, "src", &val); 2188 if (err == 0) { 2189 pll->src = val; 2190 } 2191 2192 return 0; 2193 } 2194 2195 #define RCC_PLL_NAME_SIZE 12 2196 2197 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2198 { 2199 unsigned int i = 0; 2200 2201 for (i = _PLL1; i < pdata->npll; i++) { 2202 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 2203 char name[RCC_PLL_NAME_SIZE]; 2204 int subnode = 0; 2205 int err = 0; 2206 2207 snprintf(name, sizeof(name), "st,pll-%u", i + 1); 2208 2209 subnode = fdt_subnode_offset(fdt, node, name); 2210 if (!fdt_check_node(subnode)) { 2211 continue; 2212 } 2213 2214 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2215 if (err != 0) { 2216 panic(); 2217 } 2218 } 2219 2220 return 0; 2221 } 2222 2223 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2224 { 2225 void *fdt = NULL; 2226 int node; 2227 int err; 2228 2229 if (fdt_get_address(&fdt) == 0) { 2230 return -ENOENT; 2231 } 2232 2233 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2234 if (node < 0) { 2235 panic(); 2236 } 2237 2238 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); 2239 if (err != 0) { 2240 return err; 2241 } 2242 2243 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2244 if (err != 0) { 2245 return err; 2246 } 2247 2248 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,busclk", pdata->busclk, &pdata->nbusclk); 2249 if (err != 0) { 2250 return err; 2251 } 2252 2253 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,flexgen", pdata->flexgen, 2254 &pdata->nflexgen); 2255 if (err != 0) { 2256 return err; 2257 } 2258 2259 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,kerclk", pdata->kernelclk, 2260 &pdata->nkernelclk); 2261 if (err != 0) { 2262 return err; 2263 } 2264 2265 return 0; 2266 } 2267 #endif /* IMAGE_BL2 */ 2268 2269 static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR]; 2270 2271 static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB]; 2272 2273 #define DT_FLEXGEN_CLK_MAX 64 2274 static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX]; 2275 2276 #define DT_BUS_CLK_MAX 6 2277 static uint32_t mp25_busclk[DT_BUS_CLK_MAX]; 2278 2279 #define DT_KERNEL_CLK_MAX 20 2280 static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX]; 2281 2282 static struct stm32_clk_platdata stm32mp25_pdata = { 2283 .osci = mp25_osci, 2284 .nosci = NB_OSCILLATOR, 2285 .pll = mp25_pll, 2286 .npll = _PLL_NB, 2287 .flexgen = mp25_flexgen, 2288 .nflexgen = DT_FLEXGEN_CLK_MAX, 2289 .busclk = mp25_busclk, 2290 .nbusclk = DT_BUS_CLK_MAX, 2291 .kernelclk = mp25_kernelclk, 2292 .nkernelclk = DT_KERNEL_CLK_MAX, 2293 }; 2294 2295 static uint8_t refcounts_mp25[CK_LAST]; 2296 2297 static struct stm32_clk_priv stm32mp25_clock_data = { 2298 .base = RCC_BASE, 2299 .num = ARRAY_SIZE(stm32mp25_clk), 2300 .clks = stm32mp25_clk, 2301 .parents = parent_mp25, 2302 .nb_parents = ARRAY_SIZE(parent_mp25), 2303 .gates = gates_mp25, 2304 .nb_gates = ARRAY_SIZE(gates_mp25), 2305 .div = dividers_mp25, 2306 .nb_div = ARRAY_SIZE(dividers_mp25), 2307 .osci_data = stm32mp25_osc_data, 2308 .nb_osci_data = ARRAY_SIZE(stm32mp25_osc_data), 2309 .gate_refcounts = refcounts_mp25, 2310 .pdata = &stm32mp25_pdata, 2311 .ops_array = ops_array_mp25, 2312 }; 2313 2314 int stm32mp2_clk_init(void) 2315 { 2316 uintptr_t base = RCC_BASE; 2317 int ret; 2318 2319 #ifdef IMAGE_BL2 2320 ret = stm32_clk_parse_fdt(&stm32mp25_pdata); 2321 if (ret != 0) { 2322 return ret; 2323 } 2324 #endif 2325 2326 ret = clk_stm32_init(&stm32mp25_clock_data, base); 2327 if (ret != 0) { 2328 return ret; 2329 } 2330 2331 #ifdef IMAGE_BL2 2332 ret = stm32mp2_init_clock_tree(); 2333 if (ret != 0) { 2334 return ret; 2335 } 2336 2337 clk_stm32_enable_critical_clocks(); 2338 #endif 2339 2340 return 0; 2341 } 2342 2343 int stm32mp2_pll1_disable(void) 2344 { 2345 #ifdef IMAGE_BL2 2346 return -EPERM; 2347 #else 2348 uintptr_t a35_ss_address = A35SSC_BASE; 2349 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE; 2350 2351 stm32mp2_a35_ss_on_hsi(); 2352 2353 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD); 2354 2355 return 0; 2356 #endif 2357 } 2358