1 /*
2 * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stddef.h>
8 #include <stdint.h>
9
10 #include <drivers/console.h>
11 #include <lib/mmio.h>
12 #include <lib/utils_def.h>
13 #include "scif.h"
14
15 #include "rcar_def.h"
16
17 /* CPG */
18 #define CPG_BASE 0xE6150000UL
19 #define CPG_CPGWPR (CPG_BASE + 0x0000UL)
20 #define CPG_CPGWPCR (CPG_BASE + 0x0004UL)
21 #define CPG_MSTPCR5 (CPG_BASE + 0x2D14UL)
22 #define CPG_MSTPSR5 (CPG_BASE + 0x2E14UL)
23 #define CPG_MSTPSR5_HSCIF0 BIT(14)
24 #define CPG_MSTPCR7 (CPG_BASE + 0x2D1CUL)
25 #define CPG_MSTPSR7 (CPG_BASE + 0x2E1CUL)
26 #define CPG_MSTPSR7_SCIF0 BIT(2)
27 #define CPG_MSTPSR7_SCIF3 BIT(4)
28
29 /* RST */
30 #define RST_BASE (0xE6160000UL + (RCAR_DOMAIN * 0x4000UL))
31 #define RST_MODEMR0 RST_BASE
32 #define RST_MODEMR1 (RST_BASE + 4UL)
33 #define RST_MODEMR0_MD31 BIT(31)
34 #define RST_MODEMR1_MD32 BIT(0)
35
36 /* SCIF/HSCIF */
37 #define SCIF0_BASE 0xE6E60000UL
38 #define SCIF3_BASE 0xE6C50000UL
39 #define HSCIF0_BASE 0xE6540000UL
40
41 /* SCIF */
42 #if (RCAR_LSI == RCAR_S4) /* S4 */
43 #define SCIF_BASE SCIF3_BASE
44 #define CPG_MSTPSR7_BIT CPG_MSTPSR7_SCIF3
45 #else
46 #define SCIF_BASE SCIF0_BASE
47 #define CPG_MSTPSR7_BIT CPG_MSTPSR7_SCIF0
48 #endif
49 #define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
50 #define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */
51
52 /* HSCIF */
53 #define HSCIF_BASE HSCIF0_BASE
54 #define HSCIF_HSFTDR (HSCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
55 #define HSCIF_HSFSR (HSCIF_BASE + 0x0010U) /* 16 Serial status register */
56
57 /* Mode */
58 #define MODEMR_SCIF_DLMODE 0U
59 #define MODEMR_HSCIF_DLMODE_921600 1U
60 #define MODEMR_HSCIF_DLMODE_1843200 2U
61 #define MODEMR_HSCIF_DLMODE_3000000 3U
62
console_rcar_init(uintptr_t base_addr,uint32_t uart_clk,uint32_t baud_rate)63 int console_rcar_init(uintptr_t base_addr, uint32_t uart_clk,
64 uint32_t baud_rate)
65 {
66 uint32_t modemr, mstpcr, mstpsr, mstpbit;
67
68 modemr = ((mmio_read_32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U) |
69 ((mmio_read_32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
70
71 if (modemr == MODEMR_HSCIF_DLMODE_3000000 ||
72 modemr == MODEMR_HSCIF_DLMODE_1843200 ||
73 modemr == MODEMR_HSCIF_DLMODE_921600) {
74 mstpcr = CPG_MSTPCR5;
75 mstpsr = CPG_MSTPSR5;
76 mstpbit = CPG_MSTPSR5_HSCIF0;
77 scif_console_set_regs(HSCIF_HSFSR, HSCIF_HSFTDR);
78 } else {
79 mstpcr = CPG_MSTPCR7;
80 mstpsr = CPG_MSTPSR7;
81 mstpbit = CPG_MSTPSR7_BIT;
82 scif_console_set_regs(SCIF_SCFSR, SCIF_SCFTDR);
83 }
84
85 /* Turn SCIF/HSCIF clock ON. */
86 mmio_clrbits_32(mstpcr, mstpbit);
87 while (mmio_read_32(mstpsr) & mstpbit)
88 ;
89
90 return 1;
91 }
92