1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/platform.h> 17 18 #include "iic_dvfs.h" 19 #include "micro_delay.h" 20 #include "pwrc.h" 21 #include "rcar_def.h" 22 #include "rcar_private.h" 23 #include "cpg_registers.h" 24 25 /* 26 * Someday there will be a generic power controller api. At the moment each 27 * platform has its own pwrc so just exporting functions should be acceptable. 28 */ 29 RCAR_INSTANTIATE_LOCK 30 31 #define WUP_IRQ_SHIFT (0U) 32 #define WUP_FIQ_SHIFT (8U) 33 #define WUP_CSD_SHIFT (16U) 34 #define BIT_SOFTRESET (1U << 15) 35 #define BIT_CA53_SCU (1U << 21) 36 #define BIT_CA57_SCU (1U << 12) 37 #define REQ_RESUME (1U << 1) 38 #define REQ_OFF (1U << 0) 39 #define STATUS_PWRUP (1U << 4) 40 #define STATUS_PWRDOWN (1U << 0) 41 #define STATE_CA57_CPU (27U) 42 #define STATE_CA53_CPU (22U) 43 #define MODE_L2_DOWN (0x00000002U) 44 #define CPU_PWR_OFF (0x00000003U) 45 #define RCAR_PSTR_MASK (0x00000003U) 46 #define ST_ALL_STANDBY (0x00003333U) 47 #define SYSCEXTMASK_EXTMSK0 (0x00000001U) 48 /* Suspend to ram */ 49 #define DBSC4_REG_BASE (0xE6790000U) 50 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U) 51 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U) 52 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U) 53 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U) 54 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U) 55 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U) 56 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U) 57 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U) 58 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U) 59 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U) 60 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U) 61 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U) 62 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U) 63 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U) 64 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U) 65 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0)) 66 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0)) 67 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U) 68 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U) 69 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U) 70 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U) 71 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U) 72 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U) 73 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U) 74 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U) 75 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U) 76 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U) 77 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U) 78 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U) 79 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U) 80 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU) 81 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU) 82 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U) 83 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U) 84 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U) 85 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U) 86 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U) 87 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU) 88 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU) 89 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU) 90 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU) 91 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU) 92 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU) 93 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U) 94 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U) 95 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U) 96 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U) 97 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U) 98 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U) 99 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U) 100 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U) 101 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U) 102 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U) 103 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U) 104 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U) 105 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U) 106 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U) 107 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U) 108 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U) 109 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U) 110 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U) 111 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U) 112 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U) 113 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U) 114 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U) 115 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U) 116 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U) 117 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U) 118 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U) 119 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U) 120 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U) 121 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U) 122 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U) 123 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U) 124 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U) 125 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U) 126 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U) 127 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U) 128 #define RST_BASE (0xE6160000U) 129 #define RST_MODEMR (RST_BASE + 0x0060U) 130 #define RST_MODEMR_BIT0 (0x00000001U) 131 132 #define RCAR_CNTCR_OFF (0x00U) 133 #define RCAR_CNTCVL_OFF (0x08U) 134 #define RCAR_CNTCVU_OFF (0x0CU) 135 #define RCAR_CNTFID_OFF (0x20U) 136 137 #define RCAR_CNTCR_EN ((uint32_t)1U << 0U) 138 #define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U) 139 140 #if PMIC_ROHM_BD9571 141 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4)) 142 #define PMIC_BKUP_MODE_CNT (0x20U) 143 #define PMIC_QLLM_CNT (0x27U) 144 #define PMIC_RETRY_MAX (100U) 145 #endif /* PMIC_ROHM_BD9571 */ 146 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0) 147 #define RCAR_CA53CPU_NUM_MAX (4U) 148 #define RCAR_CA57CPU_NUM_MAX (4U) 149 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57) 150 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57) 151 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53) 152 153 #ifndef __ASSEMBLER__ 154 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START); 155 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END); 156 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START); 157 #endif 158 159 uint32_t rcar_pwrc_status(u_register_t mpidr) 160 { 161 uint32_t ret = 0; 162 uint64_t cm, cpu; 163 uint32_t reg; 164 uint32_t c; 165 166 rcar_lock_get(); 167 168 c = rcar_pwrc_get_cluster(); 169 cm = mpidr & MPIDR_CLUSTER_MASK; 170 171 if (!IS_A53A57(c) && cm != 0) { 172 ret = RCAR_INVALID; 173 goto done; 174 } 175 176 reg = mmio_read_32(RCAR_PRR); 177 cpu = mpidr & MPIDR_CPU_MASK; 178 179 if (IS_CA53(c)) 180 if (reg & (1 << (STATE_CA53_CPU + cpu))) 181 ret = RCAR_INVALID; 182 if (IS_CA57(c)) 183 if (reg & (1 << (STATE_CA57_CPU + cpu))) 184 ret = RCAR_INVALID; 185 done: 186 rcar_lock_release(); 187 188 return ret; 189 } 190 191 static void scu_power_up(u_register_t mpidr) 192 { 193 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer; 194 uint32_t c, sysc_reg_bit; 195 uint32_t lsi_product; 196 uint32_t lsi_cut; 197 198 c = rcar_pwrc_get_mpidr_cluster(mpidr); 199 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR; 200 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU; 201 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3; 202 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3; 203 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3; 204 205 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0) 206 return; 207 208 if (mmio_read_32(reg_cpumcr) != 0) 209 mmio_write_32(reg_cpumcr, 0); 210 211 lsi_product = mmio_read_32((uintptr_t)RCAR_PRR); 212 lsi_cut = lsi_product & PRR_CUT_MASK; 213 lsi_product &= PRR_PRODUCT_MASK; 214 215 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || 216 lsi_product == PRR_PRODUCT_H3 || 217 lsi_product == PRR_PRODUCT_M3N || 218 lsi_product == PRR_PRODUCT_E3) { 219 mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); 220 } 221 222 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit); 223 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit); 224 225 do { 226 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0) 227 ; 228 mmio_write_32(reg_pwron, 1); 229 } while (mmio_read_32(reg_pwrer) & 1); 230 231 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0) 232 ; 233 mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit); 234 235 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || 236 lsi_product == PRR_PRODUCT_H3 || 237 lsi_product == PRR_PRODUCT_M3N || 238 lsi_product == PRR_PRODUCT_E3) { 239 mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); 240 } 241 242 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0) 243 ; 244 } 245 246 void rcar_pwrc_cpuon(u_register_t mpidr) 247 { 248 uint32_t res_data, on_data; 249 uintptr_t res_reg, on_reg; 250 uint32_t limit, c; 251 uint64_t cpu; 252 253 rcar_lock_get(); 254 255 c = rcar_pwrc_get_mpidr_cluster(mpidr); 256 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT; 257 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR; 258 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000; 259 260 res_data = mmio_read_32(res_reg) | limit; 261 scu_power_up(mpidr); 262 cpu = mpidr & MPIDR_CPU_MASK; 263 on_data = 1 << cpu; 264 mmio_write_32(CPG_CPGWPR, ~on_data); 265 mmio_write_32(on_reg, on_data); 266 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu)))); 267 268 rcar_lock_release(); 269 } 270 271 void rcar_pwrc_cpuoff(u_register_t mpidr) 272 { 273 uint32_t c; 274 uintptr_t reg; 275 uint64_t cpu; 276 277 rcar_lock_get(); 278 279 cpu = mpidr & MPIDR_CPU_MASK; 280 c = rcar_pwrc_get_mpidr_cluster(mpidr); 281 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR; 282 283 if (read_mpidr_el1() != mpidr) 284 panic(); 285 286 mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF); 287 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF); 288 289 rcar_lock_release(); 290 } 291 292 void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr) 293 { 294 uint32_t c, shift_irq, shift_fiq; 295 uintptr_t reg; 296 uint64_t cpu; 297 298 rcar_lock_get(); 299 300 cpu = mpidr & MPIDR_CPU_MASK; 301 c = rcar_pwrc_get_mpidr_cluster(mpidr); 302 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57; 303 304 shift_irq = WUP_IRQ_SHIFT + cpu; 305 shift_fiq = WUP_FIQ_SHIFT + cpu; 306 307 mmio_clrbits_32(reg, ((uint32_t) 1 << shift_irq) | 308 ((uint32_t) 1 << shift_fiq)); 309 rcar_lock_release(); 310 } 311 312 void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr) 313 { 314 uint32_t c, shift_irq, shift_fiq; 315 uintptr_t reg; 316 uint64_t cpu; 317 318 rcar_lock_get(); 319 320 cpu = mpidr & MPIDR_CPU_MASK; 321 c = rcar_pwrc_get_mpidr_cluster(mpidr); 322 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57; 323 324 shift_irq = WUP_IRQ_SHIFT + cpu; 325 shift_fiq = WUP_FIQ_SHIFT + cpu; 326 327 mmio_setbits_32(reg, ((uint32_t) 1 << shift_irq) | 328 ((uint32_t) 1 << shift_fiq)); 329 rcar_lock_release(); 330 } 331 332 void rcar_pwrc_all_disable_interrupt_wakeup(void) 333 { 334 uint32_t cpu_num; 335 u_register_t cl, cpu, mpidr; 336 337 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = { 338 RCAR_CLUSTER_CA57, 339 RCAR_CLUSTER_CA53 340 }; 341 342 for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) { 343 cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]); 344 for (cpu = 0; cpu < cpu_num; cpu++) { 345 mpidr = ((cl << MPIDR_AFFINITY_BITS) | cpu); 346 if (mpidr == rcar_boot_mpidr) { 347 rcar_pwrc_enable_interrupt_wakeup(mpidr); 348 } else { 349 rcar_pwrc_disable_interrupt_wakeup(mpidr); 350 } 351 } 352 } 353 } 354 355 void rcar_pwrc_clusteroff(u_register_t mpidr) 356 { 357 uint32_t c, product, cut, reg; 358 uintptr_t dst; 359 360 rcar_lock_get(); 361 362 reg = mmio_read_32(RCAR_PRR); 363 product = reg & PRR_PRODUCT_MASK; 364 cut = reg & PRR_CUT_MASK; 365 366 c = rcar_pwrc_get_mpidr_cluster(mpidr); 367 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR; 368 369 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) { 370 goto done; 371 } 372 373 if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) { 374 goto done; 375 } 376 377 /* all of the CPUs in the cluster is in the CoreStandby mode */ 378 mmio_write_32(dst, MODE_L2_DOWN); 379 done: 380 rcar_lock_release(); 381 } 382 383 static uint64_t rcar_pwrc_saved_cntpct_el0; 384 static uint32_t rcar_pwrc_saved_cntfid; 385 386 #if RCAR_SYSTEM_SUSPEND 387 static void rcar_pwrc_save_timer_state(void) 388 { 389 rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0(); 390 391 rcar_pwrc_saved_cntfid = 392 mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF)); 393 } 394 #endif /* RCAR_SYSTEM_SUSPEND */ 395 396 void rcar_pwrc_restore_timer_state(void) 397 { 398 /* Stop timer before restoring counter value */ 399 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U); 400 401 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF), 402 (uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU)); 403 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF), 404 (uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U)); 405 406 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF), 407 rcar_pwrc_saved_cntfid); 408 409 /* Start generic timer back */ 410 write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2()); 411 412 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 413 (RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN)); 414 } 415 416 #if !PMIC_ROHM_BD9571 417 void rcar_pwrc_system_reset(void) 418 { 419 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET); 420 } 421 #endif /* PMIC_ROHM_BD9571 */ 422 423 #define RST_CA53_CPU0_BARH (0xE6160080U) 424 #define RST_CA53_CPU0_BARL (0xE6160084U) 425 #define RST_CA57_CPU0_BARH (0xE61600C0U) 426 #define RST_CA57_CPU0_BARL (0xE61600C4U) 427 428 void rcar_pwrc_setup(void) 429 { 430 uintptr_t rst_barh; 431 uintptr_t rst_barl; 432 uint32_t i, j; 433 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF; 434 435 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = { 436 RCAR_CLUSTER_CA53, 437 RCAR_CLUSTER_CA57 438 }; 439 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = { 440 RST_CA53_CPU0_BARH, 441 RST_CA57_CPU0_BARH 442 }; 443 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = { 444 RST_CA53_CPU0_BARL, 445 RST_CA57_CPU0_BARL 446 }; 447 448 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) { 449 rst_barh = reg_barh[i]; 450 rst_barl = reg_barl[i]; 451 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) { 452 mmio_write_32(rst_barh, 0); 453 mmio_write_32(rst_barl, (uint32_t) reset); 454 rst_barh += 0x10; 455 rst_barl += 0x10; 456 } 457 } 458 459 rcar_lock_init(); 460 } 461 462 #if RCAR_SYSTEM_SUSPEND 463 #define DBCAM_FLUSH(__bit) \ 464 do { \ 465 ; \ 466 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0)) 467 468 469 static void __attribute__ ((section(".system_ram"))) 470 rcar_pwrc_set_self_refresh(void) 471 { 472 uint32_t reg = mmio_read_32(RCAR_PRR); 473 uint32_t cut, product; 474 475 product = reg & PRR_PRODUCT_MASK; 476 cut = reg & PRR_CUT_MASK; 477 478 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) { 479 goto self_refresh; 480 } 481 482 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) { 483 goto self_refresh; 484 } 485 486 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); 487 488 self_refresh: 489 490 /* DFI_PHYMSTR_ACK setting */ 491 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF, 492 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) & 493 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN)); 494 495 /* Set the Self-Refresh mode */ 496 mmio_write_32(DBSC4_REG_DBACEN, 0); 497 498 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) 499 rcar_micro_delay(100); 500 else if (product == PRR_PRODUCT_H3) { 501 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 502 DBCAM_FLUSH(0); 503 DBCAM_FLUSH(1); 504 DBCAM_FLUSH(2); 505 DBCAM_FLUSH(3); 506 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 507 } else if (product == PRR_PRODUCT_M3) { 508 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 509 DBCAM_FLUSH(0); 510 DBCAM_FLUSH(1); 511 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 512 } else { 513 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 514 DBCAM_FLUSH(0); 515 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 516 } 517 518 /* Set the SDRAM calibration configuration register */ 519 mmio_write_32(DBSC4_REG_DBCALCNF, 0); 520 521 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL | 522 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL; 523 mmio_write_32(DBSC4_REG_DBCMD, reg); 524 while (mmio_read_32(DBSC4_REG_DBWAIT)) 525 ; 526 527 /* Self-Refresh entry command */ 528 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL | 529 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 530 mmio_write_32(DBSC4_REG_DBCMD, reg); 531 while (mmio_read_32(DBSC4_REG_DBWAIT)) 532 ; 533 534 /* Mode Register Write command. (ODT disabled) */ 535 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL | 536 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC; 537 mmio_write_32(DBSC4_REG_DBCMD, reg); 538 while (mmio_read_32(DBSC4_REG_DBWAIT)) 539 ; 540 541 /* Power Down entry command */ 542 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL | 543 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 544 mmio_write_32(DBSC4_REG_DBCMD, reg); 545 while (mmio_read_32(DBSC4_REG_DBWAIT)) 546 ; 547 548 /* Set the auto-refresh enable register */ 549 mmio_write_32(DBSC4_REG_DBRFEN, 0U); 550 rcar_micro_delay(1U); 551 552 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) 553 return; 554 555 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) 556 return; 557 558 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); 559 } 560 561 static void __attribute__ ((section(".system_ram"))) 562 rcar_pwrc_set_self_refresh_e3(void) 563 { 564 uint32_t ddr_md; 565 uint32_t reg; 566 567 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0; 568 569 /* Write enable */ 570 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); 571 mmio_write_32(DBSC4_REG_DBACEN, 0); 572 DBCAM_FLUSH(0); 573 574 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL | 575 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL; 576 mmio_write_32(DBSC4_REG_DBCMD, reg); 577 while (mmio_read_32(DBSC4_REG_DBWAIT)) 578 ; 579 580 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL | 581 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 582 mmio_write_32(DBSC4_REG_DBCMD, reg); 583 while (mmio_read_32(DBSC4_REG_DBWAIT)) 584 ; 585 586 /* 587 * Set the auto-refresh enable register 588 * Set the ARFEN bit to 0 in the DBRFEN 589 */ 590 mmio_write_32(DBSC4_REG_DBRFEN, 0); 591 592 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS); 593 594 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0); 595 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0); 596 597 /* DDR_DXCCR */ 598 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR); 599 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR); 600 601 /* DDR_PGCR1 */ 602 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1); 603 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1); 604 605 /* DDR_ACIOCR1 */ 606 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1); 607 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1); 608 609 /* DDR_ACIOCR3 */ 610 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3); 611 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3); 612 613 /* DDR_ACIOCR5 */ 614 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5); 615 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5); 616 617 /* DDR_DX0GCR2 */ 618 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2); 619 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2); 620 621 /* DDR_DX1GCR2 */ 622 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2); 623 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2); 624 625 /* DDR_DX2GCR2 */ 626 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2); 627 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2); 628 629 /* DDR_DX3GCR2 */ 630 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2); 631 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2); 632 633 /* DDR_ZQCR */ 634 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR); 635 636 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ? 637 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 : 638 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1); 639 640 /* DDR_DX0GCR0 */ 641 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0); 642 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0); 643 644 /* DDR_DX1GCR0 */ 645 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0); 646 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0); 647 648 /* DDR_DX2GCR0 */ 649 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0); 650 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0); 651 652 /* DDR_DX3GCR0 */ 653 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0); 654 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0); 655 656 /* DDR_DX0GCR1 */ 657 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1); 658 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1); 659 660 /* DDR_DX1GCR1 */ 661 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1); 662 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1); 663 664 /* DDR_DX2GCR1 */ 665 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1); 666 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1); 667 668 /* DDR_DX3GCR1 */ 669 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1); 670 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1); 671 672 /* DDR_DX0GCR3 */ 673 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3); 674 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3); 675 676 /* DDR_DX1GCR3 */ 677 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3); 678 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3); 679 680 /* DDR_DX2GCR3 */ 681 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3); 682 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3); 683 684 /* DDR_DX3GCR3 */ 685 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3); 686 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3); 687 688 /* Write disable */ 689 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); 690 } 691 692 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline)) 693 rcar_pwrc_go_suspend_to_ram(void) 694 { 695 #if PMIC_ROHM_BD9571 696 int32_t rc = -1, qllm = -1; 697 uint8_t mode; 698 uint32_t i; 699 #endif 700 uint32_t reg, product; 701 702 reg = mmio_read_32(RCAR_PRR); 703 product = reg & PRR_PRODUCT_MASK; 704 705 if (product != PRR_PRODUCT_E3) 706 rcar_pwrc_set_self_refresh(); 707 else 708 rcar_pwrc_set_self_refresh_e3(); 709 710 #if PMIC_ROHM_BD9571 711 /* Set QLLM Cnt Disable */ 712 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++) 713 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0); 714 715 /* Set trigger of power down to PMIV */ 716 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) { 717 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode); 718 if (rc == 0) { 719 mode |= BIT_BKUP_CTRL_OUT; 720 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode); 721 } 722 } 723 #endif 724 wfi(); 725 726 while (1) 727 ; 728 } 729 730 void rcar_pwrc_set_suspend_to_ram(void) 731 { 732 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram; 733 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE + 734 DEVICE_SRAM_STACK_SIZE); 735 uint32_t sctlr; 736 737 rcar_pwrc_save_timer_state(); 738 739 /* disable MMU */ 740 sctlr = (uint32_t) read_sctlr_el3(); 741 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT; 742 write_sctlr_el3((uint64_t) sctlr); 743 744 rcar_pwrc_switch_stack(jump, stack, NULL); 745 } 746 747 void rcar_pwrc_init_suspend_to_ram(void) 748 { 749 #if PMIC_ROHM_BD9571 750 uint8_t mode; 751 752 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) 753 panic(); 754 755 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT); 756 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) 757 panic(); 758 #endif 759 } 760 761 void rcar_pwrc_suspend_to_ram(void) 762 { 763 #if RCAR_SYSTEM_RESET_KEEPON_DDR 764 int32_t error; 765 766 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0); 767 if (error) { 768 ERROR("Failed send KEEP10 init ret=%d\n", error); 769 return; 770 } 771 #endif 772 rcar_pwrc_set_suspend_to_ram(); 773 } 774 #endif 775 776 void rcar_pwrc_code_copy_to_system_ram(void) 777 { 778 int ret __attribute__ ((unused)); /* in assert */ 779 uint32_t attr; 780 struct device_sram_t { 781 uintptr_t base; 782 size_t len; 783 } sram = { 784 .base = (uintptr_t) DEVICE_SRAM_BASE, 785 .len = DEVICE_SRAM_SIZE, 786 }; 787 struct ddr_code_t { 788 void *base; 789 size_t len; 790 } code = { 791 .base = (void *) SRAM_COPY_START, 792 .len = SYSTEM_RAM_END - SYSTEM_RAM_START, 793 }; 794 795 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER; 796 ret = xlat_change_mem_attributes(sram.base, sram.len, attr); 797 assert(ret == 0); 798 799 memcpy((void *)sram.base, code.base, code.len); 800 flush_dcache_range((uint64_t) sram.base, code.len); 801 802 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE; 803 ret = xlat_change_mem_attributes(sram.base, sram.len, attr); 804 assert(ret == 0); 805 806 /* Invalidate instruction cache */ 807 plat_invalidate_icache(); 808 dsb(); 809 isb(); 810 } 811 812 uint32_t rcar_pwrc_get_cluster(void) 813 { 814 uint32_t reg; 815 816 reg = mmio_read_32(RCAR_PRR); 817 818 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX))) 819 return RCAR_CLUSTER_CA57; 820 821 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX))) 822 return RCAR_CLUSTER_CA53; 823 824 return RCAR_CLUSTER_A53A57; 825 } 826 827 uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr) 828 { 829 uint32_t c = rcar_pwrc_get_cluster(); 830 831 if (IS_A53A57(c)) { 832 if (mpidr & MPIDR_CLUSTER_MASK) 833 return RCAR_CLUSTER_CA53; 834 835 return RCAR_CLUSTER_CA57; 836 } 837 838 return c; 839 } 840 841 #if RCAR_LSI == RCAR_D3 842 uint32_t rcar_pwrc_get_cpu_num(uint32_t c) 843 { 844 return 1; 845 } 846 #else 847 uint32_t rcar_pwrc_get_cpu_num(uint32_t c) 848 { 849 uint32_t reg = mmio_read_32(RCAR_PRR); 850 uint32_t count = 0, i; 851 852 if (IS_A53A57(c) || IS_CA53(c)) { 853 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX))) 854 goto count_ca57; 855 856 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) { 857 if (reg & (1 << (STATE_CA53_CPU + i))) 858 continue; 859 count++; 860 } 861 } 862 863 count_ca57: 864 if (IS_A53A57(c) || IS_CA57(c)) { 865 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX))) 866 goto done; 867 868 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) { 869 if (reg & (1 << (STATE_CA57_CPU + i))) 870 continue; 871 count++; 872 } 873 } 874 875 done: 876 return count; 877 } 878 #endif 879 880 int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr) 881 { 882 uint64_t i; 883 uint64_t j; 884 uint64_t cpu_count; 885 uintptr_t reg_PSTR; 886 uint32_t status; 887 uint64_t my_cpu; 888 int32_t rtn; 889 uint32_t my_cluster_type; 890 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = { 891 RCAR_CLUSTER_CA53, 892 RCAR_CLUSTER_CA57 893 }; 894 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = { 895 RCAR_CA53PSTR, 896 RCAR_CA57PSTR 897 }; 898 899 my_cluster_type = rcar_pwrc_get_cluster(); 900 901 rtn = 0; 902 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK)); 903 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) { 904 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]); 905 reg_PSTR = registerPSTR[i]; 906 for (j = 0U; j < cpu_count; j++) { 907 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) { 908 status = mmio_read_32(reg_PSTR) >> (j * 4U); 909 if ((status & 0x00000003U) == 0U) { 910 rtn--; 911 } 912 } 913 } 914 } 915 916 return rtn; 917 } 918