1 /*
2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <drivers/qti/sec_core/sec_core.h>
10 #include <lib/mmio.h>
11
12 #include <sec_core_defs.h>
13
qti_sec_core_remap(uintptr_t entrypoint)14 void qti_sec_core_remap(uintptr_t entrypoint)
15 {
16 mmio_write_32(APSS_SHARED_KRYO_RVBARADDR_LO_ADDR,
17 (uint32_t)(entrypoint >> 2));
18 mmio_write_32(APSS_SHARED_KRYO_RVBARADDR_HI_ADDR,
19 (uint32_t)(entrypoint >> 34));
20 }
21
22 /*
23 * ACPS: security configuration.
24 * - CPU Clock control/distribution (acc).
25 * - Global CPU Clock control/distribution (gcc)
26 * - General Purpose Timer(s) (tmr configured as general purpose)
27 * - Debug Timer (tmr configured for debug)
28 * - Watch Dog timer(s) (wdt)
29 * - System Interrupt Controller (SIC or QGIC or External)
30 * - Test Interface Controller (tic).
31 * - AHB Bus Interface and decoder (ahb).
32 * - Per CPU voltage control (avs)
33 * - Per CPU power control (spm)
34 */
qti_sec_core_init(void)35 void qti_sec_core_init(void)
36 {
37 uintptr_t addr = APSS_ALIAS_0_APC_SECURE_ADDR;
38 int i = 0;
39
40 mmio_write_32(APSS_WDT_TMR1_WDOG_SECURE_ADDR,
41 APSS_WDT_TMR1_WDOG_SECURE_RMSK);
42
43 for (i = 0; i < APSS_ALIASn_APC_SECURE_MAX_INDEX + 1; i++) {
44 mmio_write_32(addr, APSS_ALIAS_0_APC_SECURE_RMSK);
45 addr += APSS_ALIASn_APC_SECURE_OFFSET_TO_NEXT;
46 }
47
48 mmio_write_32(APSS_CL_SECURE_ADDR, APSS_CL_SECURE_RMSK);
49 mmio_write_32(APSS_BANKED_APC_SECURE_ADDR, APSS_BANKED_APC_SECURE_RMSK);
50 mmio_write_32(APSS_SHARED_SHR_SECURE_ADDR, 0x0);
51 mmio_write_32(GOLD_SAW4_SECURE_ADDR, GOLD_SAW4_SECURE_RMSK);
52 mmio_write_32(SILVER_SAW4_SECURE_ADDR, SILVER_SAW4_SECURE_RMSK);
53 mmio_write_32(APSS_PWR_APM_SECURE_ADDR, APSS_PWR_APM_SECURE_RMSK);
54 mmio_write_32(APSS_PWR_MAS_SECURE_ADDR, APSS_PWR_MAS_SECURE_RMSK);
55 mmio_write_32(GOLD_PLL_SECURE_ADDR, GOLD_PLL_SECURE_RMSK);
56 mmio_write_32(SILVER_PLL_SECURE_ADDR, SILVER_PLL_SECURE_RMSK);
57 mmio_write_32(L3_PLL_SECURE_ADDR, L3_PLL_SECURE_RMSK);
58 mmio_write_32(APSS_MISC_CLK_SECURE_ADDR, APSS_MISC_CLK_SECURE_RMSK);
59
60 dsbsy();
61 isb();
62 }
63
64