1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <s32cc-clk-drv.h> 8 #include <s32cc-clk-ids.h> 9 #include <s32cc-clk-utils.h> 10 11 #define S32CC_FXOSC_FREQ (40U * MHZ) 12 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 13 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 14 #define S32CC_A53_FREQ (1U * GHZ) 15 16 int s32cc_init_early_clks(void) 17 { 18 int ret; 19 20 s32cc_clk_register_drv(); 21 22 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 23 if (ret != 0) { 24 return ret; 25 } 26 27 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 28 if (ret != 0) { 29 return ret; 30 } 31 32 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 33 if (ret != 0) { 34 return ret; 35 } 36 37 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 38 if (ret != 0) { 39 return ret; 40 } 41 42 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 43 if (ret != 0) { 44 return ret; 45 } 46 47 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 48 if (ret != 0) { 49 return ret; 50 } 51 52 ret = clk_enable(S32CC_CLK_FXOSC); 53 if (ret != 0) { 54 return ret; 55 } 56 57 ret = clk_enable(S32CC_CLK_ARM_PLL_VCO); 58 if (ret != 0) { 59 return ret; 60 } 61 62 ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0); 63 if (ret != 0) { 64 return ret; 65 } 66 67 ret = clk_enable(S32CC_CLK_A53_CORE); 68 if (ret != 0) { 69 return ret; 70 } 71 72 return ret; 73 } 74