1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <s32cc-clk-drv.h> 8 #include <s32cc-clk-ids.h> 9 #include <s32cc-clk-utils.h> 10 11 #define S32CC_FXOSC_FREQ (40U * MHZ) 12 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 13 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 14 #define S32CC_A53_FREQ (1U * GHZ) 15 16 static int enable_fxosc_clk(void) 17 { 18 int ret; 19 20 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 21 if (ret != 0) { 22 return ret; 23 } 24 25 ret = clk_enable(S32CC_CLK_FXOSC); 26 if (ret != 0) { 27 return ret; 28 } 29 30 return ret; 31 } 32 33 static int enable_arm_pll(void) 34 { 35 int ret; 36 37 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 38 if (ret != 0) { 39 return ret; 40 } 41 42 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 43 if (ret != 0) { 44 return ret; 45 } 46 47 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 48 if (ret != 0) { 49 return ret; 50 } 51 52 ret = clk_enable(S32CC_CLK_ARM_PLL_VCO); 53 if (ret != 0) { 54 return ret; 55 } 56 57 ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0); 58 if (ret != 0) { 59 return ret; 60 } 61 62 return ret; 63 } 64 65 static int enable_a53_clk(void) 66 { 67 int ret; 68 69 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 70 if (ret != 0) { 71 return ret; 72 } 73 74 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 75 if (ret != 0) { 76 return ret; 77 } 78 79 ret = clk_enable(S32CC_CLK_A53_CORE); 80 if (ret != 0) { 81 return ret; 82 } 83 84 return ret; 85 } 86 87 int s32cc_init_early_clks(void) 88 { 89 int ret; 90 91 s32cc_clk_register_drv(); 92 93 ret = enable_fxosc_clk(); 94 if (ret != 0) { 95 return ret; 96 } 97 98 ret = enable_arm_pll(); 99 if (ret != 0) { 100 return ret; 101 } 102 103 ret = enable_a53_clk(); 104 if (ret != 0) { 105 return ret; 106 } 107 108 return ret; 109 } 110