1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <platform_def.h> 8 #include <s32cc-clk-drv.h> 9 #include <s32cc-clk-ids.h> 10 #include <s32cc-clk-utils.h> 11 12 #define S32CC_FXOSC_FREQ (40U * MHZ) 13 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 14 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 15 #define S32CC_A53_FREQ (1U * GHZ) 16 #define S32CC_XBAR_2X_FREQ (800U * MHZ) 17 #define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ) 18 #define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ 19 #define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ) 20 #define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ) 21 #define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ) 22 #define S32CC_USDHC_FREQ (400U * MHZ) 23 24 static int setup_fxosc(void) 25 { 26 int ret; 27 28 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 29 if (ret != 0) { 30 return ret; 31 } 32 33 return ret; 34 } 35 36 static int setup_arm_pll(void) 37 { 38 int ret; 39 40 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 41 if (ret != 0) { 42 return ret; 43 } 44 45 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 46 if (ret != 0) { 47 return ret; 48 } 49 50 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 51 if (ret != 0) { 52 return ret; 53 } 54 55 return ret; 56 } 57 58 static int setup_periph_pll(void) 59 { 60 int ret; 61 62 ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC); 63 if (ret != 0) { 64 return ret; 65 } 66 67 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); 68 if (ret != 0) { 69 return ret; 70 } 71 72 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); 73 if (ret != 0) { 74 return ret; 75 } 76 77 return ret; 78 } 79 80 static int enable_a53_clk(void) 81 { 82 int ret; 83 84 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 85 if (ret != 0) { 86 return ret; 87 } 88 89 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 90 if (ret != 0) { 91 return ret; 92 } 93 94 ret = clk_enable(S32CC_CLK_A53_CORE); 95 if (ret != 0) { 96 return ret; 97 } 98 99 return ret; 100 } 101 102 static int enable_xbar_clk(void) 103 { 104 int ret; 105 106 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); 107 if (ret != 0) { 108 return ret; 109 } 110 111 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); 112 if (ret != 0) { 113 return ret; 114 } 115 116 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); 117 if (ret != 0) { 118 return ret; 119 } 120 121 ret = clk_enable(S32CC_CLK_XBAR_2X); 122 if (ret != 0) { 123 return ret; 124 } 125 126 return ret; 127 } 128 129 static int enable_uart_clk(void) 130 { 131 int ret; 132 133 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3); 134 if (ret != 0) { 135 return ret; 136 } 137 138 ret = clk_enable(S32CC_CLK_LINFLEX_BAUD); 139 if (ret != 0) { 140 return ret; 141 } 142 143 return ret; 144 } 145 146 static int setup_ddr_pll(void) 147 { 148 int ret; 149 150 ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC); 151 if (ret != 0) { 152 return ret; 153 } 154 155 ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL); 156 if (ret != 0) { 157 return ret; 158 } 159 160 ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL); 161 if (ret != 0) { 162 return ret; 163 } 164 165 return ret; 166 } 167 168 static int enable_ddr_clk(void) 169 { 170 int ret; 171 172 ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0); 173 if (ret != 0) { 174 return ret; 175 } 176 177 ret = clk_enable(S32CC_CLK_DDR); 178 if (ret != 0) { 179 return ret; 180 } 181 182 return ret; 183 } 184 185 static int enable_usdhc_clk(void) 186 { 187 int ret; 188 189 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX14, 190 S32CC_CLK_PERIPH_PLL_DFS3); 191 if (ret != 0) { 192 return ret; 193 } 194 195 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_DFS3, 196 S32CC_PERIPH_DFS_PHI3_FREQ, NULL); 197 if (ret != 0) { 198 return ret; 199 } 200 201 ret = clk_set_rate(S32CC_CLK_USDHC, S32CC_USDHC_FREQ, NULL); 202 if (ret != 0) { 203 return ret; 204 } 205 206 ret = clk_enable(S32CC_CLK_USDHC); 207 if (ret != 0) { 208 return ret; 209 } 210 211 return ret; 212 } 213 214 int s32cc_init_core_clocks(void) 215 { 216 int ret; 217 218 ret = s32cc_clk_register_drv(false); 219 if (ret != 0) { 220 return ret; 221 } 222 223 ret = setup_fxosc(); 224 if (ret != 0) { 225 return ret; 226 } 227 228 ret = setup_arm_pll(); 229 if (ret != 0) { 230 return ret; 231 } 232 233 ret = enable_a53_clk(); 234 if (ret != 0) { 235 return ret; 236 } 237 238 ret = enable_xbar_clk(); 239 if (ret != 0) { 240 return ret; 241 } 242 243 return ret; 244 } 245 246 int s32cc_init_early_clks(void) 247 { 248 int ret; 249 250 ret = s32cc_clk_register_drv(true); 251 if (ret != 0) { 252 return ret; 253 } 254 255 ret = setup_periph_pll(); 256 if (ret != 0) { 257 return ret; 258 } 259 260 ret = enable_uart_clk(); 261 if (ret != 0) { 262 return ret; 263 } 264 265 ret = setup_ddr_pll(); 266 if (ret != 0) { 267 return ret; 268 } 269 270 ret = enable_ddr_clk(); 271 if (ret != 0) { 272 return ret; 273 } 274 275 ret = enable_usdhc_clk(); 276 if (ret != 0) { 277 return ret; 278 } 279 280 return ret; 281 } 282