1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 #include <plat_marvell.h> 18 19 #include "phy-comphy-3700.h" 20 #include "phy-comphy-common.h" 21 22 /* 23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 24 * Linux is up to 0x178 so none will access it from Linux in runtime 25 * concurrently. 26 */ 27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 28 29 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 32 33 struct sgmii_phy_init_data_fix { 34 uint16_t addr; 35 uint16_t value; 36 }; 37 38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 39 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 46 {0x104, 0x0C10} 47 }; 48 49 /* 40M1G25 mode init data */ 50 static uint16_t sgmii_phy_init[512] = { 51 /* 0 1 2 3 4 5 6 7 */ 52 /*-----------------------------------------------------------*/ 53 /* 8 9 A B C D E F */ 54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 118 }; 119 120 /* PHY selector configures with corresponding modes */ 121 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 122 uint32_t comphy_mode) 123 { 124 uint32_t reg; 125 int mode = COMPHY_GET_MODE(comphy_mode); 126 127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 128 switch (mode) { 129 case (COMPHY_SATA_MODE): 130 /* SATA must be in Lane2 */ 131 if (comphy_index == COMPHY_LANE2) 132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 133 else 134 goto error; 135 break; 136 137 case (COMPHY_SGMII_MODE): 138 case (COMPHY_HS_SGMII_MODE): 139 if (comphy_index == COMPHY_LANE0) 140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 141 else if (comphy_index == COMPHY_LANE1) 142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 143 else 144 goto error; 145 break; 146 147 case (COMPHY_USB3H_MODE): 148 case (COMPHY_USB3D_MODE): 149 case (COMPHY_USB3_MODE): 150 if (comphy_index == COMPHY_LANE2) 151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else if (comphy_index == COMPHY_LANE0) 153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 154 else 155 goto error; 156 break; 157 158 case (COMPHY_PCIE_MODE): 159 /* PCIE must be in Lane1 */ 160 if (comphy_index == COMPHY_LANE1) 161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 default: 167 goto error; 168 } 169 170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 171 return; 172 error: 173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 174 } 175 176 /* 177 * This is something like the inverse of the previous function: for given 178 * lane it returns COMPHY_*_MODE. 179 * 180 * It is useful when powering the phy off. 181 * 182 * This function returns COMPHY_USB3_MODE even if the phy was configured 183 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 184 * code does not differentiate between these modes.) 185 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 186 * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate 187 * between these modes, but it is irrelevant when powering the phy off.) 188 */ 189 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 190 { 191 uint32_t reg; 192 193 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 194 switch (comphy_index) { 195 case COMPHY_LANE0: 196 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 197 return COMPHY_USB3_MODE; 198 else 199 return COMPHY_SGMII_MODE; 200 case COMPHY_LANE1: 201 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 202 return COMPHY_PCIE_MODE; 203 else 204 return COMPHY_SGMII_MODE; 205 case COMPHY_LANE2: 206 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 207 return COMPHY_USB3_MODE; 208 else 209 return COMPHY_SATA_MODE; 210 } 211 212 return COMPHY_UNUSED; 213 } 214 215 /* It is only used for SATA and USB3 on comphy lane2. */ 216 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 217 uint16_t mask, int mode) 218 { 219 /* 220 * When Lane 2 PHY is for USB3, access the PHY registers 221 * through indirect Address and Data registers: 222 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 223 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 224 * within the SATA Host Controller registers, Lane 2 base register 225 * offset is 0x200 226 */ 227 if (mode == COMPHY_UNUSED) 228 return; 229 230 if (mode == COMPHY_SATA_MODE) 231 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 232 else 233 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 234 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 235 236 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 237 } 238 239 /* It is only used USB3 direct access not on comphy lane2. */ 240 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 241 uint16_t data, uint16_t mask, int mode) 242 { 243 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 244 } 245 246 static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode, 247 uintptr_t sd_ip_addr) 248 { 249 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 250 int addr, fix_idx; 251 uint16_t val; 252 253 fix_idx = 0; 254 for (addr = 0; addr < 512; addr++) { 255 /* 256 * All PHY register values are defined in full for 3.125Gbps 257 * SERDES speed. The values required for 1.25 Gbps are almost 258 * the same and only few registers should be "fixed" in 259 * comparison to 3.125 Gbps values. These register values are 260 * stored in "sgmii_phy_init_fix" array. 261 */ 262 if ((mode != COMPHY_SGMII_MODE) && 263 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 264 /* Use new value */ 265 val = sgmii_phy_init_fix[fix_idx].value; 266 if (fix_idx < fix_arr_sz) 267 fix_idx++; 268 } else { 269 val = sgmii_phy_init[addr]; 270 } 271 272 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 273 } 274 } 275 276 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 277 uint32_t comphy_mode) 278 { 279 int ret = 0; 280 uint32_t offset, data = 0, ref_clk; 281 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 282 int mode = COMPHY_GET_MODE(comphy_mode); 283 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 284 285 debug_enter(); 286 287 /* Configure phy selector for SATA */ 288 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 289 290 /* Clear phy isolation mode to make it work in normal mode */ 291 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 292 comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE, 293 mode); 294 295 /* 0. Check the Polarity invert bits */ 296 if (invert & COMPHY_POLARITY_TXD_INVERT) 297 data |= TXD_INVERT_BIT; 298 if (invert & COMPHY_POLARITY_RXD_INVERT) 299 data |= RXD_INVERT_BIT; 300 301 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 302 comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 303 RXD_INVERT_BIT, mode); 304 305 /* 1. Select 40-bit data width width */ 306 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 307 comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 308 SEL_DATA_WIDTH_MASK, mode); 309 310 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 311 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 312 if (get_ref_clk() == 40) 313 ref_clk = REF_CLOCK_SPEED_40M; 314 else 315 ref_clk = REF_CLOCK_SPEED_25M; 316 317 comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 318 REF_FREF_SEL_MASK | PHY_MODE_MASK, mode); 319 320 /* 3. Use maximum PLL rate (no power save) */ 321 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 322 comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 323 USE_MAX_PLL_RATE_BIT, mode); 324 325 /* 4. Reset reserved bit */ 326 comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 327 PHYCTRL_FRM_PIN_BIT, mode); 328 329 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 330 /* XXX: in U-Boot below sequence was executed in this place, in Linux 331 * not. Now it is done only in U-Boot before this comphy 332 * initialization - tests shows that it works ok, but in case of any 333 * future problem it is left for reference. 334 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 335 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 336 */ 337 338 /* Wait for > 55 us to allow PLL be enabled */ 339 udelay(PLL_SET_DELAY_US); 340 341 /* Polling status */ 342 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 343 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 344 345 ret = polling_with_timeout(comphy_indir_regs + 346 COMPHY_LANE2_INDIR_DATA_OFFSET, 347 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 348 COMPHY_PLL_TIMEOUT, REG_32BIT); 349 350 debug_exit(); 351 352 return ret; 353 } 354 355 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 356 uint32_t comphy_mode) 357 { 358 int ret = 0; 359 uint32_t mask, data, offset; 360 uintptr_t sd_ip_addr; 361 int mode = COMPHY_GET_MODE(comphy_mode); 362 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 363 364 debug_enter(); 365 366 /* Set selector */ 367 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 368 369 /* Serdes IP Base address 370 * COMPHY Lane0 -- USB3/GBE1 371 * COMPHY Lane1 -- PCIe/GBE0 372 */ 373 if (comphy_index == COMPHY_LANE0) { 374 /* Get usb3 and gbe */ 375 sd_ip_addr = USB3_GBE1_PHY; 376 } else 377 sd_ip_addr = COMPHY_SD_ADDR; 378 379 /* 380 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 381 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 382 * PHY TXP/TXN output to idle state during PHY initialization 383 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 384 */ 385 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 386 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 387 PIN_PU_TX_BIT; 388 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 389 reg_set(offset, data, mask); 390 391 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 392 data = 0; 393 mask = PIN_RESET_COMPHY_BIT; 394 reg_set(offset, data, mask); 395 396 /* 397 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 398 * bit rate 399 */ 400 if (mode == COMPHY_SGMII_MODE) { 401 /* SGMII 1G, SerDes speed 1.25G */ 402 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 403 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 404 } else if (mode == COMPHY_HS_SGMII_MODE) { 405 /* HS SGMII (2.5G), SerDes speed 3.125G */ 406 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 407 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 408 } else { 409 /* Other rates are not supported */ 410 ERROR("unsupported SGMII speed on comphy lane%d\n", 411 comphy_index); 412 return -EINVAL; 413 } 414 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 415 reg_set(offset, data, mask); 416 417 /* 418 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 419 * start SW programming. 420 */ 421 mdelay(10); 422 423 /* 7. Program COMPHY register PHY_MODE */ 424 data = PHY_MODE_SGMII; 425 mask = PHY_MODE_MASK; 426 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 427 428 /* 429 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 430 * source 431 */ 432 data = 0; 433 mask = PHY_REF_CLK_SEL; 434 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 435 436 /* 437 * 9. Set correct reference clock frequency in COMPHY register 438 * REF_FREF_SEL. 439 */ 440 if (get_ref_clk() == 40) 441 data = REF_CLOCK_SPEED_50M; 442 else 443 data = REF_CLOCK_SPEED_25M; 444 445 mask = REF_FREF_SEL_MASK; 446 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 447 448 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 449 * This step is mentioned in the flow received from verification team. 450 * However the PHY_GEN_MAX value is only meaningful for other interfaces 451 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 452 * speed 2.5/5 Gbps 453 */ 454 455 /* 456 * 11. Program COMPHY register SEL_BITS to set correct parallel data 457 * bus width 458 */ 459 data = DATA_WIDTH_10BIT; 460 mask = SEL_DATA_WIDTH_MASK; 461 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 462 463 /* 464 * 12. As long as DFE function needs to be enabled in any mode, 465 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 466 * for real chip during COMPHY power on. 467 * The step 14 exists (and empty) in the original initialization flow 468 * obtained from the verification team. According to the functional 469 * specification DFE_UPDATE_EN already has the default value 0x3F 470 */ 471 472 /* 473 * 13. Program COMPHY GEN registers. 474 * These registers should be programmed based on the lab testing result 475 * to achieve optimal performance. Please contact the CEA group to get 476 * the related GEN table during real chip bring-up. We only required to 477 * run though the entire registers programming flow defined by 478 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 479 * 25 MHz the default values stored in PHY registers are OK. 480 */ 481 debug("Running C-DPI phy init %s mode\n", 482 mode == COMPHY_HS_SGMII_MODE ? "2G5" : "1G"); 483 if (get_ref_clk() == 40) 484 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr); 485 486 /* 487 * 14. [Simulation Only] should not be used for real chip. 488 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 489 * (R02h[9]) to 1 to shorten COMPHY simulation time. 490 */ 491 492 /* 493 * 15. [Simulation Only: should not be used for real chip] 494 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 495 * simulation time. 496 */ 497 498 /* 499 * 16. Check the PHY Polarity invert bit 500 */ 501 data = 0x0; 502 if (invert & COMPHY_POLARITY_TXD_INVERT) 503 data |= TXD_INVERT_BIT; 504 if (invert & COMPHY_POLARITY_RXD_INVERT) 505 data |= RXD_INVERT_BIT; 506 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 507 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); 508 509 /* 510 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 511 * start PHY power up sequence. All the PHY register programming should 512 * be done before PIN_PU_PLL=1. There should be no register programming 513 * for normal PHY operation from this point. 514 */ 515 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 516 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 517 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 518 519 /* 520 * 18. Wait for PHY power up sequence to finish by checking output ports 521 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 522 */ 523 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 524 COMPHY_PHY_STATUS_OFFSET(comphy_index), 525 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 526 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 527 COMPHY_PLL_TIMEOUT, REG_32BIT); 528 if (ret) 529 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 530 531 /* 532 * 19. Set COMPHY input port PIN_TX_IDLE=0 533 */ 534 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 535 0x0, PIN_TX_IDLE_BIT); 536 537 /* 538 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 539 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 540 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 541 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 542 * refer to RX initialization part for details. 543 */ 544 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 545 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 546 547 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 548 COMPHY_PHY_STATUS_OFFSET(comphy_index), 549 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 550 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 551 COMPHY_PLL_TIMEOUT, REG_32BIT); 552 if (ret) 553 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 554 555 556 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 557 COMPHY_PHY_STATUS_OFFSET(comphy_index), 558 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 559 COMPHY_PLL_TIMEOUT, REG_32BIT); 560 if (ret) 561 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 562 563 debug_exit(); 564 565 return ret; 566 } 567 568 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 569 { 570 int ret = 0; 571 uint32_t mask, data, offset; 572 573 debug_enter(); 574 575 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 576 mask = data; 577 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 578 reg_set(offset, data, mask); 579 580 debug_exit(); 581 582 return ret; 583 } 584 585 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 586 uint32_t comphy_mode) 587 { 588 int ret = 0; 589 uintptr_t reg_base = 0; 590 uint32_t mask, data, addr, cfg, ref_clk; 591 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 592 uint16_t mask, int mode); 593 int mode = COMPHY_GET_MODE(comphy_mode); 594 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 595 596 debug_enter(); 597 598 /* Set phy seclector */ 599 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 600 601 /* Set usb3 reg access func, Lane2 is indirect access */ 602 if (comphy_index == COMPHY_LANE2) { 603 usb3_reg_set = &comphy_set_indirect; 604 reg_base = COMPHY_INDIRECT_REG; 605 } else { 606 /* Get the direct access register resource and map */ 607 usb3_reg_set = &comphy_usb3_set_direct; 608 reg_base = USB3_GBE1_PHY; 609 } 610 611 /* 612 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 613 * register belong to UTMI module, so it is set in UTMI phy driver. 614 */ 615 616 /* 617 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 618 */ 619 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 620 CFG_TX_ALIGN_POS_MASK; 621 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 622 mask, mode); 623 624 /* 625 * 2. Set BIT0: enable transmitter in high impedance mode 626 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 627 * Set BIT6: Tx detect Rx at HiZ mode 628 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 629 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 630 */ 631 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 632 TX_ELEC_IDLE_MODE_EN; 633 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 634 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); 635 636 /* 637 * 3. Set Spread Spectrum Clock Enabled 638 */ 639 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 640 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode); 641 642 /* 643 * 4. Set Override Margining Controls From the MAC: 644 * Use margining signals from lane configuration 645 */ 646 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 647 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode); 648 649 /* 650 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 651 * set Mode Clock Source = PCLK is generated from REFCLK 652 */ 653 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 654 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 655 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode); 656 657 /* 658 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 659 */ 660 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 661 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode); 662 663 /* 664 * 7. Unset G3 Spread Spectrum Clock Amplitude 665 * set G3 TX and RX Register Master Current Select 666 */ 667 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 668 RSVD_PH03FH_6_0_MASK; 669 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 670 G3_VREG_RXTX_MAS_ISET_60U, mask, mode); 671 672 /* 673 * 8. Check crystal jumper setting and program the Power and PLL Control 674 * accordingly Change RX wait 675 */ 676 if (get_ref_clk() == 40) { 677 ref_clk = REF_CLOCK_SPEED_40M; 678 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 679 680 } else { 681 /* 25 MHz */ 682 ref_clk = USB3_REF_CLOCK_SPEED_25M; 683 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 684 } 685 686 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 687 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 688 REF_FREF_SEL_MASK; 689 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 690 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 691 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode); 692 693 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 694 CFG_PM_RXDLOZ_WAIT_MASK; 695 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 696 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode); 697 698 /* 699 * 9. Enable idle sync 700 */ 701 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 702 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK, 703 mode); 704 705 /* 706 * 10. Enable the output of 500M clock 707 */ 708 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 709 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK, 710 mode); 711 712 /* 713 * 11. Set 20-bit data width 714 */ 715 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 716 REG_16_BIT_MASK, mode); 717 718 /* 719 * 12. Override Speed_PLL value and use MAC PLL 720 */ 721 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 722 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 723 REG_16_BIT_MASK, mode); 724 725 /* 726 * 13. Check the Polarity invert bit 727 */ 728 data = 0U; 729 if (invert & COMPHY_POLARITY_TXD_INVERT) { 730 data |= TXD_INVERT_BIT; 731 } 732 if (invert & COMPHY_POLARITY_RXD_INVERT) { 733 data |= RXD_INVERT_BIT; 734 } 735 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 736 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode); 737 738 /* 739 * 14. Set max speed generation to USB3.0 5Gbps 740 */ 741 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 742 PHY_GEN_MAX_MASK, mode); 743 744 /* 745 * 15. Set capacitor value for FFE gain peaking to 0xF 746 */ 747 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 748 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK, 749 mode); 750 751 /* 752 * 16. Release SW reset 753 */ 754 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 755 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 756 REG_16_BIT_MASK, mode); 757 758 /* Wait for > 55 us to allow PCLK be enabled */ 759 udelay(PLL_SET_DELAY_US); 760 761 if (comphy_index == COMPHY_LANE2) { 762 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; 763 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 764 data); 765 766 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 767 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 768 COMPHY_PLL_TIMEOUT, REG_32BIT); 769 } else { 770 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 771 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 772 COMPHY_PLL_TIMEOUT, REG_16BIT); 773 } 774 if (ret) 775 ERROR("Failed to lock USB3 PLL\n"); 776 777 debug_exit(); 778 779 return ret; 780 } 781 782 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 783 uint32_t comphy_mode) 784 { 785 int ret; 786 uint32_t ref_clk; 787 uint32_t mask, data; 788 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 789 790 debug_enter(); 791 792 /* 1. Enable max PLL. */ 793 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 794 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 795 796 /* 2. Select 20 bit SERDES interface. */ 797 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 798 CFG_SEL_20B, CFG_SEL_20B); 799 800 /* 3. Force to use reg setting for PCIe mode */ 801 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 802 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 803 804 /* 4. Change RX wait */ 805 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 806 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 807 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 808 CFG_PM_RXDLOZ_WAIT_MASK)); 809 810 /* 5. Enable idle sync */ 811 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 812 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 813 814 /* 6. Enable the output of 100M/125M/500M clock */ 815 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 816 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 817 REG_16_BIT_MASK); 818 819 /* 820 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 821 * PCI-E driver 822 */ 823 824 /* 825 * 8. Check crystal jumper setting and program the Power and PLL 826 * Control accordingly 827 */ 828 829 if (get_ref_clk() == 40) 830 ref_clk = REF_CLOCK_SPEED_40M; 831 else 832 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 833 834 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 835 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 836 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 837 REG_16_BIT_MASK); 838 839 /* 9. Override Speed_PLL value and use MAC PLL */ 840 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 841 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 842 843 /* 10. Check the Polarity invert bit */ 844 data = 0U; 845 if (invert & COMPHY_POLARITY_TXD_INVERT) { 846 data |= TXD_INVERT_BIT; 847 } 848 if (invert & COMPHY_POLARITY_RXD_INVERT) { 849 data |= RXD_INVERT_BIT; 850 } 851 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 852 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 853 854 /* 11. Release SW reset */ 855 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 856 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 857 SOFT_RESET | MODE_REFDIV); 858 859 /* Wait for > 55 us to allow PCLK be enabled */ 860 udelay(PLL_SET_DELAY_US); 861 862 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 863 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 864 COMPHY_PLL_TIMEOUT, REG_16BIT); 865 if (ret) 866 ERROR("Failed to lock PCIE PLL\n"); 867 868 debug_exit(); 869 870 return ret; 871 } 872 873 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 874 { 875 int mode = COMPHY_GET_MODE(comphy_mode); 876 int ret = 0; 877 878 debug_enter(); 879 880 switch (mode) { 881 case(COMPHY_SATA_MODE): 882 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 883 comphy_mode); 884 break; 885 case(COMPHY_SGMII_MODE): 886 case(COMPHY_HS_SGMII_MODE): 887 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 888 comphy_mode); 889 break; 890 case (COMPHY_USB3_MODE): 891 case (COMPHY_USB3H_MODE): 892 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 893 comphy_mode); 894 break; 895 case (COMPHY_PCIE_MODE): 896 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 897 comphy_mode); 898 break; 899 default: 900 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 901 ret = -EINVAL; 902 break; 903 } 904 905 debug_exit(); 906 907 return ret; 908 } 909 910 static int mvebu_a3700_comphy_usb3_power_off(void) 911 { 912 /* 913 * Currently the USB3 MAC will control the USB3 PHY to set it to low 914 * state, thus do not need to power off USB3 PHY again. 915 */ 916 debug_enter(); 917 debug_exit(); 918 919 return 0; 920 } 921 922 static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode) 923 { 924 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 925 int mode = COMPHY_GET_MODE(comphy_mode); 926 uint32_t offset; 927 928 debug_enter(); 929 930 /* Set phy isolation mode */ 931 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 932 comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 933 PHY_ISOLATE_MODE, mode); 934 935 /* Power off PLL, Tx, Rx */ 936 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 937 comphy_set_indirect(comphy_indir_regs, offset, 0, 938 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode); 939 940 debug_exit(); 941 942 return 0; 943 } 944 945 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 946 { 947 int mode = COMPHY_GET_MODE(comphy_mode); 948 int err = 0; 949 950 debug_enter(); 951 952 if (!mode) { 953 /* 954 * The user did not specify which mode should be powered off. 955 * In this case we can identify this by reading the phy selector 956 * register. 957 */ 958 mode = mvebu_a3700_comphy_get_mode(comphy_index); 959 } 960 961 switch (mode) { 962 case(COMPHY_SGMII_MODE): 963 case(COMPHY_HS_SGMII_MODE): 964 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 965 break; 966 case (COMPHY_USB3_MODE): 967 case (COMPHY_USB3H_MODE): 968 err = mvebu_a3700_comphy_usb3_power_off(); 969 break; 970 case (COMPHY_SATA_MODE): 971 err = mvebu_a3700_comphy_sata_power_off(comphy_mode); 972 break; 973 974 default: 975 debug("comphy%d: power off is not implemented for mode %d\n", 976 comphy_index, mode); 977 break; 978 } 979 980 debug_exit(); 981 982 return err; 983 } 984 985 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 986 { 987 uint32_t data, addr; 988 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 989 int ret = 0; 990 991 debug_enter(); 992 993 /* Polling status */ 994 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 995 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 996 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 997 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 998 COMPHY_PLL_TIMEOUT, REG_32BIT); 999 1000 if (data != 0) { 1001 ERROR("TX PLL is not locked\n"); 1002 ret = -ETIMEDOUT; 1003 } 1004 1005 debug_exit(); 1006 1007 return ret; 1008 } 1009 1010 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1011 { 1012 int mode = COMPHY_GET_MODE(comphy_mode); 1013 int ret = 0; 1014 1015 debug_enter(); 1016 1017 switch (mode) { 1018 case(COMPHY_SATA_MODE): 1019 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1020 break; 1021 1022 default: 1023 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1024 comphy_index, mode); 1025 ret = -EINVAL; 1026 break; 1027 } 1028 1029 debug_exit(); 1030 1031 return ret; 1032 } 1033