1 /* 2 * Copyright (C) 2018-2021 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 #include <plat_marvell.h> 18 19 #include "phy-comphy-3700.h" 20 #include "phy-comphy-common.h" 21 22 /* 23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 24 * Linux is up to 0x178 so none will access it from Linux in runtime 25 * concurrently. 26 */ 27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 28 29 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 32 33 struct sgmii_phy_init_data_fix { 34 uint16_t addr; 35 uint16_t value; 36 }; 37 38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 39 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 46 {0x104, 0x0C10} 47 }; 48 49 /* 40M1G25 mode init data */ 50 static uint16_t sgmii_phy_init[512] = { 51 /* 0 1 2 3 4 5 6 7 */ 52 /*-----------------------------------------------------------*/ 53 /* 8 9 A B C D E F */ 54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 118 }; 119 120 /* PHY selector configures with corresponding modes */ 121 static int mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 122 uint32_t comphy_mode) 123 { 124 uint32_t reg; 125 int mode = COMPHY_GET_MODE(comphy_mode); 126 127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 128 switch (mode) { 129 case (COMPHY_SATA_MODE): 130 /* SATA must be in Lane2 */ 131 if (comphy_index == COMPHY_LANE2) 132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 133 else 134 goto error; 135 break; 136 137 case (COMPHY_SGMII_MODE): 138 case (COMPHY_2500BASEX_MODE): 139 if (comphy_index == COMPHY_LANE0) 140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 141 else if (comphy_index == COMPHY_LANE1) 142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 143 else 144 goto error; 145 break; 146 147 case (COMPHY_USB3H_MODE): 148 case (COMPHY_USB3D_MODE): 149 case (COMPHY_USB3_MODE): 150 if (comphy_index == COMPHY_LANE2) 151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else if (comphy_index == COMPHY_LANE0) 153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 154 else 155 goto error; 156 break; 157 158 case (COMPHY_PCIE_MODE): 159 /* PCIE must be in Lane1 */ 160 if (comphy_index == COMPHY_LANE1) 161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 default: 167 goto error; 168 } 169 170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 171 return 0; 172 error: 173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 174 return -EINVAL; 175 } 176 177 /* 178 * This is something like the inverse of the previous function: for given 179 * lane it returns COMPHY_*_MODE. 180 * 181 * It is useful when powering the phy off. 182 * 183 * This function returns COMPHY_USB3_MODE even if the phy was configured 184 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 185 * code does not differentiate between these modes.) 186 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 187 * COMPHY_2500BASEX_MODE. (The sgmii phy initialization code does differentiate 188 * between these modes, but it is irrelevant when powering the phy off.) 189 */ 190 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 191 { 192 uint32_t reg; 193 194 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 195 switch (comphy_index) { 196 case COMPHY_LANE0: 197 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 198 return COMPHY_USB3_MODE; 199 else 200 return COMPHY_SGMII_MODE; 201 case COMPHY_LANE1: 202 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 203 return COMPHY_PCIE_MODE; 204 else 205 return COMPHY_SGMII_MODE; 206 case COMPHY_LANE2: 207 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 208 return COMPHY_USB3_MODE; 209 else 210 return COMPHY_SATA_MODE; 211 } 212 213 return COMPHY_UNUSED; 214 } 215 216 /* It is only used for SATA and USB3 on comphy lane2. */ 217 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 218 uint16_t mask, bool is_sata) 219 { 220 /* 221 * When Lane 2 PHY is for USB3, access the PHY registers 222 * through indirect Address and Data registers: 223 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 224 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 225 * within the SATA Host Controller registers, Lane 2 base register 226 * offset is 0x200 227 */ 228 if (is_sata) { 229 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 230 } else { 231 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 232 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 233 } 234 235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 236 } 237 238 /* It is only used for SATA on comphy lane2. */ 239 static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset, 240 uint16_t data, uint16_t mask) 241 { 242 comphy_set_indirect(addr, reg_offset, data, mask, true); 243 } 244 245 /* It is only used for USB3 indirect access on comphy lane2. */ 246 static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset, 247 uint16_t data, uint16_t mask) 248 { 249 comphy_set_indirect(addr, reg_offset, data, mask, false); 250 } 251 252 /* It is only used for USB3 direct access not on comphy lane2. */ 253 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 254 uint16_t data, uint16_t mask) 255 { 256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 257 } 258 259 static void comphy_sgmii_phy_init(uintptr_t sd_ip_addr, bool is_1gbps) 260 { 261 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 262 int addr, fix_idx; 263 uint16_t val; 264 265 fix_idx = 0; 266 for (addr = 0; addr < 512; addr++) { 267 /* 268 * All PHY register values are defined in full for 3.125Gbps 269 * SERDES speed. The values required for 1.25 Gbps are almost 270 * the same and only few registers should be "fixed" in 271 * comparison to 3.125 Gbps values. These register values are 272 * stored in "sgmii_phy_init_fix" array. 273 */ 274 if (!is_1gbps && sgmii_phy_init_fix[fix_idx].addr == addr) { 275 /* Use new value */ 276 val = sgmii_phy_init_fix[fix_idx].value; 277 if (fix_idx < fix_arr_sz) 278 fix_idx++; 279 } else { 280 val = sgmii_phy_init[addr]; 281 } 282 283 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 284 } 285 } 286 287 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 288 uint32_t comphy_mode) 289 { 290 int ret; 291 uint32_t offset, data = 0, ref_clk; 292 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 293 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 294 295 debug_enter(); 296 297 /* Configure phy selector for SATA */ 298 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 299 if (ret) { 300 return ret; 301 } 302 303 /* Clear phy isolation mode to make it work in normal mode */ 304 offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 305 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE); 306 307 /* 0. Check the Polarity invert bits */ 308 if (invert & COMPHY_POLARITY_TXD_INVERT) 309 data |= TXD_INVERT_BIT; 310 if (invert & COMPHY_POLARITY_RXD_INVERT) 311 data |= RXD_INVERT_BIT; 312 313 offset = COMPHY_SYNC_PATTERN + SATAPHY_LANE2_REG_BASE_OFFSET; 314 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 315 RXD_INVERT_BIT); 316 317 /* 1. Select 40-bit data width width */ 318 offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET; 319 comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 320 SEL_DATA_WIDTH_MASK); 321 322 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 323 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 324 if (get_ref_clk() == 40) 325 ref_clk = REF_FREF_SEL_SERDES_40MHZ; 326 else 327 ref_clk = REF_FREF_SEL_SERDES_25MHZ; 328 329 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 330 REF_FREF_SEL_MASK | PHY_MODE_MASK); 331 332 /* 3. Use maximum PLL rate (no power save) */ 333 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 334 comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 335 USE_MAX_PLL_RATE_BIT); 336 337 /* 4. Reset reserved bit */ 338 comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 339 PHYCTRL_FRM_PIN_BIT); 340 341 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 342 /* XXX: in U-Boot below sequence was executed in this place, in Linux 343 * not. Now it is done only in U-Boot before this comphy 344 * initialization - tests shows that it works ok, but in case of any 345 * future problem it is left for reference. 346 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 347 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 348 */ 349 350 /* Wait for > 55 us to allow PLL be enabled */ 351 udelay(PLL_SET_DELAY_US); 352 353 /* Polling status */ 354 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 355 COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET); 356 357 ret = polling_with_timeout(comphy_indir_regs + 358 COMPHY_LANE2_INDIR_DATA_OFFSET, 359 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 360 COMPHY_PLL_TIMEOUT, REG_32BIT); 361 if (ret) { 362 return -ETIMEDOUT; 363 } 364 365 debug_exit(); 366 367 return 0; 368 } 369 370 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 371 uint32_t comphy_mode) 372 { 373 int ret; 374 uint32_t mask, data; 375 uintptr_t offset; 376 uintptr_t sd_ip_addr; 377 int mode = COMPHY_GET_MODE(comphy_mode); 378 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 379 380 debug_enter(); 381 382 /* Set selector */ 383 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 384 if (ret) { 385 return ret; 386 } 387 388 /* Serdes IP Base address 389 * COMPHY Lane0 -- USB3/GBE1 390 * COMPHY Lane1 -- PCIe/GBE0 391 */ 392 if (comphy_index == COMPHY_LANE0) { 393 /* Get usb3 and gbe */ 394 sd_ip_addr = USB3_GBE1_PHY; 395 } else 396 sd_ip_addr = COMPHY_SD_ADDR; 397 398 /* 399 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 400 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 401 * PHY TXP/TXN output to idle state during PHY initialization 402 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 403 */ 404 data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 405 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 406 PIN_PU_TX_BIT; 407 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 408 reg_set(offset, data, mask); 409 410 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 411 data = 0; 412 mask = PIN_RESET_COMPHY_BIT; 413 reg_set(offset, data, mask); 414 415 /* 416 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 417 * bit rate 418 */ 419 if (mode == COMPHY_SGMII_MODE) { 420 /* SGMII 1G, SerDes speed 1.25G */ 421 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 422 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 423 } else if (mode == COMPHY_2500BASEX_MODE) { 424 /* 2500Base-X, SerDes speed 3.125G */ 425 data |= SD_SPEED_3_125_G << GEN_RX_SEL_OFFSET; 426 data |= SD_SPEED_3_125_G << GEN_TX_SEL_OFFSET; 427 } else { 428 /* Other rates are not supported */ 429 ERROR("unsupported SGMII speed on comphy lane%d\n", 430 comphy_index); 431 return -EINVAL; 432 } 433 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 434 reg_set(offset, data, mask); 435 436 /* 437 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 438 * start SW programming. 439 */ 440 mdelay(10); 441 442 /* 7. Program COMPHY register PHY_MODE */ 443 data = PHY_MODE_SGMII; 444 mask = PHY_MODE_MASK; 445 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 446 447 /* 448 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 449 * source 450 */ 451 data = 0; 452 mask = PHY_REF_CLK_SEL; 453 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask); 454 455 /* 456 * 9. Set correct reference clock frequency in COMPHY register 457 * REF_FREF_SEL. 458 */ 459 if (get_ref_clk() == 40) 460 data = REF_FREF_SEL_SERDES_50MHZ; 461 else 462 data = REF_FREF_SEL_SERDES_25MHZ; 463 464 mask = REF_FREF_SEL_MASK; 465 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 466 467 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 468 * This step is mentioned in the flow received from verification team. 469 * However the PHY_GEN_MAX value is only meaningful for other interfaces 470 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 471 * speed 2.5/5 Gbps 472 */ 473 474 /* 475 * 11. Program COMPHY register SEL_BITS to set correct parallel data 476 * bus width 477 */ 478 data = DATA_WIDTH_10BIT; 479 mask = SEL_DATA_WIDTH_MASK; 480 reg_set16(SGMIIPHY_ADDR(COMPHY_DIG_LOOPBACK_EN, sd_ip_addr), 481 data, mask); 482 483 /* 484 * 12. As long as DFE function needs to be enabled in any mode, 485 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 486 * for real chip during COMPHY power on. 487 * The step 14 exists (and empty) in the original initialization flow 488 * obtained from the verification team. According to the functional 489 * specification DFE_UPDATE_EN already has the default value 0x3F 490 */ 491 492 /* 493 * 13. Program COMPHY GEN registers. 494 * These registers should be programmed based on the lab testing result 495 * to achieve optimal performance. Please contact the CEA group to get 496 * the related GEN table during real chip bring-up. We only required to 497 * run though the entire registers programming flow defined by 498 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 499 * 25 MHz the default values stored in PHY registers are OK. 500 */ 501 debug("Running C-DPI phy init %s mode\n", 502 mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G"); 503 if (get_ref_clk() == 40) 504 comphy_sgmii_phy_init(sd_ip_addr, mode != COMPHY_2500BASEX_MODE); 505 506 /* 507 * 14. [Simulation Only] should not be used for real chip. 508 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 509 * (R02h[9]) to 1 to shorten COMPHY simulation time. 510 */ 511 512 /* 513 * 15. [Simulation Only: should not be used for real chip] 514 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 515 * simulation time. 516 */ 517 518 /* 519 * 16. Check the PHY Polarity invert bit 520 */ 521 data = 0x0; 522 if (invert & COMPHY_POLARITY_TXD_INVERT) 523 data |= TXD_INVERT_BIT; 524 if (invert & COMPHY_POLARITY_RXD_INVERT) 525 data |= RXD_INVERT_BIT; 526 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 527 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN, sd_ip_addr), data, mask); 528 529 /* 530 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 531 * start PHY power up sequence. All the PHY register programming should 532 * be done before PIN_PU_PLL=1. There should be no register programming 533 * for normal PHY operation from this point. 534 */ 535 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 536 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 537 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 538 539 /* 540 * 18. Wait for PHY power up sequence to finish by checking output ports 541 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 542 */ 543 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 544 COMPHY_PHY_STATUS_OFFSET(comphy_index), 545 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 546 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 547 COMPHY_PLL_TIMEOUT, REG_32BIT); 548 if (ret) { 549 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 550 return -ETIMEDOUT; 551 } 552 553 /* 554 * 19. Set COMPHY input port PIN_TX_IDLE=0 555 */ 556 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 557 0x0, PIN_TX_IDLE_BIT); 558 559 /* 560 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 561 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 562 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 563 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 564 * refer to RX initialization part for details. 565 */ 566 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 567 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 568 569 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 570 COMPHY_PHY_STATUS_OFFSET(comphy_index), 571 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 572 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 573 COMPHY_PLL_TIMEOUT, REG_32BIT); 574 if (ret) { 575 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 576 return -ETIMEDOUT; 577 } 578 579 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 580 COMPHY_PHY_STATUS_OFFSET(comphy_index), 581 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 582 COMPHY_PLL_TIMEOUT, REG_32BIT); 583 if (ret) { 584 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 585 return -ETIMEDOUT; 586 } 587 588 debug_exit(); 589 590 return 0; 591 } 592 593 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 594 { 595 uintptr_t offset; 596 uint32_t mask, data; 597 598 debug_enter(); 599 600 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 601 mask = data; 602 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 603 reg_set(offset, data, mask); 604 605 debug_exit(); 606 607 return 0; 608 } 609 610 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 611 uint32_t comphy_mode) 612 { 613 int ret; 614 uintptr_t reg_base = 0; 615 uintptr_t addr; 616 uint32_t mask, data, cfg, ref_clk; 617 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 618 uint16_t mask); 619 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 620 621 debug_enter(); 622 623 /* Set phy seclector */ 624 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 625 if (ret) { 626 return ret; 627 } 628 629 /* Set usb3 reg access func, Lane2 is indirect access */ 630 if (comphy_index == COMPHY_LANE2) { 631 usb3_reg_set = &comphy_usb3_set_indirect; 632 reg_base = COMPHY_INDIRECT_REG; 633 } else { 634 /* Get the direct access register resource and map */ 635 usb3_reg_set = &comphy_usb3_set_direct; 636 reg_base = USB3_GBE1_PHY; 637 } 638 639 /* 640 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 641 * register belong to UTMI module, so it is set in UTMI phy driver. 642 */ 643 644 /* 645 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 646 */ 647 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 648 CFG_TX_ALIGN_POS_MASK; 649 usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask); 650 651 /* 652 * 2. Set BIT0: enable transmitter in high impedance mode 653 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 654 * Set BIT6: Tx detect Rx at HiZ mode 655 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 656 * together with bit 0 of COMPHY_LANE_CFG0 register 657 */ 658 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 659 TX_ELEC_IDLE_MODE_EN; 660 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 661 usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask); 662 663 /* 664 * 3. Set Spread Spectrum Clock Enabled 665 */ 666 usb3_reg_set(reg_base, COMPHY_LANE_CFG4, 667 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 668 669 /* 670 * 4. Set Override Margining Controls From the MAC: 671 * Use margining signals from lane configuration 672 */ 673 usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL, 674 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK); 675 676 /* 677 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 678 * set Mode Clock Source = PCLK is generated from REFCLK 679 */ 680 usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0, 681 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | 682 BUNDLE_PERIOD_SCALE_MASK | BUNDLE_SAMPLE_CTRL | 683 PLL_READY_DLY_MASK)); 684 685 /* 686 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 687 */ 688 usb3_reg_set(reg_base, COMPHY_GEN2_SET2, 689 GS2_TX_SSC_AMP_VALUE_20, GS2_TX_SSC_AMP_MASK); 690 691 /* 692 * 7. Unset G3 Spread Spectrum Clock Amplitude 693 * set G3 TX and RX Register Master Current Select 694 */ 695 mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | 696 GS2_RSVD_6_0_MASK; 697 usb3_reg_set(reg_base, COMPHY_GEN3_SET2, 698 GS2_VREG_RXTX_MAS_ISET_60U, mask); 699 700 /* 701 * 8. Check crystal jumper setting and program the Power and PLL Control 702 * accordingly Change RX wait 703 */ 704 if (get_ref_clk() == 40) { 705 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 706 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 707 708 } else { 709 /* 25 MHz */ 710 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 711 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 712 } 713 714 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 715 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 716 REF_FREF_SEL_MASK; 717 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 718 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 719 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask); 720 721 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 722 CFG_PM_RXDLOZ_WAIT_MASK; 723 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 724 usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask); 725 726 /* 727 * 9. Enable idle sync 728 */ 729 data = IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN; 730 usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK); 731 732 /* 733 * 10. Enable the output of 500M clock 734 */ 735 data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN; 736 usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK); 737 738 /* 739 * 11. Set 20-bit data width 740 */ 741 usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT, 742 REG_16_BIT_MASK); 743 744 /* 745 * 12. Override Speed_PLL value and use MAC PLL 746 */ 747 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 748 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 749 REG_16_BIT_MASK); 750 751 /* 752 * 13. Check the Polarity invert bit 753 */ 754 data = 0U; 755 if (invert & COMPHY_POLARITY_TXD_INVERT) { 756 data |= TXD_INVERT_BIT; 757 } 758 if (invert & COMPHY_POLARITY_RXD_INVERT) { 759 data |= RXD_INVERT_BIT; 760 } 761 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 762 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask); 763 764 /* 765 * 14. Set max speed generation to USB3.0 5Gbps 766 */ 767 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN, PHY_GEN_MAX_USB3_5G, 768 PHY_GEN_MAX_MASK); 769 770 /* 771 * 15. Set capacitor value for FFE gain peaking to 0xF 772 */ 773 usb3_reg_set(reg_base, COMPHY_GEN2_SET3, 774 GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); 775 776 /* 777 * 16. Release SW reset 778 */ 779 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 780 usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK); 781 782 /* Wait for > 55 us to allow PCLK be enabled */ 783 udelay(PLL_SET_DELAY_US); 784 785 if (comphy_index == COMPHY_LANE2) { 786 data = COMPHY_LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET; 787 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 788 data); 789 790 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 791 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 792 COMPHY_PLL_TIMEOUT, REG_32BIT); 793 } else { 794 ret = polling_with_timeout(LANE_STAT1_ADDR(USB3) + reg_base, 795 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 796 COMPHY_PLL_TIMEOUT, REG_16BIT); 797 } 798 if (ret) { 799 ERROR("Failed to lock USB3 PLL\n"); 800 return -ETIMEDOUT; 801 } 802 803 debug_exit(); 804 805 return 0; 806 } 807 808 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 809 uint32_t comphy_mode) 810 { 811 int ret; 812 uint32_t ref_clk; 813 uint32_t mask, data; 814 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 815 816 debug_enter(); 817 818 /* Configure phy selector for PCIe */ 819 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 820 if (ret) { 821 return ret; 822 } 823 824 /* 1. Enable max PLL. */ 825 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 826 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 827 828 /* 2. Select 20 bit SERDES interface. */ 829 reg_set16(CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 830 CFG_SEL_20B, CFG_SEL_20B); 831 832 /* 3. Force to use reg setting for PCIe mode */ 833 reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR, 834 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 835 836 /* 4. Change RX wait */ 837 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 838 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 839 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 840 CFG_PM_RXDLOZ_WAIT_MASK)); 841 842 /* 5. Enable idle sync */ 843 reg_set16(IDLE_SYNC_EN_ADDR(PCIE) + COMPHY_SD_ADDR, 844 IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 845 846 /* 6. Enable the output of 100M/125M/500M clock */ 847 reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 848 MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 849 REG_16_BIT_MASK); 850 851 /* 852 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 853 * PCI-E driver 854 */ 855 856 /* 857 * 8. Check crystal jumper setting and program the Power and PLL 858 * Control accordingly 859 */ 860 861 if (get_ref_clk() == 40) 862 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 863 else 864 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 865 866 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 867 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 868 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 869 REG_16_BIT_MASK); 870 871 /* 9. Override Speed_PLL value and use MAC PLL */ 872 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 873 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 874 875 /* 10. Check the Polarity invert bit */ 876 data = 0U; 877 if (invert & COMPHY_POLARITY_TXD_INVERT) { 878 data |= TXD_INVERT_BIT; 879 } 880 if (invert & COMPHY_POLARITY_RXD_INVERT) { 881 data |= RXD_INVERT_BIT; 882 } 883 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 884 reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 885 886 /* 11. Release SW reset */ 887 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; 888 mask = data | SOFT_RESET | MODE_REFDIV_MASK; 889 reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 890 891 /* Wait for > 55 us to allow PCLK be enabled */ 892 udelay(PLL_SET_DELAY_US); 893 894 ret = polling_with_timeout(LANE_STAT1_ADDR(PCIE) + COMPHY_SD_ADDR, 895 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 896 COMPHY_PLL_TIMEOUT, REG_16BIT); 897 if (ret) { 898 ERROR("Failed to lock PCIE PLL\n"); 899 return -ETIMEDOUT; 900 } 901 902 debug_exit(); 903 904 return 0; 905 } 906 907 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 908 { 909 int mode = COMPHY_GET_MODE(comphy_mode); 910 int ret = 0; 911 912 debug_enter(); 913 914 switch (mode) { 915 case(COMPHY_SATA_MODE): 916 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 917 comphy_mode); 918 break; 919 case(COMPHY_SGMII_MODE): 920 case(COMPHY_2500BASEX_MODE): 921 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 922 comphy_mode); 923 break; 924 case (COMPHY_USB3_MODE): 925 case (COMPHY_USB3H_MODE): 926 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 927 comphy_mode); 928 break; 929 case (COMPHY_PCIE_MODE): 930 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 931 comphy_mode); 932 break; 933 default: 934 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 935 ret = -EINVAL; 936 break; 937 } 938 939 debug_exit(); 940 941 return ret; 942 } 943 944 static int mvebu_a3700_comphy_usb3_power_off(void) 945 { 946 /* 947 * Currently the USB3 MAC will control the USB3 PHY to set it to low 948 * state, thus do not need to power off USB3 PHY again. 949 */ 950 debug_enter(); 951 debug_exit(); 952 953 return 0; 954 } 955 956 static int mvebu_a3700_comphy_sata_power_off(void) 957 { 958 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 959 uint32_t offset; 960 961 debug_enter(); 962 963 /* Set phy isolation mode */ 964 offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 965 comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 966 PHY_ISOLATE_MODE); 967 968 /* Power off PLL, Tx, Rx */ 969 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 970 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, 971 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 972 973 debug_exit(); 974 975 return 0; 976 } 977 978 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 979 { 980 int mode = COMPHY_GET_MODE(comphy_mode); 981 int err = 0; 982 983 debug_enter(); 984 985 if (!mode) { 986 /* 987 * The user did not specify which mode should be powered off. 988 * In this case we can identify this by reading the phy selector 989 * register. 990 */ 991 mode = mvebu_a3700_comphy_get_mode(comphy_index); 992 } 993 994 switch (mode) { 995 case(COMPHY_SGMII_MODE): 996 case(COMPHY_2500BASEX_MODE): 997 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 998 break; 999 case (COMPHY_USB3_MODE): 1000 case (COMPHY_USB3H_MODE): 1001 err = mvebu_a3700_comphy_usb3_power_off(); 1002 break; 1003 case (COMPHY_SATA_MODE): 1004 err = mvebu_a3700_comphy_sata_power_off(); 1005 break; 1006 1007 default: 1008 debug("comphy%d: power off is not implemented for mode %d\n", 1009 comphy_index, mode); 1010 break; 1011 } 1012 1013 debug_exit(); 1014 1015 return err; 1016 } 1017 1018 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 1019 { 1020 uint32_t data, addr; 1021 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 1022 int ret = 0; 1023 1024 debug_enter(); 1025 1026 /* Polling status */ 1027 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 1028 COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET); 1029 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 1030 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 1031 COMPHY_PLL_TIMEOUT, REG_32BIT); 1032 1033 if (data != 0) { 1034 ERROR("TX PLL is not locked\n"); 1035 ret = -ETIMEDOUT; 1036 } 1037 1038 debug_exit(); 1039 1040 return ret; 1041 } 1042 1043 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1044 { 1045 int mode = COMPHY_GET_MODE(comphy_mode); 1046 int ret = 0; 1047 1048 debug_enter(); 1049 1050 switch (mode) { 1051 case(COMPHY_SATA_MODE): 1052 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1053 break; 1054 1055 default: 1056 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1057 comphy_index, mode); 1058 ret = -EINVAL; 1059 break; 1060 } 1061 1062 debug_exit(); 1063 1064 return ret; 1065 } 1066