1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <debug.h> 9 #include <delay_timer.h> 10 #include <errno.h> 11 #include <mmio.h> 12 #include <mvebu.h> 13 #include <mvebu_def.h> 14 #include <spinlock.h> 15 #include "phy-comphy-3700.h" 16 #include "phy-comphy-common.h" 17 18 /* 19 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 20 * Linux is up to 0x178 so none will access it from Linux in runtime 21 * concurrently. 22 */ 23 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 24 25 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 26 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 27 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 28 29 /* 30 * Below address in used only for reading, therefore no problem with concurrent 31 * Linux access. 32 */ 33 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8) 34 #define MVEBU_XTAL_MODE_MASK BIT(9) 35 #define MVEBU_XTAL_MODE_OFFS 9 36 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 37 38 struct sgmii_phy_init_data_fix { 39 uint16_t addr; 40 uint16_t value; 41 }; 42 43 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 44 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 45 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 46 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 47 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 48 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 49 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 50 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 51 {0x104, 0x0C10} 52 }; 53 54 /* 40M1G25 mode init data */ 55 static uint16_t sgmii_phy_init[512] = { 56 /* 0 1 2 3 4 5 6 7 */ 57 /*-----------------------------------------------------------*/ 58 /* 8 9 A B C D E F */ 59 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 60 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 61 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 62 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 63 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 64 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 65 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 66 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 67 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 68 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 69 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 70 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 71 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 72 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 73 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 74 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 75 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 76 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 77 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 78 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 79 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 80 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 81 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 82 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 83 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 84 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 85 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 86 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 87 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 88 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 89 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 90 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 91 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 93 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 101 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 106 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 123 }; 124 125 /* returns reference clock in MHz (25 or 40) */ 126 static uint32_t get_ref_clk(void) 127 { 128 uint32_t val; 129 130 val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 131 MVEBU_XTAL_MODE_OFFS; 132 133 if (val == MVEBU_XTAL_CLOCK_25MHZ) 134 return 25; 135 else 136 return 40; 137 } 138 139 /* PHY selector configures with corresponding modes */ 140 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 141 uint32_t comphy_mode) 142 { 143 uint32_t reg; 144 int mode = COMPHY_GET_MODE(comphy_mode); 145 146 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 147 switch (mode) { 148 case (COMPHY_SATA_MODE): 149 /* SATA must be in Lane2 */ 150 if (comphy_index == COMPHY_LANE2) 151 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 152 else 153 goto error; 154 break; 155 156 case (COMPHY_SGMII_MODE): 157 case (COMPHY_HS_SGMII_MODE): 158 if (comphy_index == COMPHY_LANE0) 159 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 160 else if (comphy_index == COMPHY_LANE1) 161 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 162 else 163 goto error; 164 break; 165 166 case (COMPHY_USB3H_MODE): 167 case (COMPHY_USB3D_MODE): 168 case (COMPHY_USB3_MODE): 169 if (comphy_index == COMPHY_LANE2) 170 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 171 else if (comphy_index == COMPHY_LANE0) 172 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 173 else 174 goto error; 175 break; 176 177 case (COMPHY_PCIE_MODE): 178 /* PCIE must be in Lane1 */ 179 if (comphy_index == COMPHY_LANE1) 180 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 181 else 182 goto error; 183 break; 184 185 default: 186 goto error; 187 } 188 189 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 190 return; 191 error: 192 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 193 } 194 195 /* It is only used for SATA and USB3 on comphy lane2. */ 196 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 197 uint16_t mask, int mode) 198 { 199 /* 200 * When Lane 2 PHY is for USB3, access the PHY registers 201 * through indirect Address and Data registers: 202 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 203 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 204 * within the SATA Host Controller registers, Lane 2 base register 205 * offset is 0x200 206 */ 207 if (mode == COMPHY_UNUSED) 208 return; 209 210 if (mode == COMPHY_SATA_MODE) 211 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 212 else 213 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 214 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 215 216 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 217 } 218 219 /* It is only used USB3 direct access not on comphy lane2. */ 220 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 221 uint16_t data, uint16_t mask, int mode) 222 { 223 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 224 } 225 226 static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode, 227 uintptr_t sd_ip_addr) 228 { 229 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 230 int addr, fix_idx; 231 uint16_t val; 232 233 fix_idx = 0; 234 for (addr = 0; addr < 512; addr++) { 235 /* 236 * All PHY register values are defined in full for 3.125Gbps 237 * SERDES speed. The values required for 1.25 Gbps are almost 238 * the same and only few registers should be "fixed" in 239 * comparison to 3.125 Gbps values. These register values are 240 * stored in "sgmii_phy_init_fix" array. 241 */ 242 if ((mode != COMPHY_SGMII_MODE) && 243 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 244 /* Use new value */ 245 val = sgmii_phy_init_fix[fix_idx].value; 246 if (fix_idx < fix_arr_sz) 247 fix_idx++; 248 } else { 249 val = sgmii_phy_init[addr]; 250 } 251 252 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 253 } 254 } 255 256 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 257 uint32_t comphy_mode) 258 { 259 int ret = 0; 260 uint32_t offset, data = 0, ref_clk; 261 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 262 int mode = COMPHY_GET_MODE(comphy_mode); 263 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 264 265 debug_enter(); 266 267 /* Configure phy selector for SATA */ 268 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 269 270 /* Clear phy isolation mode to make it work in normal mode */ 271 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 272 comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE, 273 mode); 274 275 /* 0. Check the Polarity invert bits */ 276 if (invert & COMPHY_POLARITY_TXD_INVERT) 277 data |= TXD_INVERT_BIT; 278 if (invert & COMPHY_POLARITY_RXD_INVERT) 279 data |= RXD_INVERT_BIT; 280 281 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 282 comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 283 RXD_INVERT_BIT, mode); 284 285 /* 1. Select 40-bit data width width */ 286 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 287 comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 288 SEL_DATA_WIDTH_MASK, mode); 289 290 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 291 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 292 if (get_ref_clk() == 40) 293 ref_clk = REF_CLOCK_SPEED_40M; 294 else 295 ref_clk = REF_CLOCK_SPEED_25M; 296 297 comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 298 REF_FREF_SEL_MASK | PHY_MODE_MASK, mode); 299 300 /* 3. Use maximum PLL rate (no power save) */ 301 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 302 comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 303 USE_MAX_PLL_RATE_BIT, mode); 304 305 /* 4. Reset reserved bit */ 306 comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 307 PHYCTRL_FRM_PIN_BIT, mode); 308 309 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 310 /* XXX: in U-Boot below sequence was executed in this place, in Linux 311 * not. Now it is done only in U-Boot before this comphy 312 * initialization - tests shows that it works ok, but in case of any 313 * future problem it is left for reference. 314 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 315 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 316 */ 317 318 /* Wait for > 55 us to allow PLL be enabled */ 319 udelay(PLL_SET_DELAY_US); 320 321 /* Polling status */ 322 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 323 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 324 325 ret = polling_with_timeout(comphy_indir_regs + 326 COMPHY_LANE2_INDIR_DATA_OFFSET, 327 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 328 COMPHY_PLL_TIMEOUT, REG_32BIT); 329 330 debug_exit(); 331 332 return ret; 333 } 334 335 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 336 uint32_t comphy_mode) 337 { 338 int ret = 0; 339 uint32_t mask, data, offset; 340 uintptr_t sd_ip_addr; 341 int mode = COMPHY_GET_MODE(comphy_mode); 342 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 343 344 debug_enter(); 345 346 /* Set selector */ 347 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 348 349 /* Serdes IP Base address 350 * COMPHY Lane0 -- USB3/GBE1 351 * COMPHY Lane1 -- PCIe/GBE0 352 */ 353 if (comphy_index == COMPHY_LANE0) { 354 /* Get usb3 and gbe */ 355 sd_ip_addr = USB3_GBE1_PHY; 356 } else 357 sd_ip_addr = COMPHY_SD_ADDR; 358 359 /* 360 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 361 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 362 * PHY TXP/TXN output to idle state during PHY initialization 363 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 364 */ 365 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 366 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 367 PIN_PU_TX_BIT; 368 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 369 reg_set(offset, data, mask); 370 371 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 372 data = 0; 373 mask = PIN_RESET_COMPHY_BIT; 374 reg_set(offset, data, mask); 375 376 /* 377 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 378 * bit rate 379 */ 380 if (mode == COMPHY_SGMII_MODE) { 381 /* SGMII 1G, SerDes speed 1.25G */ 382 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 383 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 384 } else if (mode == COMPHY_HS_SGMII_MODE) { 385 /* HS SGMII (2.5G), SerDes speed 3.125G */ 386 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 387 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 388 } else { 389 /* Other rates are not supported */ 390 ERROR("unsupported SGMII speed on comphy lane%d\n", 391 comphy_index); 392 return -EINVAL; 393 } 394 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 395 reg_set(offset, data, mask); 396 397 /* 398 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 399 * start SW programming. 400 */ 401 mdelay(10); 402 403 /* 7. Program COMPHY register PHY_MODE */ 404 data = PHY_MODE_SGMII; 405 mask = PHY_MODE_MASK; 406 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 407 408 /* 409 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 410 * source 411 */ 412 data = 0; 413 mask = PHY_REF_CLK_SEL; 414 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 415 416 /* 417 * 9. Set correct reference clock frequency in COMPHY register 418 * REF_FREF_SEL. 419 */ 420 if (get_ref_clk() == 40) 421 data = REF_CLOCK_SPEED_50M; 422 else 423 data = REF_CLOCK_SPEED_25M; 424 425 mask = REF_FREF_SEL_MASK; 426 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 427 428 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 429 * This step is mentioned in the flow received from verification team. 430 * However the PHY_GEN_MAX value is only meaningful for other interfaces 431 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 432 * speed 2.5/5 Gbps 433 */ 434 435 /* 436 * 11. Program COMPHY register SEL_BITS to set correct parallel data 437 * bus width 438 */ 439 data = DATA_WIDTH_10BIT; 440 mask = SEL_DATA_WIDTH_MASK; 441 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 442 443 /* 444 * 12. As long as DFE function needs to be enabled in any mode, 445 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 446 * for real chip during COMPHY power on. 447 * The step 14 exists (and empty) in the original initialization flow 448 * obtained from the verification team. According to the functional 449 * specification DFE_UPDATE_EN already has the default value 0x3F 450 */ 451 452 /* 453 * 13. Program COMPHY GEN registers. 454 * These registers should be programmed based on the lab testing result 455 * to achieve optimal performance. Please contact the CEA group to get 456 * the related GEN table during real chip bring-up. We only required to 457 * run though the entire registers programming flow defined by 458 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 459 * 25 MHz the default values stored in PHY registers are OK. 460 */ 461 debug("Running C-DPI phy init %s mode\n", 462 mode == COMPHY_HS_SGMII_MODE ? "2G5" : "1G"); 463 if (get_ref_clk() == 40) 464 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr); 465 466 /* 467 * 14. [Simulation Only] should not be used for real chip. 468 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 469 * (R02h[9]) to 1 to shorten COMPHY simulation time. 470 */ 471 472 /* 473 * 15. [Simulation Only: should not be used for real chip] 474 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 475 * simulation time. 476 */ 477 478 /* 479 * 16. Check the PHY Polarity invert bit 480 */ 481 data = 0x0; 482 if (invert & COMPHY_POLARITY_TXD_INVERT) 483 data |= TXD_INVERT_BIT; 484 if (invert & COMPHY_POLARITY_RXD_INVERT) 485 data |= RXD_INVERT_BIT; 486 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0); 487 488 /* 489 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 490 * start PHY power up sequence. All the PHY register programming should 491 * be done before PIN_PU_PLL=1. There should be no register programming 492 * for normal PHY operation from this point. 493 */ 494 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 495 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 496 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 497 498 /* 499 * 18. Wait for PHY power up sequence to finish by checking output ports 500 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 501 */ 502 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 503 COMPHY_PHY_STATUS_OFFSET(comphy_index), 504 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 505 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 506 COMPHY_PLL_TIMEOUT, REG_32BIT); 507 if (ret) 508 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 509 510 /* 511 * 19. Set COMPHY input port PIN_TX_IDLE=0 512 */ 513 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 514 0x0, PIN_TX_IDLE_BIT); 515 516 /* 517 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 518 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 519 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 520 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 521 * refer to RX initialization part for details. 522 */ 523 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 524 PHY_RX_INIT_BIT, 0x0); 525 526 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 527 COMPHY_PHY_STATUS_OFFSET(comphy_index), 528 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 529 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 530 COMPHY_PLL_TIMEOUT, REG_32BIT); 531 if (ret) 532 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 533 534 535 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 536 COMPHY_PHY_STATUS_OFFSET(comphy_index), 537 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 538 COMPHY_PLL_TIMEOUT, REG_32BIT); 539 if (ret) 540 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 541 542 debug_exit(); 543 544 return ret; 545 } 546 547 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 548 uint32_t comphy_mode) 549 { 550 int ret = 0; 551 uintptr_t reg_base = 0; 552 uint32_t mask, data, addr, cfg, ref_clk; 553 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 554 uint16_t mask, int mode); 555 int mode = COMPHY_GET_MODE(comphy_mode); 556 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 557 558 debug_enter(); 559 560 /* Set phy seclector */ 561 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 562 563 /* Set usb3 reg access func, Lane2 is indirect access */ 564 if (comphy_index == COMPHY_LANE2) { 565 usb3_reg_set = &comphy_set_indirect; 566 reg_base = COMPHY_INDIRECT_REG; 567 } else { 568 /* Get the direct access register resource and map */ 569 usb3_reg_set = &comphy_usb3_set_direct; 570 reg_base = USB3_GBE1_PHY; 571 } 572 573 /* 574 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 575 * register belong to UTMI module, so it is set in UTMI phy driver. 576 */ 577 578 /* 579 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 580 */ 581 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 582 CFG_TX_ALIGN_POS_MASK; 583 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 584 mask, mode); 585 586 /* 587 * 2. Set BIT0: enable transmitter in high impedance mode 588 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 589 * Set BIT6: Tx detect Rx at HiZ mode 590 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 591 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 592 */ 593 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 594 TX_ELEC_IDLE_MODE_EN; 595 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 596 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); 597 598 /* 599 * 3. Set Spread Spectrum Clock Enabled 600 */ 601 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 602 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode); 603 604 /* 605 * 4. Set Override Margining Controls From the MAC: 606 * Use margining signals from lane configuration 607 */ 608 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 609 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode); 610 611 /* 612 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 613 * set Mode Clock Source = PCLK is generated from REFCLK 614 */ 615 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 616 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 617 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode); 618 619 /* 620 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 621 */ 622 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 623 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode); 624 625 /* 626 * 7. Unset G3 Spread Spectrum Clock Amplitude 627 * set G3 TX and RX Register Master Current Select 628 */ 629 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 630 RSVD_PH03FH_6_0_MASK; 631 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 632 G3_VREG_RXTX_MAS_ISET_60U, mask, mode); 633 634 /* 635 * 8. Check crystal jumper setting and program the Power and PLL Control 636 * accordingly Change RX wait 637 */ 638 if (get_ref_clk() == 40) { 639 ref_clk = REF_CLOCK_SPEED_40M; 640 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 641 642 } else { 643 /* 25 MHz */ 644 ref_clk = USB3_REF_CLOCK_SPEED_25M; 645 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 646 } 647 648 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 649 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 650 REF_FREF_SEL_MASK; 651 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 652 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 653 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode); 654 655 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 656 CFG_PM_RXDLOZ_WAIT_MASK; 657 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 658 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode); 659 660 /* 661 * 9. Enable idle sync 662 */ 663 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 664 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK, 665 mode); 666 667 /* 668 * 10. Enable the output of 500M clock 669 */ 670 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 671 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK, 672 mode); 673 674 /* 675 * 11. Set 20-bit data width 676 */ 677 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 678 REG_16_BIT_MASK, mode); 679 680 /* 681 * 12. Override Speed_PLL value and use MAC PLL 682 */ 683 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 684 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 685 REG_16_BIT_MASK, mode); 686 687 /* 688 * 13. Check the Polarity invert bit 689 */ 690 if (invert & COMPHY_POLARITY_TXD_INVERT) 691 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT, 692 TXD_INVERT_BIT, mode); 693 if (invert & COMPHY_POLARITY_RXD_INVERT) 694 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT, 695 RXD_INVERT_BIT, mode); 696 697 /* 698 * 14. Set max speed generation to USB3.0 5Gbps 699 */ 700 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 701 PHY_GEN_MAX_MASK, mode); 702 703 /* 704 * 15. Set capacitor value for FFE gain peaking to 0xF 705 */ 706 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 707 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK, 708 mode); 709 710 /* 711 * 16. Release SW reset 712 */ 713 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 714 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 715 REG_16_BIT_MASK, mode); 716 717 /* Wait for > 55 us to allow PCLK be enabled */ 718 udelay(PLL_SET_DELAY_US); 719 720 if (comphy_index == COMPHY_LANE2) { 721 data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; 722 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 723 data); 724 725 addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; 726 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 727 COMPHY_PLL_TIMEOUT, REG_32BIT); 728 } else { 729 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 730 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 731 COMPHY_PLL_TIMEOUT, REG_16BIT); 732 } 733 if (ret) 734 ERROR("Failed to lock USB3 PLL\n"); 735 736 debug_exit(); 737 738 return ret; 739 } 740 741 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 742 uint32_t comphy_mode) 743 { 744 int ret; 745 uint32_t ref_clk; 746 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 747 748 debug_enter(); 749 750 /* 1. Enable max PLL. */ 751 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 752 USE_MAX_PLL_RATE_EN, 0x0); 753 754 /* 2. Select 20 bit SERDES interface. */ 755 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 756 CFG_SEL_20B, 0); 757 758 /* 3. Force to use reg setting for PCIe mode */ 759 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 760 SEL_BITS_PCIE_FORCE, 0); 761 762 /* 4. Change RX wait */ 763 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 764 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 765 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 766 CFG_PM_RXDLOZ_WAIT_MASK)); 767 768 /* 5. Enable idle sync */ 769 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 770 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 771 772 /* 6. Enable the output of 100M/125M/500M clock */ 773 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 774 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN, 775 REG_16_BIT_MASK); 776 777 /* 778 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 779 * PCI-E driver 780 */ 781 782 /* 783 * 8. Check crystal jumper setting and program the Power and PLL 784 * Control accordingly 785 */ 786 787 if (get_ref_clk() == 40) 788 ref_clk = REF_CLOCK_SPEED_40M; 789 else 790 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 791 792 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 793 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 794 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 795 REG_16_BIT_MASK); 796 797 /* 9. Override Speed_PLL value and use MAC PLL */ 798 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 799 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 800 801 /* 10. Check the Polarity invert bit */ 802 if (invert & COMPHY_POLARITY_TXD_INVERT) 803 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, 804 TXD_INVERT_BIT, 0x0); 805 806 if (invert & COMPHY_POLARITY_RXD_INVERT) 807 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, 808 RXD_INVERT_BIT, 0x0); 809 810 /* 11. Release SW reset */ 811 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 812 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 813 SOFT_RESET | MODE_REFDIV); 814 815 /* Wait for > 55 us to allow PCLK be enabled */ 816 udelay(PLL_SET_DELAY_US); 817 818 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 819 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 820 COMPHY_PLL_TIMEOUT, REG_16BIT); 821 if (ret) 822 ERROR("Failed to lock PCIE PLL\n"); 823 824 debug_exit(); 825 826 return ret; 827 } 828 829 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 830 { 831 int mode = COMPHY_GET_MODE(comphy_mode); 832 int ret = 0; 833 834 debug_enter(); 835 836 switch (mode) { 837 case(COMPHY_SATA_MODE): 838 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 839 comphy_mode); 840 break; 841 case(COMPHY_SGMII_MODE): 842 case(COMPHY_HS_SGMII_MODE): 843 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 844 comphy_mode); 845 break; 846 case (COMPHY_USB3_MODE): 847 case (COMPHY_USB3H_MODE): 848 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 849 comphy_mode); 850 break; 851 case (COMPHY_PCIE_MODE): 852 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 853 comphy_mode); 854 break; 855 default: 856 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 857 ret = -EINVAL; 858 break; 859 } 860 861 debug_exit(); 862 863 return ret; 864 } 865 866 static int mvebu_a3700_comphy_usb3_power_off(void) 867 { 868 /* 869 * Currently the USB3 MAC will control the USB3 PHY to set it to low 870 * state, thus do not need to power off USB3 PHY again. 871 */ 872 debug_enter(); 873 debug_exit(); 874 875 return 0; 876 } 877 878 static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode) 879 { 880 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 881 int mode = COMPHY_GET_MODE(comphy_mode); 882 uint32_t offset; 883 884 debug_enter(); 885 886 /* Set phy isolation mode */ 887 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 888 comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 889 PHY_ISOLATE_MODE, mode); 890 891 /* Power off PLL, Tx, Rx */ 892 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 893 comphy_set_indirect(comphy_indir_regs, offset, 0, 894 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode); 895 896 debug_exit(); 897 898 return 0; 899 } 900 901 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 902 { 903 int mode = COMPHY_GET_MODE(comphy_mode); 904 int err = 0; 905 906 debug_enter(); 907 908 switch (mode) { 909 case (COMPHY_USB3_MODE): 910 case (COMPHY_USB3H_MODE): 911 err = mvebu_a3700_comphy_usb3_power_off(); 912 break; 913 case (COMPHY_SATA_MODE): 914 err = mvebu_a3700_comphy_sata_power_off(comphy_mode); 915 break; 916 917 default: 918 debug("comphy%d: power off is not implemented for mode %d\n", 919 comphy_index, mode); 920 break; 921 } 922 923 debug_exit(); 924 925 return err; 926 } 927 928 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 929 { 930 uint32_t data, addr; 931 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 932 int ret = 0; 933 934 debug_enter(); 935 936 /* Polling status */ 937 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 938 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 939 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 940 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 941 COMPHY_PLL_TIMEOUT, REG_32BIT); 942 943 if (data != 0) { 944 ERROR("TX PLL is not locked\n"); 945 ret = -ETIMEDOUT; 946 } 947 948 debug_exit(); 949 950 return ret; 951 } 952 953 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 954 { 955 int mode = COMPHY_GET_MODE(comphy_mode); 956 int ret = 0; 957 958 debug_enter(); 959 960 switch (mode) { 961 case(COMPHY_SATA_MODE): 962 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 963 break; 964 965 default: 966 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 967 comphy_index, mode); 968 ret = -EINVAL; 969 break; 970 } 971 972 debug_exit(); 973 974 return ret; 975 } 976