1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright 2025 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef IMX_USDHC_H 9 #define IMX_USDHC_H 10 11 #include <drivers/mmc.h> 12 13 typedef struct imx_usdhc_params { 14 uintptr_t reg_base; 15 unsigned int clk_rate; 16 unsigned int bus_width; 17 unsigned int flags; 18 } imx_usdhc_params_t; 19 20 void imx_usdhc_init(imx_usdhc_params_t *params, 21 struct mmc_device_info *mmc_dev_info); 22 23 /* iMX MMC registers definition */ 24 #define DSADDR 0x000U 25 #define BLKATT 0x004U 26 #define CMDARG 0x008U 27 #define CMDRSP0 0x010U 28 #define CMDRSP1 0x014U 29 #define CMDRSP2 0x018U 30 #define CMDRSP3 0x01cU 31 32 #define XFERTYPE 0x00cU 33 #define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U) 34 #define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U) 35 #define XFERTYPE_CMDTYP_ABORT (3U << 22U) 36 #define XFERTYPE_DPSEL BIT_32(21U) 37 #define XFERTYPE_CICEN BIT_32(20U) 38 #define XFERTYPE_CCCEN BIT_32(19U) 39 #define XFERTYPE_RSPTYP_136 BIT_32(16U) 40 #define XFERTYPE_RSPTYP_48 BIT_32(17U) 41 #define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U)) 42 43 #define PSTATE 0x024U 44 #define PSTATE_DAT0 BIT_32(24U) 45 #define PSTATE_DLA BIT_32(2U) 46 #define PSTATE_CDIHB BIT_32(1U) 47 #define PSTATE_CIHB BIT_32(0U) 48 49 #define PROTCTRL 0x028U 50 #define PROTCTRL_LE BIT_32(5U) 51 #define PROTCTRL_WIDTH_4 BIT_32(1U) 52 #define PROTCTRL_WIDTH_8 BIT_32(2U) 53 #define PROTCTRL_WIDTH_MASK 0x6U 54 55 #define SYSCTRL 0x02cU 56 #define SYSCTRL_RSTD BIT_32(26U) 57 #define SYSCTRL_RSTC BIT_32(25U) 58 #define SYSCTRL_RSTA BIT_32(24U) 59 #define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U) 60 #define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U) 61 #define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U) 62 63 #define INTSTAT 0x030U 64 #define INTSTAT_DMAE BIT_32(28U) 65 #define INTSTAT_DEBE BIT_32(22U) 66 #define INTSTAT_DCE BIT_32(21U) 67 #define INTSTAT_DTOE BIT_32(20U) 68 #define INTSTAT_CIE BIT_32(19U) 69 #define INTSTAT_CEBE BIT_32(18U) 70 #define INTSTAT_CCE BIT_32(17U) 71 #define INTSTAT_DINT BIT_32(3U) 72 #define INTSTAT_BGE BIT_32(2U) 73 #define INTSTAT_TC BIT_32(1U) 74 #define INTSTAT_CC BIT_32(0U) 75 #define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE) 76 #define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \ 77 INTSTAT_DTOE) 78 #define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC) 79 80 #define INTSTATEN 0x034U 81 #define INTSTATEN_DEBE BIT_32(22U) 82 #define INTSTATEN_DCE BIT_32(21U) 83 #define INTSTATEN_DTOE BIT_32(20U) 84 #define INTSTATEN_CIE BIT_32(19U) 85 #define INTSTATEN_CEBE BIT_32(18U) 86 #define INTSTATEN_CCE BIT_32(17U) 87 #define INTSTATEN_CTOE BIT_32(16U) 88 #define INTSTATEN_CINT BIT_32(8U) 89 #define INTSTATEN_BRR BIT_32(5U) 90 #define INTSTATEN_BWR BIT_32(4U) 91 #define INTSTATEN_DINT BIT_32(3U) 92 #define INTSTATEN_TC BIT_32(1U) 93 #define INTSTATEN_CC BIT_32(0U) 94 #define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \ 95 INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \ 96 INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \ 97 INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \ 98 INTSTATEN_DEBE) 99 100 #define INTSIGEN 0x038U 101 102 #define WATERMARKLEV 0x044U 103 #define WMKLV_RD_MASK GENMASK_32(7U, 0U) 104 #define WMKLV_WR_MASK GENMASK_32(23U, 16U) 105 #define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK) 106 107 #define MIXCTRL 0x048U 108 #define MIXCTRL_MSBSEL BIT_32(5U) 109 #define MIXCTRL_DTDSEL BIT_32(4U) 110 #define MIXCTRL_DDREN BIT_32(3U) 111 #define MIXCTRL_AC12EN BIT_32(2U) 112 #define MIXCTRL_BCEN BIT_32(1U) 113 #define MIXCTRL_DMAEN BIT_32(0U) 114 #define MIXCTRL_DATMASK 0x7fU 115 116 #define DLLCTRL 0x060U 117 118 #define CLKTUNECTRLSTS 0x068U 119 120 #define VENDSPEC 0x0c0U 121 #define VENDSPEC_RSRV1 BIT_32(29U) 122 #define VENDSPEC_CARD_CLKEN BIT_32(14U) 123 #define VENDSPEC_PER_CLKEN BIT_32(13U) 124 #define VENDSPEC_AHB_CLKEN BIT_32(12U) 125 #define VENDSPEC_IPG_CLKEN BIT_32(11U) 126 #define VENDSPEC_AC12_CHKBUSY BIT_32(3U) 127 #define VENDSPEC_EXTDMA BIT_32(0U) 128 #define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \ 129 VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \ 130 VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \ 131 VENDSPEC_EXTDMA) 132 133 #define MMCBOOT 0x0c4U 134 135 #define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set)) 136 #define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear)) 137 #define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set)) 138 139 #endif /* IMX_USDHC_H */ 140