1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright 2025 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <string.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <lib/mmio.h> 18 19 #include <imx_usdhc.h> 20 21 /* These masks represent the commands which involve a data transfer. */ 22 #define ADTC_MASK_SD (BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\ 23 BIT_32(24U) | BIT_32(25U)) 24 #define ADTC_MASK_ACMD (BIT_64(51U)) 25 26 static void imx_usdhc_initialize(void); 27 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd); 28 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width); 29 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size); 30 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size); 31 static int imx_usdhc_write(int lba, uintptr_t buf, size_t size); 32 33 static const struct mmc_ops imx_usdhc_ops = { 34 .init = imx_usdhc_initialize, 35 .send_cmd = imx_usdhc_send_cmd, 36 .set_ios = imx_usdhc_set_ios, 37 .prepare = imx_usdhc_prepare, 38 .read = imx_usdhc_read, 39 .write = imx_usdhc_write, 40 }; 41 42 static imx_usdhc_params_t imx_usdhc_params; 43 44 #define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000) 45 static void imx_usdhc_set_clk(int clk) 46 { 47 int div = 1; 48 int pre_div = 1; 49 unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE; 50 uintptr_t reg_base = imx_usdhc_params.reg_base; 51 52 assert(clk > 0); 53 54 while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256) 55 pre_div *= 2; 56 57 while (sdhc_clk / div > clk && div < 16) 58 div++; 59 60 pre_div >>= 1; 61 div -= 1; 62 clk = (pre_div << 8) | (div << 4); 63 64 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); 65 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); 66 udelay(10000); 67 68 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); 69 } 70 71 static void imx_usdhc_initialize(void) 72 { 73 unsigned int timeout = 10000; 74 uintptr_t reg_base = imx_usdhc_params.reg_base; 75 76 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); 77 78 /* reset the controller */ 79 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); 80 81 /* wait for reset done */ 82 while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) { 83 if (!timeout) 84 ERROR("IMX MMC reset timeout.\n"); 85 timeout--; 86 } 87 88 mmio_write_32(reg_base + MMCBOOT, 0); 89 mmio_write_32(reg_base + MIXCTRL, 0); 90 mmio_write_32(reg_base + CLKTUNECTRLSTS, 0); 91 92 mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT); 93 mmio_write_32(reg_base + DLLCTRL, 0); 94 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN); 95 96 /* Set the initial boot clock rate */ 97 imx_usdhc_set_clk(MMC_BOOT_CLK_RATE); 98 udelay(100); 99 100 /* Clear read/write ready status */ 101 mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR); 102 103 /* configure as little endian */ 104 mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE); 105 106 /* Set timeout to the maximum value */ 107 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK, 108 SYSCTRL_TIMEOUT(15)); 109 110 /* set wartermark level as 16 for safe for MMC */ 111 mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16)); 112 } 113 114 #define FSL_CMD_RETRIES 1000 115 116 static bool is_data_transfer_to_card(const struct mmc_cmd *cmd) 117 { 118 unsigned int cmd_idx = cmd->cmd_idx; 119 120 return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25)); 121 } 122 123 static bool is_data_transfer_cmd(const struct mmc_cmd *cmd) 124 { 125 uintptr_t reg_base = imx_usdhc_params.reg_base; 126 unsigned int cmd_idx = cmd->cmd_idx; 127 uint32_t xfer_type; 128 129 xfer_type = mmio_read_32(reg_base + XFERTYPE); 130 131 if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) { 132 return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL; 133 } 134 135 if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) { 136 return true; 137 } 138 139 return false; 140 } 141 142 static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype) 143 { 144 *xfertype = XFERTYPE_CMD(cmd->cmd_idx); 145 146 switch (cmd->resp_type) { 147 case MMC_RESPONSE_R2: 148 *xfertype |= XFERTYPE_RSPTYP_136; 149 *xfertype |= XFERTYPE_CCCEN; 150 break; 151 case MMC_RESPONSE_R4: 152 *xfertype |= XFERTYPE_RSPTYP_48; 153 break; 154 case MMC_RESPONSE_R6: 155 *xfertype |= XFERTYPE_RSPTYP_48; 156 *xfertype |= XFERTYPE_CICEN; 157 *xfertype |= XFERTYPE_CCCEN; 158 break; 159 case MMC_RESPONSE_R1B: 160 *xfertype |= XFERTYPE_RSPTYP_48_BUSY; 161 *xfertype |= XFERTYPE_CICEN; 162 *xfertype |= XFERTYPE_CCCEN; 163 break; 164 default: 165 ERROR("Invalid CMD response: %u\n", cmd->resp_type); 166 return -EINVAL; 167 } 168 169 if (data) { 170 *xfertype |= XFERTYPE_DPSEL; 171 } 172 173 return 0; 174 } 175 176 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd) 177 { 178 uintptr_t reg_base = imx_usdhc_params.reg_base; 179 unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE; 180 unsigned int mixctl = 0, multiple = 0; 181 unsigned int cmd_retries = 0; 182 uint32_t xfertype; 183 bool data; 184 int err = 0; 185 186 assert(cmd); 187 188 data = is_data_transfer_cmd(cmd); 189 190 err = get_xfr_type(cmd, data, &xfertype); 191 if (err != 0) { 192 return err; 193 } 194 195 /* clear all irq status */ 196 mmio_write_32(reg_base + INTSTAT, 0xffffffff); 197 198 /* Wait for the bus to be idle */ 199 do { 200 state = mmio_read_32(reg_base + PSTATE); 201 } while (state & (PSTATE_CDIHB | PSTATE_CIHB)); 202 203 while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA) 204 ; 205 206 mmio_write_32(reg_base + INTSIGEN, 0); 207 udelay(1000); 208 209 switch (cmd->cmd_idx) { 210 case MMC_CMD(18): 211 multiple = 1; 212 break; 213 case MMC_CMD(25): 214 multiple = 1; 215 /* for data op flag */ 216 /* fallthrough */ 217 break; 218 default: 219 break; 220 } 221 222 if (multiple) { 223 mixctl |= MIXCTRL_MSBSEL; 224 mixctl |= MIXCTRL_BCEN; 225 } 226 227 if (data) { 228 mixctl |= MIXCTRL_DMAEN; 229 } 230 231 if (!is_data_transfer_to_card(cmd)) { 232 mixctl |= MIXCTRL_DTDSEL; 233 } 234 235 /* Send the command */ 236 mmio_write_32(reg_base + CMDARG, cmd->cmd_arg); 237 mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl); 238 mmio_write_32(reg_base + XFERTYPE, xfertype); 239 240 /* Wait for the command done */ 241 do { 242 state = mmio_read_32(reg_base + INTSTAT); 243 if (cmd_retries) 244 udelay(1); 245 } while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES); 246 247 if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) { 248 if (cmd_retries == FSL_CMD_RETRIES) 249 err = -ETIMEDOUT; 250 else 251 err = -EIO; 252 ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n", 253 cmd->cmd_idx, state, err); 254 goto out; 255 } 256 257 /* Copy the response to the response buffer */ 258 if (cmd->resp_type & MMC_RSP_136) { 259 unsigned int cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 260 261 cmdrsp3 = mmio_read_32(reg_base + CMDRSP3); 262 cmdrsp2 = mmio_read_32(reg_base + CMDRSP2); 263 cmdrsp1 = mmio_read_32(reg_base + CMDRSP1); 264 cmdrsp0 = mmio_read_32(reg_base + CMDRSP0); 265 cmd->resp_data[3] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 266 cmd->resp_data[2] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 267 cmd->resp_data[1] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 268 cmd->resp_data[0] = (cmdrsp0 << 8); 269 } else { 270 cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0); 271 } 272 273 /* Wait until all of the blocks are transferred */ 274 if (data) { 275 flags = DATA_COMPLETE; 276 do { 277 state = mmio_read_32(reg_base + INTSTAT); 278 279 if (state & (INTSTATEN_DTOE | DATA_ERR)) { 280 err = -EIO; 281 ERROR("imx_usdhc mmc data state 0x%x\n", state); 282 goto out; 283 } 284 } while ((state & flags) != flags); 285 } 286 287 out: 288 /* Reset CMD and DATA on error */ 289 if (err) { 290 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC); 291 while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC) 292 ; 293 294 if (data) { 295 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD); 296 while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD) 297 ; 298 } 299 } 300 301 /* clear all irq status */ 302 mmio_write_32(reg_base + INTSTAT, 0xffffffff); 303 304 return err; 305 } 306 307 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width) 308 { 309 uintptr_t reg_base = imx_usdhc_params.reg_base; 310 311 imx_usdhc_set_clk(clk); 312 313 if (width == MMC_BUS_WIDTH_4) 314 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, 315 PROTCTRL_WIDTH_4); 316 else if (width == MMC_BUS_WIDTH_8) 317 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, 318 PROTCTRL_WIDTH_8); 319 320 return 0; 321 } 322 323 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size) 324 { 325 uintptr_t reg_base = imx_usdhc_params.reg_base; 326 327 mmio_write_32(reg_base + DSADDR, buf); 328 mmio_write_32(reg_base + BLKATT, 329 (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE); 330 331 return 0; 332 } 333 334 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size) 335 { 336 return 0; 337 } 338 339 static int imx_usdhc_write(int lba, uintptr_t buf, size_t size) 340 { 341 return 0; 342 } 343 344 void imx_usdhc_init(imx_usdhc_params_t *params, 345 struct mmc_device_info *mmc_dev_info) 346 { 347 assert((params != 0) && 348 ((params->reg_base & MMC_BLOCK_MASK) == 0) && 349 ((params->bus_width == MMC_BUS_WIDTH_1) || 350 (params->bus_width == MMC_BUS_WIDTH_4) || 351 (params->bus_width == MMC_BUS_WIDTH_8))); 352 353 memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t)); 354 mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width, 355 params->flags, mmc_dev_info); 356 } 357