1 /*
2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <stdbool.h>
11 #include <stddef.h>
12 #include <string.h>
13
14 #include <arch_helpers.h>
15 #include <common/debug.h>
16 #include <drivers/cadence/cdns_sdmmc.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/mmc.h>
19 #include <lib/mmio.h>
20 #include <lib/utils.h>
21
22 void cdns_init(void);
23 int cdns_send_cmd(struct mmc_cmd *cmd);
24 int cdns_set_ios(unsigned int clk, unsigned int width);
25 int cdns_prepare(int lba, uintptr_t buf, size_t size);
26 int cdns_read(int lba, uintptr_t buf, size_t size);
27 int cdns_write(int lba, uintptr_t buf, size_t size);
28
29 const struct mmc_ops cdns_sdmmc_ops = {
30 .init = cdns_init,
31 .send_cmd = cdns_send_cmd,
32 .set_ios = cdns_set_ios,
33 .prepare = cdns_prepare,
34 .read = cdns_read,
35 .write = cdns_write,
36 };
37 void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uintptr_t buf,
38 size_t size);
39 struct cdns_sdmmc_params cdns_params;
40 struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
41 struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
42 struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(8);
43
44 bool data_cmd;
45
cdns_wait_ics(uint16_t timeout,uint32_t cdn_srs_res)46 int cdns_wait_ics(uint16_t timeout, uint32_t cdn_srs_res)
47 {
48 /* Clock for sdmclk and sdclk */
49 uint32_t count = 0;
50 uint32_t data = 0;
51
52 /* Wait status command response ready */
53 do {
54 data = mmio_read_32(cdn_srs_res);
55 count++;
56
57 /* delay 300us to prevent CPU polling too frequently */
58 udelay(300);
59 if (count >= timeout) {
60 return -ETIMEDOUT;
61 }
62 } while ((data & (1 << SDMMC_CDN_ICS)) == 0);
63
64 return 0;
65 }
66
cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy * combo_phy_reg,struct cdns_sdmmc_sdhc * sdhc_reg)67 void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg,
68 struct cdns_sdmmc_sdhc *sdhc_reg)
69 {
70 /* Values are taken by the reference of cadence IP documents */
71 combo_phy_reg->cp_clk_wr_delay = 0;
72 combo_phy_reg->cp_clk_wrdqs_delay = 0;
73 combo_phy_reg->cp_data_select_oe_end = 1;
74 combo_phy_reg->cp_dll_bypass_mode = 1;
75 combo_phy_reg->cp_dll_locked_mode = 0;
76 combo_phy_reg->cp_dll_start_point = 254;
77 combo_phy_reg->cp_gate_cfg_always_on = 1;
78 combo_phy_reg->cp_io_mask_always_on = 0;
79 combo_phy_reg->cp_io_mask_end = 5;
80 combo_phy_reg->cp_io_mask_start = 0;
81 combo_phy_reg->cp_rd_del_sel = 52;
82 combo_phy_reg->cp_read_dqs_cmd_delay = 0;
83 combo_phy_reg->cp_read_dqs_delay = 0;
84 combo_phy_reg->cp_sw_half_cycle_shift = 0;
85 combo_phy_reg->cp_sync_method = 1;
86 combo_phy_reg->cp_underrun_suppress = 1;
87 combo_phy_reg->cp_use_ext_lpbk_dqs = 1;
88 combo_phy_reg->cp_use_lpbk_dqs = 1;
89 combo_phy_reg->cp_use_phony_dqs = 1;
90 combo_phy_reg->cp_use_phony_dqs_cmd = 1;
91
92 sdhc_reg->sdhc_extended_rd_mode = 1;
93 sdhc_reg->sdhc_extended_wr_mode = 1;
94 sdhc_reg->sdhc_hcsdclkadj = 3;
95 sdhc_reg->sdhc_idelay_val = 0;
96 sdhc_reg->sdhc_rdcmd_en = 1;
97 sdhc_reg->sdhc_rddata_en = 1;
98 sdhc_reg->sdhc_rw_compensate = 10;
99 sdhc_reg->sdhc_sdcfsh = 0;
100 sdhc_reg->sdhc_sdcfsl = 0;
101 sdhc_reg->sdhc_wrcmd0_dly = 1;
102 sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0;
103 sdhc_reg->sdhc_wrcmd1_dly = 0;
104 sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0;
105 sdhc_reg->sdhc_wrdata0_dly = 0;
106 sdhc_reg->sdhc_wrdata0_sdclk_dly = 0;
107 sdhc_reg->sdhc_wrdata1_dly = 0;
108 sdhc_reg->sdhc_wrdata1_sdclk_dly = 0;
109 }
110
cdns_program_phy_reg(struct cdns_sdmmc_combo_phy * combo_phy_reg,struct cdns_sdmmc_sdhc * sdhc_reg)111 int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
112 struct cdns_sdmmc_sdhc *sdhc_reg)
113 {
114 uint32_t value = 0;
115 int ret = 0;
116 uint32_t timeout = 0;
117
118 /* HRS00 - Software Reset */
119 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_HRS00), SDHC_CDNS_HRS00_SWR);
120
121 /* Waiting for SDHC_CDNS_HRS00_SWR reset */
122 timeout = TIMEOUT;
123 do {
124 udelay(250);
125 if (--timeout <= 0) {
126 NOTICE(" SDHC Software Reset failed!!!\n");
127 panic();
128 }
129 } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00) &
130 SDHC_CDNS_HRS00_SWR) == 1));
131
132 /* Step 1, switch on DLL_RESET */
133 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
134 value &= ~SDHC_PHY_SW_RESET;
135 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
136
137 /* program PHY_DQS_TIMING_REG */
138 value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) |
139 (CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) |
140 (CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) |
141 (CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd));
142 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
143 COMBO_PHY_REG + PHY_DQS_TIMING_REG,
144 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
145 if (ret != 0U) {
146 return ret;
147 }
148
149 /* program PHY_GATE_LPBK_CTRL_REG */
150 value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) |
151 (CP_SW_HALF_CYCLE_SHIFT(combo_phy_reg->cp_sw_half_cycle_shift)) |
152 (CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) |
153 (CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) |
154 (CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on));
155 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
156 COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG,
157 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
158 if (ret != 0U) {
159 return -ret;
160 }
161
162 /* program PHY_DLL_MASTER_CTRL_REG */
163 value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) | (2 << 20) |
164 (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point));
165 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
166 COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG,
167 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
168 if (ret != 0U) {
169 return ret;
170 }
171
172 /* program PHY_DLL_SLAVE_CTRL_REG */
173 value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) |
174 (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) |
175 (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) |
176 (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay));
177 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
178 COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG,
179 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
180 if (ret != 0U) {
181 return ret;
182 }
183
184 /* program PHY_CTRL_REG */
185 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS04, COMBO_PHY_REG + PHY_CTRL_REG);
186 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS05);
187
188 /* phony_dqs_timing=0 */
189 value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT);
190 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS05, value);
191
192 /* switch off DLL_RESET */
193 do {
194 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
195 value |= SDHC_PHY_SW_RESET;
196 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
197 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
198 /* polling PHY_INIT_COMPLETE */
199 } while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE);
200
201 /* program PHY_DQ_TIMING_REG */
202 value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) |
203 (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) |
204 (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) |
205 (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end));
206
207 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
208 COMBO_PHY_REG + PHY_DQ_TIMING_REG,
209 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
210 if (ret != 0U) {
211 return ret;
212 }
213
214 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
215 value |= (HRS_09_EXTENDED_RD_MODE | HRS_09_EXTENDED_WR_MODE |
216 HRS_09_RDCMD_EN | HRS_09_RDDATA_EN);
217 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
218
219 value = 0;
220 value = SDHC_HCSDCLKADJ(HRS_10_HCSDCLKADJ_VAL);
221 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS10, value);
222
223 value = 0;
224 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS16, value);
225
226 value = (10 << 16);
227 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS07, value);
228
229 return 0;
230 }
231
cdns_read(int lba,uintptr_t buf,size_t size)232 int cdns_read(int lba, uintptr_t buf, size_t size)
233 {
234 return 0;
235 }
236
cdns_write(int lba,uintptr_t buf,size_t size)237 int cdns_write(int lba, uintptr_t buf, size_t size)
238 {
239 return 0;
240 }
241
cdns_init(void)242 void cdns_init(void)
243 {
244 /* Dummy function pointer for cdns_init. */
245 }
246
cdns_prepare(int dma_start_addr,uintptr_t dma_buff,size_t size)247 int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size)
248 {
249 struct cdns_idmac_desc *cdns_desc_data;
250 assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) &&
251 (cdns_params.desc_size > 0));
252
253 cdns_desc_data = (struct cdns_idmac_desc *)cdns_params.desc_base;
254 sd_host_adma_prepare(cdns_desc_data, dma_buff, size);
255
256 return 0;
257 }
258
cdns_host_set_clk(uint32_t clk)259 void cdns_host_set_clk(uint32_t clk)
260 {
261 uint32_t ret = 0;
262 uint32_t sdclkfsval = 0;
263 uint32_t dtcvval = 0xE;
264
265 sdclkfsval = (cdns_params.sdmclk / 2) / clk;
266 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0);
267 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11,
268 (dtcvval << SDMMC_CDN_DTCV) | (sdclkfsval << SDMMC_CDN_SDCLKFS) |
269 (1 << SDMMC_CDN_ICE));
270
271 ret = cdns_wait_ics(5000, cdns_params.reg_base + SDHC_CDNS_SRS11);
272 if (ret != 0) {
273 ERROR("Waiting ICS timeout");
274 }
275 /* Enable DLL reset */
276 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
277 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & ~0x00000001);
278 /* Set extended_wr_mode */
279 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
280 (mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & 0xFFFFFFF7) |
281 (1 << EXTENDED_WR_MODE));
282 /* Release DLL reset */
283 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
284 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | PHY_SW_RESET_EN);
285 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
286 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | RDCMD_EN);
287
288 do {
289 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
290 } while (~mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) &
291 (PHY_INIT_COMPLETE_BIT));
292
293 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
294 (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) |
295 (1 << SDMMC_CDN_SDCE));
296
297 ret = cdns_wait_ics(5000, cdns_params.reg_base + SDHC_CDNS_SRS11);
298 if (ret != 0)
299 ERROR("Waiting ICS timeout");
300
301 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS13, 0xFFFFFFFF);
302 }
303
cdns_set_ios(unsigned int clk,unsigned int width)304 int cdns_set_ios(unsigned int clk, unsigned int width)
305 {
306 uint32_t _status = 0;
307
308 _status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
309 switch (width) {
310 case MMC_BUS_WIDTH_1:
311 _status &= ~(BIT4);
312 break;
313
314 case MMC_BUS_WIDTH_4:
315 _status |= BIT4;
316 break;
317
318 case MMC_BUS_WIDTH_8:
319 _status |= BIT8;
320 break;
321
322 default:
323 assert(0);
324 break;
325 }
326 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS10), _status);
327 cdns_host_set_clk(clk);
328
329 return 0;
330 }
331
cdns_sdmmc_write_sd_host_reg(uint32_t addr,uint32_t data)332 int cdns_sdmmc_write_sd_host_reg(uint32_t addr, uint32_t data)
333 {
334 uint32_t value = 0;
335
336 value = mmio_read_32(addr);
337 value &= ~SDHC_REG_MASK;
338 value |= data;
339 mmio_write_32(addr, value);
340 value = mmio_read_32(addr);
341
342 if (value != data) {
343 ERROR("SD host address is not set properly\n");
344 return -ENXIO;
345 }
346
347 return 0;
348 }
349
350
351
sd_host_oper_mode(enum sd_opr_modes opr_mode)352 void sd_host_oper_mode(enum sd_opr_modes opr_mode)
353 {
354
355 uint32_t reg = 0;
356
357 switch (opr_mode) {
358 case SD_HOST_OPR_MODE_HV4E_0_SDMA_32:
359 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
360 reg &= ~(DMA_SEL_BIT);
361 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
362 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
363 reg &= ~(HV4E | BIT_AD_64);
364 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
365 break;
366
367 case SD_HOST_OPR_MODE_HV4E_1_SDMA_32:
368 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
369 reg &= ~(DMA_SEL_BIT);
370 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
371 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
372 reg &= ~(HV4E | BIT_AD_64);
373 reg |= (HV4E);
374 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
375 break;
376
377 case SD_HOST_OPR_MODE_HV4E_1_SDMA_64:
378 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
379 reg &= ~(DMA_SEL_BIT);
380 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
381 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
382 reg |= (HV4E | BIT_AD_64);
383 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
384 break;
385
386 case SD_HOST_OPR_MODE_HV4E_0_ADMA_32:
387 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
388 reg &= ~(DMA_SEL_BIT);
389 reg |= DMA_SEL_BIT_2;
390 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
391 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
392 reg &= ~(HV4E | BIT_AD_64);
393 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
394 break;
395
396 case SD_HOST_OPR_MODE_HV4E_0_ADMA_64:
397 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
398 reg &= ~(DMA_SEL_BIT);
399 reg |= DMA_SEL_BIT_3;
400 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
401 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
402 reg &= ~(HV4E | BIT_AD_64);
403 reg |= BIT_AD_64;
404 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
405 break;
406
407 case SD_HOST_OPR_MODE_HV4E_1_ADMA_32:
408 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
409 reg &= ~(DMA_SEL_BIT);
410 reg |= DMA_SEL_BIT_2;
411 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
412 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
413 reg &= ~(HV4E | BIT_AD_64);
414 reg |= HV4E;
415 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
416 break;
417
418 case SD_HOST_OPR_MODE_HV4E_1_ADMA_64:
419 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
420 reg &= ~(DMA_SEL_BIT);
421 reg |= DMA_SEL_BIT_2;
422 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
423 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
424 reg |= (HV4E | BIT_AD_64);
425 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
426 break;
427 }
428 }
429
card_reset(bool power_enable)430 void card_reset(bool power_enable)
431 {
432 uint32_t reg_value = 0;
433
434 /* Reading SRS10 value before writing */
435 reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
436
437 if (power_enable == true) {
438 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
439 reg_value = ((1 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
440 } else {
441 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
442 }
443 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
444 }
445
high_speed_enable(bool mode)446 void high_speed_enable(bool mode)
447 {
448
449 uint32_t reg_value = 0;
450 /* Reading SRS10 value before writing */
451 reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
452
453 if (mode == true) {
454 reg_value |= HS_EN;
455 } else {
456 reg_value &= ~HS_EN;
457 }
458
459 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
460 }
461
cdns_reset(void)462 int cdns_reset(void)
463 {
464 volatile uint32_t data = 0;
465 uint32_t count = 0;
466
467 /* Software reset */
468 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_SRFA);
469 /* Wait status command response ready */
470 do {
471 data = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00);
472 count++;
473 if (count >= CDNS_TIMEOUT) {
474 return -ETIMEDOUT;
475 }
476 /* Wait for SRS11 */
477 } while (((SRS11_SRFA_CHK(data)) & 1) == 1);
478
479 return 0;
480 }
481
sdmmc_host_init(bool uhs2_enable)482 void sdmmc_host_init(bool uhs2_enable)
483 {
484 uint32_t timeout;
485
486 /* SRS11 - Host Control default value set */
487 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0x0);
488
489 /* Waiting for detect card */
490 timeout = TIMEOUT;
491 do {
492 udelay(250);
493 if (--timeout <= 0) {
494 NOTICE(" SDHC Card Detecion failed!!!\n");
495 panic();
496 }
497 } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & CHECK_CARD) == 0));
498
499 /* UHS2 Host setting */
500 if (uhs2_enable == true) {
501 /** need to implement*/
502 }
503
504 /* Card reset */
505
506 card_reset(1);
507 udelay(2500);
508 card_reset(0);
509 udelay(2500);
510 card_reset(1);
511 udelay(2500);
512
513 /* Enable Interrupt Flags*/
514 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS13), ~0);
515 high_speed_enable(true);
516 }
517
cdns_sd_host_init(struct cdns_sdmmc_combo_phy * mmc_combo_phy_reg,struct cdns_sdmmc_sdhc * mmc_sdhc_reg)518 int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg,
519 struct cdns_sdmmc_sdhc *mmc_sdhc_reg)
520 {
521 int ret = 0;
522
523 ret = cdns_reset();
524 if (ret != 0U) {
525 ERROR("Program phy reg init failed");
526 return ret;
527 }
528
529 ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
530 if (ret != 0U) {
531 ERROR("Program phy reg init failed");
532 return ret;
533 }
534 sdmmc_host_init(0);
535 cdns_host_set_clk(100000);
536
537 sd_host_oper_mode(SD_HOST_OPR_MODE_HV4E_0_ADMA_64);
538
539 return 0;
540 }
541
cdns_send_cmd(struct mmc_cmd * cmd)542 int cdns_send_cmd(struct mmc_cmd *cmd)
543 {
544 uint32_t cmd_flags = 0;
545 uint32_t timeout = 0;
546 uint32_t status_check = 0;
547 uint32_t mode = 0;
548 uint32_t status;
549
550 assert(cmd);
551
552 cmd_flags = CDNS_HOST_CMD_INHIBIT | CDNS_HOST_DATA_INHIBIT;
553
554 if ((cmd->cmd_idx == SD_STOP_TRANSMISSION) && (!data_cmd)) {
555 cmd_flags &= ~CDNS_HOST_DATA_INHIBIT;
556 }
557
558 timeout = TIMEOUT;
559 do {
560 udelay(100);
561 if (--timeout <= 0) {
562 udelay(50);
563 NOTICE("Timeout occur data and cmd line %x\n",
564 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09));
565 panic();
566 }
567 } while ((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & (cmd_flags)));
568
569 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, 0xFFFFFFFF);
570 cmd_flags = 0;
571 cmd_flags = (cmd->cmd_idx) << COM_IDX;
572
573 if ((cmd->resp_type & MMC_RSP_136) != 0) {
574 cmd_flags |= RES_TYPE_SEL_136;
575 } else if (((cmd->resp_type & MMC_RSP_48) != 0) &&
576 ((cmd->resp_type & MMC_RSP_BUSY) != 0)) {
577 cmd_flags |= RES_TYPE_SEL_48_B;
578 } else if ((cmd->resp_type & MMC_RSP_48) != 0) {
579 cmd_flags |= RES_TYPE_SEL_48;
580 } else {
581 cmd_flags &= ~RES_TYPE_SEL_NO;
582 }
583
584 if ((cmd->resp_type & MMC_RSP_CRC) != 0) {
585 cmd_flags |= CMD_CHECK_RESP_CRC;
586 }
587
588 if ((cmd->resp_type & MMC_RSP_CMD_IDX) != 0) {
589 cmd_flags |= CMD_IDX_CHK_ENABLE;
590 }
591
592 if ((cmd->cmd_idx == MMC_ACMD(51)) || (cmd->cmd_idx == MMC_CMD(17)) ||
593 (cmd->cmd_idx == MMC_CMD(18)) || (cmd->cmd_idx == MMC_CMD(24)) ||
594 (cmd->cmd_idx == MMC_CMD(25)) || (cmd->cmd_idx == MMC_CMD(8) &&
595 cdns_params.cdn_sdmmc_dev_type == MMC_IS_EMMC)) {
596 mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
597 cmd_flags |= DATA_PRESENT;
598 mode |= BLK_CNT_EN;
599
600 mode |= (DMA_ENABLED);
601 if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
602 (cmd->cmd_idx == SD_READ_MULTIPLE_BLOCK)) {
603 mode |= (MULTI_BLK_READ);
604 } else {
605 mode &= ~(MULTI_BLK_READ);
606 }
607 if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
608 (cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK)) {
609 mode &= ~CMD_READ;
610 } else {
611 mode |= CMD_READ;
612 }
613 mmio_write_16(cdns_params.reg_base + SDHC_CDNS_SRS03, mode);
614
615 } else {
616 mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
617 }
618
619 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS02, cmd->cmd_arg);
620 mmio_write_16((cdns_params.reg_base + CICE_OFFSET),
621 SDHCI_MAKE_CMD(cmd->cmd_idx, cmd_flags));
622
623 timeout = TIMEOUT;
624
625 do {
626 udelay(CDNS_TIMEOUT);
627 status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12);
628 } while (((status & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0));
629
630 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
631 status_check = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12) & 0xffff8000;
632 if (status_check != 0U) {
633 timeout = TIMEOUT;
634 ERROR("SD host controller send command failed, SRS12 = %x", status_check);
635 return -1;
636 }
637
638 if (!((cmd_flags & RES_TYPE_SEL_NO) == 0)) {
639 cmd->resp_data[0] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS04);
640 if ((cmd_flags & RES_TYPE_SEL_NO) == RES_TYPE_SEL_136) {
641 cmd->resp_data[1] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS05);
642 cmd->resp_data[2] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS06);
643 cmd->resp_data[3] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS07);
644 /* 136-bit: RTS=01b, Response field R[127:8] - RESP3[23:0],
645 * RESP2[31:0], RESP1[31:0], RESP0[31:0]
646 * Subsystem expects 128 bits response but cadence SDHC sends
647 * 120 bits response from R[127:8]. Bits manupulation to address
648 * the correct responses for the 136 bit response type.
649 */
650 cmd->resp_data[3] = ((cmd->resp_data[3] << 8) |
651 ((cmd->resp_data[2] >> 24) &
652 CDNS_CSD_BYTE_MASK));
653 cmd->resp_data[2] = ((cmd->resp_data[2] << 8) |
654 ((cmd->resp_data[1] >> 24) &
655 CDNS_CSD_BYTE_MASK));
656 cmd->resp_data[1] = ((cmd->resp_data[1] << 8) |
657 ((cmd->resp_data[0] >> 24) &
658 CDNS_CSD_BYTE_MASK));
659 cmd->resp_data[0] = (cmd->resp_data[0] << 8);
660 }
661 }
662
663 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
664
665 return 0;
666 }
667
sd_host_adma_prepare(struct cdns_idmac_desc * desc_ptr,uint64_t buf,size_t size)668 void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uint64_t buf,
669 size_t size)
670 {
671 uint32_t full_desc_cnt = 0;
672 uint32_t non_full_desc_cnt = 0;
673 uint64_t desc_address;
674 uint32_t block_count;
675 uint32_t transfer_block_size;
676
677 full_desc_cnt = (size / PAGE_BUFFER_LEN);
678 non_full_desc_cnt = (size % PAGE_BUFFER_LEN);
679 for (int i = 0; i < full_desc_cnt; i++) {
680 desc_ptr->attr = (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_VALID);
681 desc_ptr->len = 0; // 0 means 64kb page size it will take
682 desc_ptr->addr_lo = 0;
683 #if CONFIG_DMA_ADDR_T_64BIT == 1
684 desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
685 #endif
686 if (non_full_desc_cnt == 0) {
687 desc_ptr->attr |= (ADMA_DESC_ATTR_END);
688 }
689 buf += PAGE_BUFFER_LEN;
690 }
691
692 if (non_full_desc_cnt != 0) {
693 desc_ptr->attr =
694 (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_END | ADMA_DESC_ATTR_VALID);
695 desc_ptr->addr_lo = buf & 0xffffffff;
696 desc_ptr->len = size;
697 #if CONFIG_DMA_ADDR_T_64BIT == 1
698 desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
699 #endif
700 desc_address = (uint64_t)desc_ptr;
701 if (size > MMC_MAX_BLOCK_LEN) {
702 transfer_block_size = MMC_MAX_BLOCK_LEN;
703 } else {
704 transfer_block_size = size;
705 }
706
707 block_count = (size / transfer_block_size);
708 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS01,
709 ((transfer_block_size << BLOCK_SIZE) | SDMA_BUF |
710 (block_count << BLK_COUNT_CT)));
711 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS22,
712 (uint32_t)desc_address & 0xFFFFFFFF);
713 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS23,
714 (uint32_t)(desc_address >> 32 & 0xFFFFFFFF));
715 }
716 }
717
cdns_mmc_init(struct cdns_sdmmc_params * params,struct mmc_device_info * info)718 int cdns_mmc_init(struct cdns_sdmmc_params *params,
719 struct mmc_device_info *info)
720 {
721
722 int result = 0;
723
724 assert((params != NULL) &&
725 ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
726 ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
727 ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
728 ((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
729 (params->desc_size > 0) &&
730 (params->clk_rate > 0) &&
731 (params->sdmclk > 0) &&
732 ((params->bus_width == MMC_BUS_WIDTH_1) ||
733 (params->bus_width == MMC_BUS_WIDTH_4) ||
734 (params->bus_width == MMC_BUS_WIDTH_8)));
735
736 memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params));
737
738 cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
739 result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
740 if (result < 0) {
741 return result;
742 }
743
744 cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
745 cdns_params.cdn_sdmmc_dev_mode = SD_DS;
746
747 result = mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
748 params->flags, info);
749
750 return result;
751 }
752