1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gic_common.h> 14 15 #include <platform_def.h> 16 17 #include "../common/gic_common_private.h" 18 #include "gicv3_private.h" 19 20 /****************************************************************************** 21 * This function marks the core as awake in the re-distributor and 22 * ensures that the interface is active. 23 *****************************************************************************/ 24 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 25 { 26 /* 27 * The WAKER_PS_BIT should be changed to 0 28 * only when WAKER_CA_BIT is 1. 29 */ 30 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 31 32 /* Mark the connected core as awake */ 33 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 34 35 /* Wait till the WAKER_CA_BIT changes to 0 */ 36 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 37 } 38 } 39 40 /****************************************************************************** 41 * This function marks the core as asleep in the re-distributor and ensures 42 * that the interface is quiescent. 43 *****************************************************************************/ 44 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 45 { 46 /* Mark the connected core as asleep */ 47 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 48 49 /* Wait till the WAKER_CA_BIT changes to 1 */ 50 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 51 } 52 } 53 54 /******************************************************************************* 55 * This function probes the Redistributor frames when the driver is initialised 56 * and saves their base addresses. These base addresses are used later to 57 * initialise each Redistributor interface. 58 ******************************************************************************/ 59 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 60 unsigned int rdistif_num, 61 uintptr_t gicr_base, 62 mpidr_hash_fn mpidr_to_core_pos) 63 { 64 u_register_t mpidr; 65 unsigned int proc_num; 66 uint64_t typer_val; 67 uintptr_t rdistif_base = gicr_base; 68 69 assert(rdistif_base_addrs != NULL); 70 71 /* 72 * Iterate over the Redistributor frames. Store the base address of each 73 * frame in the platform provided array. Use the "Processor Number" 74 * field to index into the array if the platform has not provided a hash 75 * function to convert an MPIDR (obtained from the "Affinity Value" 76 * field into a linear index. 77 */ 78 do { 79 typer_val = gicr_read_typer(rdistif_base); 80 if (mpidr_to_core_pos != NULL) { 81 mpidr = mpidr_from_gicr_typer(typer_val); 82 proc_num = mpidr_to_core_pos(mpidr); 83 } else { 84 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 85 TYPER_PROC_NUM_MASK; 86 } 87 88 if (proc_num < rdistif_num) { 89 rdistif_base_addrs[proc_num] = rdistif_base; 90 } 91 rdistif_base += gicv3_redist_size(typer_val); 92 } while ((typer_val & TYPER_LAST_BIT) == 0U); 93 } 94 95 /******************************************************************************* 96 * Helper function to get the maximum SPI INTID + 1. 97 ******************************************************************************/ 98 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) 99 { 100 unsigned int spi_limit; 101 unsigned int typer_reg = gicd_read_typer(gicd_base); 102 103 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */ 104 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 105 106 /* Filter out special INTIDs 1020-1023 */ 107 if (spi_limit > (MAX_SPI_ID + 1U)) { 108 return MAX_SPI_ID + 1U; 109 } 110 111 return spi_limit; 112 } 113 114 #if GIC_EXT_INTID 115 /******************************************************************************* 116 * Helper function to get the maximum ESPI INTID + 1. 117 ******************************************************************************/ 118 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base) 119 { 120 unsigned int typer_reg = gicd_read_typer(gicd_base); 121 122 /* Check if extended SPI range is implemented */ 123 if ((typer_reg & TYPER_ESPI) != 0U) { 124 /* 125 * (maximum ESPI INTID + 1) is equal to 126 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096 127 */ 128 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 129 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 130 } 131 132 return 0U; 133 } 134 #endif /* GIC_EXT_INTID */ 135 136 /******************************************************************************* 137 * Helper function to configure the default attributes of (E)SPIs. 138 ******************************************************************************/ 139 void gicv3_spis_config_defaults(uintptr_t gicd_base) 140 { 141 unsigned int i, num_ints; 142 #if GIC_EXT_INTID 143 unsigned int num_eints; 144 #endif 145 146 num_ints = gicv3_get_spi_limit(gicd_base); 147 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); 148 149 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 150 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 151 gicd_write_igroupr(gicd_base, i, ~0U); 152 } 153 154 #if GIC_EXT_INTID 155 num_eints = gicv3_get_espi_limit(gicd_base); 156 if (num_eints != 0U) { 157 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); 158 159 for (i = MIN_ESPI_ID; i < num_eints; 160 i += (1U << IGROUPR_SHIFT)) { 161 gicd_write_igroupr(gicd_base, i, ~0U); 162 } 163 } else { 164 INFO("ESPI range is not implemented.\n"); 165 } 166 #endif 167 168 /* Setup the default (E)SPI priorities doing four at a time */ 169 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 170 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 171 } 172 173 #if GIC_EXT_INTID 174 for (i = MIN_ESPI_ID; i < num_eints; 175 i += (1U << IPRIORITYR_SHIFT)) { 176 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 177 } 178 #endif 179 /* 180 * Treat all (E)SPIs as level triggered by default, write 16 at a time 181 */ 182 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 183 gicd_write_icfgr(gicd_base, i, 0U); 184 } 185 186 #if GIC_EXT_INTID 187 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 188 gicd_write_icfgr(gicd_base, i, 0U); 189 } 190 #endif 191 } 192 193 /******************************************************************************* 194 * Helper function to configure properties of secure (E)SPIs 195 ******************************************************************************/ 196 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 197 const interrupt_prop_t *interrupt_props, 198 unsigned int interrupt_props_num) 199 { 200 unsigned int i; 201 const interrupt_prop_t *current_prop; 202 unsigned long long gic_affinity_val; 203 unsigned int ctlr_enable = 0U; 204 205 /* Make sure there's a valid property array */ 206 if (interrupt_props_num > 0U) { 207 assert(interrupt_props != NULL); 208 } 209 210 for (i = 0U; i < interrupt_props_num; i++) { 211 current_prop = &interrupt_props[i]; 212 213 unsigned int intr_num = current_prop->intr_num; 214 215 /* Skip SGI, (E)PPI and LPI interrupts */ 216 if (!IS_SPI(intr_num)) { 217 continue; 218 } 219 220 /* Configure this interrupt as a secure interrupt */ 221 gicd_clr_igroupr(gicd_base, intr_num); 222 223 /* Configure this interrupt as G0 or a G1S interrupt */ 224 assert((current_prop->intr_grp == INTR_GROUP0) || 225 (current_prop->intr_grp == INTR_GROUP1S)); 226 227 if (current_prop->intr_grp == INTR_GROUP1S) { 228 gicd_set_igrpmodr(gicd_base, intr_num); 229 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 230 } else { 231 gicd_clr_igrpmodr(gicd_base, intr_num); 232 ctlr_enable |= CTLR_ENABLE_G0_BIT; 233 } 234 235 /* Set interrupt configuration */ 236 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); 237 238 /* Set the priority of this interrupt */ 239 gicd_set_ipriorityr(gicd_base, intr_num, 240 current_prop->intr_pri); 241 242 /* Target (E)SPIs to the primary CPU */ 243 gic_affinity_val = 244 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 245 gicd_write_irouter(gicd_base, intr_num, 246 gic_affinity_val); 247 248 /* Enable this interrupt */ 249 gicd_set_isenabler(gicd_base, intr_num); 250 } 251 252 return ctlr_enable; 253 } 254 255 /******************************************************************************* 256 * Helper function to configure the default attributes of (E)PPIs/SGIs 257 ******************************************************************************/ 258 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 259 { 260 unsigned int i, ppi_regs_num, regs_num; 261 262 #if GIC_EXT_INTID 263 /* Calculate number of PPI registers */ 264 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 265 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 266 /* All other values except PPInum [0-2] are reserved */ 267 if (ppi_regs_num > 3U) { 268 ppi_regs_num = 1U; 269 } 270 #else 271 ppi_regs_num = 1U; 272 #endif 273 /* 274 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 275 * This is a more scalable approach as it avoids clearing 276 * the enable bits in the GICD_CTLR. 277 */ 278 for (i = 0U; i < ppi_regs_num; ++i) { 279 gicr_write_icenabler(gicr_base, i, ~0U); 280 } 281 282 /* Wait for pending writes to GICR_ICENABLER */ 283 gicr_wait_for_pending_write(gicr_base); 284 285 /* 32 interrupt IDs per GICR_IGROUPR register */ 286 for (i = 0U; i < ppi_regs_num; ++i) { 287 /* Treat all SGIs/(E)PPIs as G1NS by default */ 288 gicr_write_igroupr(gicr_base, i, ~0U); 289 } 290 291 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 292 regs_num = ppi_regs_num << 3; 293 for (i = 0U; i < regs_num; ++i) { 294 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 295 gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL); 296 } 297 298 /* 16 interrupt IDs per GICR_ICFGR register */ 299 regs_num = ppi_regs_num << 1; 300 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 301 /* Configure all (E)PPIs as level triggered by default */ 302 gicr_write_icfgr(gicr_base, i, 0U); 303 } 304 } 305 306 /******************************************************************************* 307 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 308 ******************************************************************************/ 309 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 310 const interrupt_prop_t *interrupt_props, 311 unsigned int interrupt_props_num) 312 { 313 unsigned int i; 314 const interrupt_prop_t *current_prop; 315 unsigned int ctlr_enable = 0U; 316 317 /* Make sure there's a valid property array */ 318 if (interrupt_props_num > 0U) { 319 assert(interrupt_props != NULL); 320 } 321 322 for (i = 0U; i < interrupt_props_num; i++) { 323 current_prop = &interrupt_props[i]; 324 325 unsigned int intr_num = current_prop->intr_num; 326 327 /* Skip (E)SPI interrupt */ 328 if (!IS_SGI_PPI(intr_num)) { 329 continue; 330 } 331 332 /* Configure this interrupt as a secure interrupt */ 333 gicr_clr_igroupr(gicr_base, intr_num); 334 335 /* Configure this interrupt as G0 or a G1S interrupt */ 336 assert((current_prop->intr_grp == INTR_GROUP0) || 337 (current_prop->intr_grp == INTR_GROUP1S)); 338 339 if (current_prop->intr_grp == INTR_GROUP1S) { 340 gicr_set_igrpmodr(gicr_base, intr_num); 341 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 342 } else { 343 gicr_clr_igrpmodr(gicr_base, intr_num); 344 ctlr_enable |= CTLR_ENABLE_G0_BIT; 345 } 346 347 /* Set the priority of this interrupt */ 348 gicr_set_ipriorityr(gicr_base, intr_num, 349 current_prop->intr_pri); 350 351 /* 352 * Set interrupt configuration for (E)PPIs. 353 * Configurations for SGIs 0-15 are ignored. 354 */ 355 if (intr_num >= MIN_PPI_ID) { 356 gicr_set_icfgr(gicr_base, intr_num, 357 current_prop->intr_cfg); 358 } 359 360 /* Enable this interrupt */ 361 gicr_set_isenabler(gicr_base, intr_num); 362 } 363 364 return ctlr_enable; 365 } 366 367 /** 368 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 369 * @gicr_frame: base address of the GICR region to check 370 * 371 * This iterates over the GICR_TYPER registers of multiple GICR frames in 372 * a GICR region, to find the instance which has the LAST bit set. For most 373 * systems this corresponds to the number of cores handled by a redistributor, 374 * but there could be disabled cores among them. 375 * It assumes that each GICR region is fully accessible (till the LAST bit 376 * marks the end of the region). 377 * If a platform has multiple GICR regions, this function would need to be 378 * called multiple times, providing the respective GICR base address each time. 379 * 380 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 381 ******************************************************************************/ 382 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 383 { 384 uintptr_t rdistif_base = gicr_frame; 385 unsigned int count; 386 387 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) { 388 uint64_t typer_val = gicr_read_typer(rdistif_base); 389 390 if ((typer_val & TYPER_LAST_BIT) != 0U) { 391 break; 392 } 393 rdistif_base += gicv3_redist_size(typer_val); 394 } 395 396 return count; 397 } 398 399 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame) 400 { 401 unsigned int part_id; 402 403 /* 404 * The lower 8 bits of PIDR0, complemented by the lower 4 bits of 405 * PIDR1 contain a part number identifying the GIC component at a 406 * particular base address. 407 */ 408 part_id = mmio_read_32(gic_frame + GICD_PIDR0_GICV3) & 0xff; 409 part_id |= (mmio_read_32(gic_frame + GICD_PIDR1_GICV3) << 8) & 0xf00; 410 411 return part_id; 412 } 413 414 /******************************************************************************* 415 * Helper function to return product ID and revision of GIC 416 * @gicd_base: base address of the GIC distributor 417 * @gic_prod_id: retrieved product id of GIC 418 * @gic_rev: retrieved revision of GIC 419 ******************************************************************************/ 420 void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, 421 unsigned int *gic_prod_id, 422 uint8_t *gic_rev) 423 { 424 unsigned int gicd_iidr; 425 uint8_t gic_variant; 426 427 gicd_iidr = gicd_read_iidr(gicd_base); 428 *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT; 429 *gic_prod_id &= IIDR_PRODUCT_ID_MASK; 430 431 gic_variant = gicd_iidr >> IIDR_VARIANT_SHIFT; 432 gic_variant &= IIDR_VARIANT_MASK; 433 434 *gic_rev = gicd_iidr >> IIDR_REV_SHIFT; 435 *gic_rev &= IIDR_REV_MASK; 436 437 /* 438 * pack gic variant and gic_rev in 1 byte 439 * gic_rev = gic_variant[7:4] and gic_rev[0:3] 440 */ 441 *gic_rev = *gic_rev | gic_variant << 0x4; 442 443 } 444