1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include "../common/gic_common_private.h" 14 #include "gicv3_private.h" 15 16 /* 17 * Accessor to read the GIC Distributor IGRPMODR corresponding to the 18 * interrupt `id`, 32 interrupt IDs at a time. 19 */ 20 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) 21 { 22 unsigned int n = id >> IGRPMODR_SHIFT; 23 24 return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); 25 } 26 27 /* 28 * Accessor to write the GIC Distributor IGRPMODR corresponding to the 29 * interrupt `id`, 32 interrupt IDs at a time. 30 */ 31 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) 32 { 33 unsigned int n = id >> IGRPMODR_SHIFT; 34 35 mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); 36 } 37 38 /* 39 * Accessor to get the bit corresponding to interrupt ID 40 * in GIC Distributor IGRPMODR. 41 */ 42 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) 43 { 44 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 45 unsigned int reg_val = gicd_read_igrpmodr(base, id); 46 47 return (reg_val >> bit_num) & 0x1U; 48 } 49 50 /* 51 * Accessor to set the bit corresponding to interrupt ID 52 * in GIC Distributor IGRPMODR. 53 */ 54 void gicd_set_igrpmodr(uintptr_t base, unsigned int id) 55 { 56 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 57 unsigned int reg_val = gicd_read_igrpmodr(base, id); 58 59 gicd_write_igrpmodr(base, id, reg_val | (1U << bit_num)); 60 } 61 62 /* 63 * Accessor to clear the bit corresponding to interrupt ID 64 * in GIC Distributor IGRPMODR. 65 */ 66 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) 67 { 68 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 69 unsigned int reg_val = gicd_read_igrpmodr(base, id); 70 71 gicd_write_igrpmodr(base, id, reg_val & ~(1U << bit_num)); 72 } 73 74 /* 75 * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the 76 * interrupt `id`, 4 interrupts IDs at a time. 77 */ 78 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) 79 { 80 unsigned int n = id >> IPRIORITYR_SHIFT; 81 82 return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); 83 } 84 85 /* 86 * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the 87 * interrupt `id`, 4 interrupts IDs at a time. 88 */ 89 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) 90 { 91 unsigned int n = id >> IPRIORITYR_SHIFT; 92 93 mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); 94 } 95 96 /* 97 * Accessor to get the bit corresponding to interrupt ID 98 * from GIC Re-distributor IGROUPR0. 99 */ 100 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) 101 { 102 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 103 unsigned int reg_val = gicr_read_igroupr0(base); 104 105 return (reg_val >> bit_num) & 0x1U; 106 } 107 108 /* 109 * Accessor to set the bit corresponding to interrupt ID 110 * in GIC Re-distributor IGROUPR0. 111 */ 112 void gicr_set_igroupr0(uintptr_t base, unsigned int id) 113 { 114 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 115 unsigned int reg_val = gicr_read_igroupr0(base); 116 117 gicr_write_igroupr0(base, reg_val | (1U << bit_num)); 118 } 119 120 /* 121 * Accessor to clear the bit corresponding to interrupt ID 122 * in GIC Re-distributor IGROUPR0. 123 */ 124 void gicr_clr_igroupr0(uintptr_t base, unsigned int id) 125 { 126 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 127 unsigned int reg_val = gicr_read_igroupr0(base); 128 129 gicr_write_igroupr0(base, reg_val & ~(1U << bit_num)); 130 } 131 132 /* 133 * Accessor to get the bit corresponding to interrupt ID 134 * from GIC Re-distributor IGRPMODR0. 135 */ 136 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) 137 { 138 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 139 unsigned int reg_val = gicr_read_igrpmodr0(base); 140 141 return (reg_val >> bit_num) & 0x1U; 142 } 143 144 /* 145 * Accessor to set the bit corresponding to interrupt ID 146 * in GIC Re-distributor IGRPMODR0. 147 */ 148 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) 149 { 150 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 151 unsigned int reg_val = gicr_read_igrpmodr0(base); 152 153 gicr_write_igrpmodr0(base, reg_val | (1U << bit_num)); 154 } 155 156 /* 157 * Accessor to clear the bit corresponding to interrupt ID 158 * in GIC Re-distributor IGRPMODR0. 159 */ 160 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) 161 { 162 unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U); 163 unsigned int reg_val = gicr_read_igrpmodr0(base); 164 165 gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num)); 166 } 167 168 /* 169 * Accessor to set the bit corresponding to interrupt ID 170 * in GIC Re-distributor ISENABLER0. 171 */ 172 void gicr_set_isenabler0(uintptr_t base, unsigned int id) 173 { 174 unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U); 175 176 gicr_write_isenabler0(base, (1U << bit_num)); 177 } 178 179 /* 180 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 181 * ICENABLER0. 182 */ 183 void gicr_set_icenabler0(uintptr_t base, unsigned int id) 184 { 185 unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U); 186 187 gicr_write_icenabler0(base, (1U << bit_num)); 188 } 189 190 /* 191 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 192 * ISACTIVER0. 193 */ 194 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id) 195 { 196 unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U); 197 unsigned int reg_val = gicr_read_isactiver0(base); 198 199 return (reg_val >> bit_num) & 0x1U; 200 } 201 202 /* 203 * Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor 204 * ICPENDRR0. 205 */ 206 void gicr_set_icpendr0(uintptr_t base, unsigned int id) 207 { 208 unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U); 209 210 gicr_write_icpendr0(base, (1U << bit_num)); 211 } 212 213 /* 214 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 215 * ISPENDR0. 216 */ 217 void gicr_set_ispendr0(uintptr_t base, unsigned int id) 218 { 219 unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U); 220 221 gicr_write_ispendr0(base, (1U << bit_num)); 222 } 223 224 /* 225 * Accessor to set the byte corresponding to interrupt ID 226 * in GIC Re-distributor IPRIORITYR. 227 */ 228 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) 229 { 230 uint8_t val = pri & GIC_PRI_MASK; 231 232 mmio_write_8(base + GICR_IPRIORITYR + id, val); 233 } 234 235 /* 236 * Accessor to set the bit fields corresponding to interrupt ID 237 * in GIC Re-distributor ICFGR0. 238 */ 239 void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg) 240 { 241 /* Interrupt configuration is a 2-bit field */ 242 unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U); 243 unsigned int bit_shift = bit_num << 1U; 244 245 uint32_t reg_val = gicr_read_icfgr0(base); 246 247 /* Clear the field, and insert required configuration */ 248 reg_val &= ~(GIC_CFG_MASK << bit_shift); 249 reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); 250 251 gicr_write_icfgr0(base, reg_val); 252 } 253 254 /* 255 * Accessor to set the bit fields corresponding to interrupt ID 256 * in GIC Re-distributor ICFGR1. 257 */ 258 void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg) 259 { 260 /* Interrupt configuration is a 2-bit field */ 261 unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U); 262 unsigned int bit_shift = bit_num << 1U; 263 264 uint32_t reg_val = gicr_read_icfgr1(base); 265 266 /* Clear the field, and insert required configuration */ 267 reg_val &= ~(GIC_CFG_MASK << bit_shift); 268 reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); 269 270 gicr_write_icfgr1(base, reg_val); 271 } 272 273 /****************************************************************************** 274 * This function marks the core as awake in the re-distributor and 275 * ensures that the interface is active. 276 *****************************************************************************/ 277 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 278 { 279 /* 280 * The WAKER_PS_BIT should be changed to 0 281 * only when WAKER_CA_BIT is 1. 282 */ 283 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 284 285 /* Mark the connected core as awake */ 286 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 287 288 /* Wait till the WAKER_CA_BIT changes to 0 */ 289 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) 290 ; 291 } 292 293 294 /****************************************************************************** 295 * This function marks the core as asleep in the re-distributor and ensures 296 * that the interface is quiescent. 297 *****************************************************************************/ 298 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 299 { 300 /* Mark the connected core as asleep */ 301 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 302 303 /* Wait till the WAKER_CA_BIT changes to 1 */ 304 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) 305 ; 306 } 307 308 309 /******************************************************************************* 310 * This function probes the Redistributor frames when the driver is initialised 311 * and saves their base addresses. These base addresses are used later to 312 * initialise each Redistributor interface. 313 ******************************************************************************/ 314 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 315 unsigned int rdistif_num, 316 uintptr_t gicr_base, 317 mpidr_hash_fn mpidr_to_core_pos) 318 { 319 u_register_t mpidr; 320 unsigned int proc_num; 321 uint64_t typer_val; 322 uintptr_t rdistif_base = gicr_base; 323 324 assert(rdistif_base_addrs != NULL); 325 326 /* 327 * Iterate over the Redistributor frames. Store the base address of each 328 * frame in the platform provided array. Use the "Processor Number" 329 * field to index into the array if the platform has not provided a hash 330 * function to convert an MPIDR (obtained from the "Affinity Value" 331 * field into a linear index. 332 */ 333 do { 334 typer_val = gicr_read_typer(rdistif_base); 335 if (mpidr_to_core_pos != NULL) { 336 mpidr = mpidr_from_gicr_typer(typer_val); 337 proc_num = mpidr_to_core_pos(mpidr); 338 } else { 339 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 340 TYPER_PROC_NUM_MASK; 341 } 342 assert(proc_num < rdistif_num); 343 rdistif_base_addrs[proc_num] = rdistif_base; 344 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 345 } while ((typer_val & TYPER_LAST_BIT) == 0U); 346 } 347 348 /******************************************************************************* 349 * Helper function to configure the default attributes of SPIs. 350 ******************************************************************************/ 351 void gicv3_spis_config_defaults(uintptr_t gicd_base) 352 { 353 unsigned int index, num_ints; 354 355 num_ints = gicd_read_typer(gicd_base); 356 num_ints &= TYPER_IT_LINES_NO_MASK; 357 num_ints = (num_ints + 1U) << 5; 358 359 /* 360 * Treat all SPIs as G1NS by default. The number of interrupts is 361 * calculated as 32 * (IT_LINES + 1). We do 32 at a time. 362 */ 363 for (index = MIN_SPI_ID; index < num_ints; index += 32U) 364 gicd_write_igroupr(gicd_base, index, ~0U); 365 366 /* Setup the default SPI priorities doing four at a time */ 367 for (index = MIN_SPI_ID; index < num_ints; index += 4U) 368 gicd_write_ipriorityr(gicd_base, 369 index, 370 GICD_IPRIORITYR_DEF_VAL); 371 372 /* 373 * Treat all SPIs as level triggered by default, write 16 at 374 * a time 375 */ 376 for (index = MIN_SPI_ID; index < num_ints; index += 16U) 377 gicd_write_icfgr(gicd_base, index, 0U); 378 } 379 380 /******************************************************************************* 381 * Helper function to configure properties of secure SPIs 382 ******************************************************************************/ 383 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 384 const interrupt_prop_t *interrupt_props, 385 unsigned int interrupt_props_num) 386 { 387 unsigned int i; 388 const interrupt_prop_t *current_prop; 389 unsigned long long gic_affinity_val; 390 unsigned int ctlr_enable = 0U; 391 392 /* Make sure there's a valid property array */ 393 if (interrupt_props_num > 0U) 394 assert(interrupt_props != NULL); 395 396 for (i = 0U; i < interrupt_props_num; i++) { 397 current_prop = &interrupt_props[i]; 398 399 if (current_prop->intr_num < MIN_SPI_ID) 400 continue; 401 402 /* Configure this interrupt as a secure interrupt */ 403 gicd_clr_igroupr(gicd_base, current_prop->intr_num); 404 405 /* Configure this interrupt as G0 or a G1S interrupt */ 406 assert((current_prop->intr_grp == INTR_GROUP0) || 407 (current_prop->intr_grp == INTR_GROUP1S)); 408 if (current_prop->intr_grp == INTR_GROUP1S) { 409 gicd_set_igrpmodr(gicd_base, current_prop->intr_num); 410 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 411 } else { 412 gicd_clr_igrpmodr(gicd_base, current_prop->intr_num); 413 ctlr_enable |= CTLR_ENABLE_G0_BIT; 414 } 415 416 /* Set interrupt configuration */ 417 gicd_set_icfgr(gicd_base, current_prop->intr_num, 418 current_prop->intr_cfg); 419 420 /* Set the priority of this interrupt */ 421 gicd_set_ipriorityr(gicd_base, current_prop->intr_num, 422 current_prop->intr_pri); 423 424 /* Target SPIs to the primary CPU */ 425 gic_affinity_val = 426 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 427 gicd_write_irouter(gicd_base, current_prop->intr_num, 428 gic_affinity_val); 429 430 /* Enable this interrupt */ 431 gicd_set_isenabler(gicd_base, current_prop->intr_num); 432 } 433 434 return ctlr_enable; 435 } 436 437 /******************************************************************************* 438 * Helper function to configure the default attributes of SPIs. 439 ******************************************************************************/ 440 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 441 { 442 unsigned int index; 443 444 /* 445 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 446 * more scalable approach as it avoids clearing the enable bits in the 447 * GICD_CTLR 448 */ 449 gicr_write_icenabler0(gicr_base, ~0U); 450 gicr_wait_for_pending_write(gicr_base); 451 452 /* Treat all SGIs/PPIs as G1NS by default. */ 453 gicr_write_igroupr0(gicr_base, ~0U); 454 455 /* Setup the default PPI/SGI priorities doing four at a time */ 456 for (index = 0U; index < MIN_SPI_ID; index += 4U) 457 gicr_write_ipriorityr(gicr_base, 458 index, 459 GICD_IPRIORITYR_DEF_VAL); 460 461 /* Configure all PPIs as level triggered by default */ 462 gicr_write_icfgr1(gicr_base, 0U); 463 } 464 465 /******************************************************************************* 466 * Helper function to configure properties of secure G0 and G1S PPIs and SGIs. 467 ******************************************************************************/ 468 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 469 const interrupt_prop_t *interrupt_props, 470 unsigned int interrupt_props_num) 471 { 472 unsigned int i; 473 const interrupt_prop_t *current_prop; 474 unsigned int ctlr_enable = 0U; 475 476 /* Make sure there's a valid property array */ 477 if (interrupt_props_num > 0U) 478 assert(interrupt_props != NULL); 479 480 for (i = 0U; i < interrupt_props_num; i++) { 481 current_prop = &interrupt_props[i]; 482 483 if (current_prop->intr_num >= MIN_SPI_ID) 484 continue; 485 486 /* Configure this interrupt as a secure interrupt */ 487 gicr_clr_igroupr0(gicr_base, current_prop->intr_num); 488 489 /* Configure this interrupt as G0 or a G1S interrupt */ 490 assert((current_prop->intr_grp == INTR_GROUP0) || 491 (current_prop->intr_grp == INTR_GROUP1S)); 492 if (current_prop->intr_grp == INTR_GROUP1S) { 493 gicr_set_igrpmodr0(gicr_base, current_prop->intr_num); 494 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 495 } else { 496 gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num); 497 ctlr_enable |= CTLR_ENABLE_G0_BIT; 498 } 499 500 /* Set the priority of this interrupt */ 501 gicr_set_ipriorityr(gicr_base, current_prop->intr_num, 502 current_prop->intr_pri); 503 504 /* 505 * Set interrupt configuration for PPIs. Configuration for SGIs 506 * are ignored. 507 */ 508 if ((current_prop->intr_num >= MIN_PPI_ID) && 509 (current_prop->intr_num < MIN_SPI_ID)) { 510 gicr_set_icfgr1(gicr_base, current_prop->intr_num, 511 current_prop->intr_cfg); 512 } 513 514 /* Enable this interrupt */ 515 gicr_set_isenabler0(gicr_base, current_prop->intr_num); 516 } 517 518 return ctlr_enable; 519 } 520