1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gic_common.h> 16 17 #include <platform_def.h> 18 19 #include "../common/gic_common_private.h" 20 #include "gicv3_private.h" 21 22 uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base) 23 { 24 #if GICV3_IMPL_GIC600_MULTICHIP 25 if (gic600_multichip_is_initialized()) { 26 return gic600_multichip_gicd_base_for_spi(spi_id); 27 } 28 #endif 29 return gicd_base; 30 } 31 32 /****************************************************************************** 33 * This function marks the core as awake in the re-distributor and 34 * ensures that the interface is active. 35 *****************************************************************************/ 36 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 37 { 38 /* 39 * The WAKER_PS_BIT should be changed to 0 40 * only when WAKER_CA_BIT is 1. 41 */ 42 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 43 44 /* Mark the connected core as awake */ 45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 46 47 /* Wait till the WAKER_CA_BIT changes to 0 */ 48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 49 } 50 } 51 52 /****************************************************************************** 53 * This function marks the core as asleep in the re-distributor and ensures 54 * that the interface is quiescent. 55 *****************************************************************************/ 56 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 57 { 58 /* Mark the connected core as asleep */ 59 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 60 61 /* Wait till the WAKER_CA_BIT changes to 1 */ 62 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 63 } 64 } 65 66 /******************************************************************************* 67 * This function probes the Redistributor frames when the driver is initialised 68 * and saves their base addresses. These base addresses are used later to 69 * initialise each Redistributor interface. 70 ******************************************************************************/ 71 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 72 unsigned int rdistif_num, 73 uintptr_t gicr_base, 74 mpidr_hash_fn mpidr_to_core_pos) 75 { 76 u_register_t mpidr; 77 unsigned int proc_num; 78 uint64_t typer_val; 79 uintptr_t rdistif_base = gicr_base; 80 81 assert(rdistif_base_addrs != NULL); 82 83 /* 84 * Iterate over the Redistributor frames. Store the base address of each 85 * frame in the platform provided array. Use the "Processor Number" 86 * field to index into the array if the platform has not provided a hash 87 * function to convert an MPIDR (obtained from the "Affinity Value" 88 * field into a linear index. 89 */ 90 do { 91 typer_val = gicr_read_typer(rdistif_base); 92 if (mpidr_to_core_pos != NULL) { 93 mpidr = mpidr_from_gicr_typer(typer_val); 94 proc_num = mpidr_to_core_pos(mpidr); 95 } else { 96 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 97 TYPER_PROC_NUM_MASK; 98 } 99 100 if (proc_num < rdistif_num) { 101 rdistif_base_addrs[proc_num] = rdistif_base; 102 } 103 rdistif_base += gicv3_redist_size(typer_val); 104 } while ((typer_val & TYPER_LAST_BIT) == 0U); 105 } 106 107 /******************************************************************************* 108 * Helper function to get the maximum SPI INTID + 1. 109 ******************************************************************************/ 110 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) 111 { 112 unsigned int spi_limit; 113 unsigned int typer_reg = gicd_read_typer(gicd_base); 114 115 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */ 116 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 117 118 /* Filter out special INTIDs 1020-1023 */ 119 if (spi_limit > (MAX_SPI_ID + 1U)) { 120 return MAX_SPI_ID + 1U; 121 } 122 123 return spi_limit; 124 } 125 126 #if GIC_EXT_INTID 127 /******************************************************************************* 128 * Helper function to get the maximum ESPI INTID + 1. 129 ******************************************************************************/ 130 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base) 131 { 132 unsigned int typer_reg = gicd_read_typer(gicd_base); 133 134 /* Check if extended SPI range is implemented */ 135 if ((typer_reg & TYPER_ESPI) != 0U) { 136 /* 137 * (maximum ESPI INTID + 1) is equal to 138 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096 139 */ 140 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 141 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 142 } 143 144 return 0U; 145 } 146 #endif /* GIC_EXT_INTID */ 147 148 /******************************************************************************* 149 * Helper function to configure the default attributes of (E)SPIs. 150 ******************************************************************************/ 151 void gicv3_spis_config_defaults(uintptr_t gicd_base) 152 { 153 unsigned int i, num_ints; 154 #if GIC_EXT_INTID 155 unsigned int num_eints; 156 #endif 157 158 num_ints = gicv3_get_spi_limit(gicd_base); 159 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); 160 161 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 162 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 163 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); 164 } 165 166 #if GIC_EXT_INTID 167 num_eints = gicv3_get_espi_limit(gicd_base); 168 if (num_eints != 0U) { 169 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); 170 171 for (i = MIN_ESPI_ID; i < num_eints; 172 i += (1U << IGROUPR_SHIFT)) { 173 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); 174 } 175 } else { 176 INFO("ESPI range is not implemented.\n"); 177 } 178 #endif 179 180 /* Setup the default (E)SPI priorities doing four at a time */ 181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 182 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); 183 } 184 185 #if GIC_EXT_INTID 186 for (i = MIN_ESPI_ID; i < num_eints; 187 i += (1U << IPRIORITYR_SHIFT)) { 188 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); 189 } 190 #endif 191 /* 192 * Treat all (E)SPIs as level triggered by default, write 16 at a time 193 */ 194 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 195 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U); 196 } 197 198 #if GIC_EXT_INTID 199 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 200 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U); 201 } 202 #endif 203 } 204 205 /******************************************************************************* 206 * Helper function to configure properties of secure (E)SPIs 207 ******************************************************************************/ 208 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 209 const interrupt_prop_t *interrupt_props, 210 unsigned int interrupt_props_num) 211 { 212 unsigned int i; 213 const interrupt_prop_t *current_prop; 214 unsigned long long gic_affinity_val; 215 unsigned int ctlr_enable = 0U; 216 217 /* Make sure there's a valid property array */ 218 if (interrupt_props_num > 0U) { 219 assert(interrupt_props != NULL); 220 } 221 222 for (i = 0U; i < interrupt_props_num; i++) { 223 current_prop = &interrupt_props[i]; 224 225 unsigned int intr_num = current_prop->intr_num; 226 uintptr_t multichip_gicd_base = gicv3_get_multichip_base(intr_num, gicd_base); 227 228 /* Skip SGI, (E)PPI and LPI interrupts */ 229 if (!IS_SPI(intr_num)) { 230 continue; 231 } 232 233 /* Configure this interrupt as a secure interrupt */ 234 gicd_clr_igroupr(multichip_gicd_base, intr_num); 235 236 /* Configure this interrupt as G0 or a G1S interrupt */ 237 assert((current_prop->intr_grp == INTR_GROUP0) || 238 (current_prop->intr_grp == INTR_GROUP1S)); 239 240 if (current_prop->intr_grp == INTR_GROUP1S) { 241 gicd_set_igrpmodr(multichip_gicd_base, intr_num); 242 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 243 } else { 244 gicd_clr_igrpmodr(multichip_gicd_base, intr_num); 245 ctlr_enable |= CTLR_ENABLE_G0_BIT; 246 } 247 248 /* Set interrupt configuration */ 249 gicd_set_icfgr(multichip_gicd_base, intr_num, 250 current_prop->intr_cfg); 251 252 /* Set the priority of this interrupt */ 253 gicd_set_ipriorityr(multichip_gicd_base, intr_num, 254 current_prop->intr_pri); 255 256 /* Target (E)SPIs to the primary CPU */ 257 gic_affinity_val = 258 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 259 gicd_write_irouter(multichip_gicd_base, intr_num, 260 gic_affinity_val); 261 262 /* Enable this interrupt */ 263 gicd_set_isenabler(multichip_gicd_base, intr_num); 264 } 265 266 return ctlr_enable; 267 } 268 269 /******************************************************************************* 270 * Helper function to configure the default attributes of (E)PPIs/SGIs 271 ******************************************************************************/ 272 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 273 { 274 unsigned int i, ppi_regs_num, regs_num; 275 276 #if GIC_EXT_INTID 277 /* Calculate number of PPI registers */ 278 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 279 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 280 /* All other values except PPInum [0-2] are reserved */ 281 if (ppi_regs_num > 3U) { 282 ppi_regs_num = 1U; 283 } 284 #else 285 ppi_regs_num = 1U; 286 #endif 287 /* 288 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 289 * This is a more scalable approach as it avoids clearing 290 * the enable bits in the GICD_CTLR. 291 */ 292 for (i = 0U; i < ppi_regs_num; ++i) { 293 gicr_write_icenabler(gicr_base, i, ~0U); 294 } 295 296 /* Wait for pending writes to GICR_ICENABLER */ 297 gicr_wait_for_pending_write(gicr_base); 298 299 /* 32 interrupt IDs per GICR_IGROUPR register */ 300 for (i = 0U; i < ppi_regs_num; ++i) { 301 /* Treat all SGIs/(E)PPIs as G1NS by default */ 302 gicr_write_igroupr(gicr_base, i, ~0U); 303 } 304 305 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 306 regs_num = ppi_regs_num << 3; 307 for (i = 0U; i < regs_num; ++i) { 308 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 309 gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL); 310 } 311 312 /* 16 interrupt IDs per GICR_ICFGR register */ 313 regs_num = ppi_regs_num << 1; 314 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 315 /* Configure all (E)PPIs as level triggered by default */ 316 gicr_write_icfgr(gicr_base, i, 0U); 317 } 318 } 319 320 /******************************************************************************* 321 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 322 ******************************************************************************/ 323 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 324 const interrupt_prop_t *interrupt_props, 325 unsigned int interrupt_props_num) 326 { 327 unsigned int i; 328 const interrupt_prop_t *current_prop; 329 unsigned int ctlr_enable = 0U; 330 331 /* Make sure there's a valid property array */ 332 if (interrupt_props_num > 0U) { 333 assert(interrupt_props != NULL); 334 } 335 336 for (i = 0U; i < interrupt_props_num; i++) { 337 current_prop = &interrupt_props[i]; 338 339 unsigned int intr_num = current_prop->intr_num; 340 341 /* Skip (E)SPI interrupt */ 342 if (!IS_SGI_PPI(intr_num)) { 343 continue; 344 } 345 346 /* Configure this interrupt as a secure interrupt */ 347 gicr_clr_igroupr(gicr_base, intr_num); 348 349 /* Configure this interrupt as G0 or a G1S interrupt */ 350 assert((current_prop->intr_grp == INTR_GROUP0) || 351 (current_prop->intr_grp == INTR_GROUP1S)); 352 353 if (current_prop->intr_grp == INTR_GROUP1S) { 354 gicr_set_igrpmodr(gicr_base, intr_num); 355 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 356 } else { 357 gicr_clr_igrpmodr(gicr_base, intr_num); 358 ctlr_enable |= CTLR_ENABLE_G0_BIT; 359 } 360 361 /* Set the priority of this interrupt */ 362 gicr_set_ipriorityr(gicr_base, intr_num, 363 current_prop->intr_pri); 364 365 /* 366 * Set interrupt configuration for (E)PPIs. 367 * Configurations for SGIs 0-15 are ignored. 368 */ 369 if (intr_num >= MIN_PPI_ID) { 370 gicr_set_icfgr(gicr_base, intr_num, 371 current_prop->intr_cfg); 372 } 373 374 /* Enable this interrupt */ 375 gicr_set_isenabler(gicr_base, intr_num); 376 } 377 378 return ctlr_enable; 379 } 380 381 /** 382 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 383 * @gicr_frame: base address of the GICR region to check 384 * 385 * This iterates over the GICR_TYPER registers of multiple GICR frames in 386 * a GICR region, to find the instance which has the LAST bit set. For most 387 * systems this corresponds to the number of cores handled by a redistributor, 388 * but there could be disabled cores among them. 389 * It assumes that each GICR region is fully accessible (till the LAST bit 390 * marks the end of the region). 391 * If a platform has multiple GICR regions, this function would need to be 392 * called multiple times, providing the respective GICR base address each time. 393 * 394 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 395 ******************************************************************************/ 396 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 397 { 398 uintptr_t rdistif_base = gicr_frame; 399 unsigned int count; 400 401 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) { 402 uint64_t typer_val = gicr_read_typer(rdistif_base); 403 404 if ((typer_val & TYPER_LAST_BIT) != 0U) { 405 break; 406 } 407 rdistif_base += gicv3_redist_size(typer_val); 408 } 409 410 return count; 411 } 412 413 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame) 414 { 415 unsigned int part_id; 416 417 /* 418 * The lower 8 bits of PIDR0, complemented by the lower 4 bits of 419 * PIDR1 contain a part number identifying the GIC component at a 420 * particular base address. 421 */ 422 part_id = mmio_read_32(gic_frame + GICD_PIDR0_GICV3) & 0xff; 423 part_id |= (mmio_read_32(gic_frame + GICD_PIDR1_GICV3) << 8) & 0xf00; 424 425 return part_id; 426 } 427 428 /******************************************************************************* 429 * Helper function to return product ID and revision of GIC 430 * @gicd_base: base address of the GIC distributor 431 * @gic_prod_id: retrieved product id of GIC 432 * @gic_rev: retrieved revision of GIC 433 ******************************************************************************/ 434 void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, 435 unsigned int *gic_prod_id, 436 uint8_t *gic_rev) 437 { 438 unsigned int gicd_iidr; 439 uint8_t gic_variant; 440 441 gicd_iidr = gicd_read_iidr(gicd_base); 442 *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT; 443 *gic_prod_id &= IIDR_PRODUCT_ID_MASK; 444 445 gic_variant = gicd_iidr >> IIDR_VARIANT_SHIFT; 446 gic_variant &= IIDR_VARIANT_MASK; 447 448 *gic_rev = gicd_iidr >> IIDR_REV_SHIFT; 449 *gic_rev &= IIDR_REV_MASK; 450 451 /* 452 * pack gic variant and gic_rev in 1 byte 453 * gic_rev = gic_variant[7:4] and gic_rev[0:3] 454 */ 455 *gic_rev = *gic_rev | gic_variant << 0x4; 456 457 } 458