1TF-A Build Instructions for Marvell Platforms 2============================================= 3 4This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. 5 6Build Instructions 7------------------ 8(1) Set the cross compiler 9 10 .. code:: shell 11 12 > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- 13 14(2) Set path for FIP images: 15 16Set U-Boot image path (relatively to TF-A root or absolute path) 17 18 .. code:: shell 19 20 > export BL33=path/to/u-boot.bin 21 22For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, 23BL33 should be ``~/project/u-boot/u-boot.bin`` 24 25 .. note:: 26 27 *u-boot.bin* should be used and not *u-boot-spl.bin* 28 29Set MSS/SCP image path (mandatory only for A7K/8K/CN913x) 30 31 .. code:: shell 32 33 > export SCP_BL2=path/to/mrvl_scp_bl2*.img 34 35(3) Armada-37x0 build requires WTP tools installation. 36 37See below in the section "Tools and external components installation". 38Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 39 40 .. code:: shell 41 42 > sudo apt-get install gcc-arm-linux-gnueabi 43 44(4) Clean previous build residuals (if any) 45 46 .. code:: shell 47 48 > make distclean 49 50(5) Build TF-A 51 52There are several build options: 53 54- DEBUG 55 56 Default is without debug information (=0). in order to enable it use ``DEBUG=1``. 57 Must be disabled when building UART recovery images due to current console driver 58 implementation that is not compatible with Xmodem protocol used for boot image download. 59 60- LOG_LEVEL 61 62 Defines the level of logging which will be purged to the default output port. 63 64 - 0 - LOG_LEVEL_NONE 65 - 10 - LOG_LEVEL_ERROR 66 - 20 - LOG_LEVEL_NOTICE (default for DEBUG=0) 67 - 30 - LOG_LEVEL_WARNING 68 - 40 - LOG_LEVEL_INFO (default for DEBUG=1) 69 - 50 - LOG_LEVEL_VERBOSE 70 71- USE_COHERENT_MEM 72 73 This flag determines whether to include the coherent memory region in the 74 BL memory map or not. Enabled by default. 75 76- LLC_ENABLE 77 78 Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). 79 80- LLC_SRAM 81 82 Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used 83 by Trusted OS (OP-TEE OS, BL32). The TF-A only prepares CCU address translation windows 84 for SRAM address range at BL31 execution stage with window target set to DRAM-0. 85 When Trusted OS activates LLC SRAM, the CCU window target is changed to SRAM. 86 There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n. 87 Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y. 88 89- CM3_SYSTEM_RESET 90 91 For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will 92 be used for system reset. 93 TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the 94 Cortex-M3 secure coprocessor. 95 The firmware running in the coprocessor must either implement this functionality or 96 ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell 97 repository). If this option is enabled but the firmware does not support this command, 98 an error message will be printed prior trying to reboot via the usual way. 99 100 This option is needed on Turris MOX as a workaround to a HW bug which causes reset to 101 sometime hang the board. 102 103- MARVELL_SECURE_BOOT 104 105 Build trusted(=1)/non trusted(=0) image, default is non trusted. 106 107- BLE_PATH 108 109 Points to BLE (Binary ROM extension) sources folder. 110 Only required for A7K/8K/CN913x builds. 111 The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``. 112 113- MV_DDR_PATH 114 115 For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, 116 it is used for ddr_tool build. 117 118 Usage example: MV_DDR_PATH=path/to/mv_ddr 119 120 The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr 121 sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter 122 is necessary for A37x0. 123 124 For the mv_ddr source location, check the section "Tools and external components installation" 125 126- CP_NUM 127 128 Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted, 129 the build uses the default number of CPs, which is a number of embedded CPs inside the 130 package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC 131 family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid 132 values with CP_NUM are in a range of 1 to 3. 133 134- DDR_TOPOLOGY 135 136 For Armada37x0 only, the DDR topology map index/name, default is 0. 137 138 Supported Options: 139 - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) 140 - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB) 141 - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS) 142 - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB) 143 - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) 144 - 5 - DDR4 1CS: EspressoBin V7 (1GB) 145 - 6 - DDR4 2CS: EspressoBin V7 (2GB) 146 - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB) 147 - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB 148 149- CLOCKSPRESET 150 151 For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, 152 default is CPU_800_DDR_800. 153 154 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz 155 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz 156 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz 157 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz 158 159- BOOTDEV 160 161 For Armada37x0 only, the flash boot device, default is ``SPINOR``. 162 163 Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: 164 165 - SPINOR - SPI NOR flash boot 166 - SPINAND - SPI NAND flash boot 167 - EMMCNORM - eMMC Download Mode 168 169 Download boot loader or program code from eMMC flash into CM3 or CA53 170 Requires full initialization and command sequence 171 172 - SATA - SATA device boot 173 174- PARTNUM 175 176 For Armada37x0 only, the boot partition number, default is 0. 177 178 To boot from eMMC, the value should be aligned with the parameter in 179 U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is 180 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot 181 build instructions. 182 183- WTMI_IMG 184 185 For Armada37x0 only, the path of the WTMI image can point to an image which 186 does nothing, an image which supports EFUSE or a customized CM3 firmware 187 binary. The default image is wtmi.bin that built from sources in WTP 188 folder, which is the next option. If the default image is OK, then this 189 option should be skipped. 190 191- WTP 192 193 For Armada37x0 only, use this parameter to point to wtptools source code 194 directory, which can be found as a3700_utils.zip in the release. Usage 195 example: ``WTP=/path/to/a3700_utils`` 196 197- CRYPTOPP_PATH 198 199 For Armada37x0 only, use this parameter tp point to Crypto++ source code 200 directory, which is required for building WTP image tool. 201 202 203For example, in order to build the image in debug mode with log level up to 'notice' level run 204 205.. code:: shell 206 207 > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> mrvl_flash 208 209And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, 210the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, 211the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command 212line is as following 213 214.. code:: shell 215 216 > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ 217 MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ 218 MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ 219 CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ 220 all fip mrvl_bootimage mrvl_flash 221 222To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command: 223 224.. code:: shell 225 226 > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \ 227 CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage 228 229You can build TF-A for the Globalscale ESPRESSObin-Ultra board (DDR4, 1 GB) by running the following command: 230 231.. code:: shell 232 233 > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1200_DDR_750 \ 234 MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=5 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \ 235 MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \ 236 CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \ 237 all fip mrvl_bootimage mrvl_flash 238 239Supported MARVELL_PLATFORM are: 240 - a3700 (for both A3720 DB and EspressoBin) 241 - a70x0 242 - a70x0_amc (for AMC board) 243 - a80x0 244 - a80x0_mcbin (for MacchiatoBin) 245 - a80x0_puzzle (for IEI Puzzle-M801) 246 - t9130 (OcteonTX2 CN913x) 247 248Special Build Flags 249-------------------- 250 251- PLAT_RECOVERY_IMAGE_ENABLE 252 When set this option to enable secondary recovery function when build atf. 253 In order to build UART recovery image this operation should be disabled for 254 A7K/8K/CN913x because of hardware limitation (boot from secondary image 255 can interrupt UART recovery process). This MACRO definition is set in 256 ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. 257 258- DDR32 259 In order to work in 32bit DDR, instead of the default 64bit ECC DDR, 260 this flag should be set to 1. 261 262For more information about build options, please refer to the 263:ref:`Build Options` document. 264 265 266Build output 267------------ 268Marvell's TF-A compilation generates 8 files: 269 270 - ble.bin - BLe image 271 - bl1.bin - BL1 image 272 - bl2.bin - BL2 image 273 - bl31.bin - BL31 image 274 - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) 275 - boot-image.bin - TF-A image (contains BL1 and FIP images) 276 - flash-image.bin - Image which contains boot-image.bin and SPL image. 277 Should be placed on the boot flash/device. 278 - uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images 279 for booting via UART. Could be loaded via Marvell's WtpDownload tool from 280 A3700-utils-marvell repository. 281 282Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target 283``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files. 284 285 286Tools and external components installation 287------------------------------------------ 288 289Armada37x0 Builds require installation of 3 components 290~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 291 292(1) ARM cross compiler capable of building images for the service CPU (CM3). 293 This component is usually included in the Linux host packages. 294 On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed 295 using the following command 296 297 .. code:: shell 298 299 > sudo apt-get install gcc-arm-linux-gnueabi 300 301 Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be 302 overwritten using the environment variable ``CROSS_CM3``. 303 Example for BASH shell 304 305 .. code:: shell 306 307 > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi 308 309(2) DDR initialization library sources (mv_ddr) available at the following repository 310 (use the "mv-ddr-devel" branch): 311 312 https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git 313 314(3) Armada3700 tools available at the following repository 315 (use the "A3700_utils-armada-18.12-fixed" branch): 316 317 https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git 318 319(4) Crypto++ library available at the following repository: 320 321 https://github.com/weidai11/cryptopp.git 322 323Armada70x0 and Armada80x0 Builds require installation of an additional component 324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 325 326(1) DDR initialization library sources (mv_ddr) available at the following repository 327 (use the "mv-ddr-devel" branch): 328 329 https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git 330