1c5407693SSandrine Bailleux.. _build_options_arm_fvp_platform: 2c5407693SSandrine Bailleux 3c5407693SSandrine BailleuxArm FVP Platform Specific Build Options 4c5407693SSandrine Bailleux--------------------------------------- 5c5407693SSandrine Bailleux 6c5407693SSandrine Bailleux- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 7c5407693SSandrine Bailleux build the topology tree within TF-A. By default TF-A is configured for dual 8c5407693SSandrine Bailleux cluster topology and this option can be used to override the default value. 9c5407693SSandrine Bailleux 10c5407693SSandrine Bailleux- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 11c5407693SSandrine Bailleux default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 12c5407693SSandrine Bailleux explained in the options below: 13c5407693SSandrine Bailleux 14c5407693SSandrine Bailleux - ``FVP_CCI`` : The CCI driver is selected. This is the default 15c5407693SSandrine Bailleux if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 16c5407693SSandrine Bailleux - ``FVP_CCN`` : The CCN driver is selected. This is the default 17c5407693SSandrine Bailleux if ``FVP_CLUSTER_COUNT`` > 2. 18c5407693SSandrine Bailleux 19c5407693SSandrine Bailleux- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 20c5407693SSandrine Bailleux a single cluster. This option defaults to 4. 21c5407693SSandrine Bailleux 22c5407693SSandrine Bailleux- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 23c5407693SSandrine Bailleux in the system. This option defaults to 1. Note that the build option 24c5407693SSandrine Bailleux ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 25c5407693SSandrine Bailleux 26c5407693SSandrine Bailleux- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 27c5407693SSandrine Bailleux 28c5407693SSandrine Bailleux - ``FVP_GICV2`` : The GICv2 only driver is selected 29c5407693SSandrine Bailleux - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 30c5407693SSandrine Bailleux 31c5407693SSandrine Bailleux- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 32c5407693SSandrine Bailleux to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 33c5407693SSandrine Bailleux details on HW_CONFIG. By default, this is initialized to a sensible DTS 34c5407693SSandrine Bailleux file in ``fdts/`` folder depending on other build options. But some cases, 35c5407693SSandrine Bailleux like shifted affinity format for MPIDR, cannot be detected at build time 36c5407693SSandrine Bailleux and this option is needed to specify the appropriate DTS file. 37c5407693SSandrine Bailleux 38c5407693SSandrine Bailleux- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 39c5407693SSandrine Bailleux FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 40c5407693SSandrine Bailleux similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 41c5407693SSandrine Bailleux HW_CONFIG blob instead of the DTS file. This option is useful to override 42c5407693SSandrine Bailleux the default HW_CONFIG selected by the build system. 43c5407693SSandrine Bailleux 44c5407693SSandrine Bailleux- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 45c5407693SSandrine Bailleux inactive/fused CPU cores as read-only. The default value of this option 46c5407693SSandrine Bailleux is ``0``, which means the redistributor pages of all CPU cores are marked 47c5407693SSandrine Bailleux as read and write. 48c5407693SSandrine Bailleux 49*0d49a415SSalman Nabi- ``INITRD_SIZE`` : Enable the insertion of initrd properties to the device 50*0d49a415SSalman Nabi tree blob at build time. Takes an initrd size value in hex format 51*0d49a415SSalman Nabi 52*0d49a415SSalman Nabi- ``INITRD_PATH`` : Enable the insertion of initrd properties to the device tree 53*0d49a415SSalman Nabi blob at build time. Takes a path to an initrd file. Can be used as an 54*0d49a415SSalman Nabi alternative to ``INITRD_SIZE``. ``INITRD_SIZE`` takes precedence over 55*0d49a415SSalman Nabi ``INITRD_PATH`` if both values are provided. 56*0d49a415SSalman Nabi 57*0d49a415SSalman Nabi- ``INITRD_BASE`` : Provide the preloaded initrd base address in memory (hex format). 58*0d49a415SSalman Nabi 59c5407693SSandrine Bailleux-------------- 60c5407693SSandrine Bailleux 61*0d49a415SSalman Nabi*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 62