1 /* 2 * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_features.h> 8 #include <common/debug.h> 9 #include <common/feat_detect.h> 10 #include <plat/common/platform.h> 11 12 static bool detection_done[PLATFORM_CORE_COUNT] = { false }; 13 14 /******************************************************************************* 15 * This section lists the wrapper modules for each feature to evaluate the 16 * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform 17 * necessary action as below: 18 * 19 * It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not. 20 * Without this check an exception would occur during context save/restore 21 * routines, if the feature is enabled but not supported by PE. 22 ******************************************************************************/ 23 24 #define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b)) 25 26 /******************************************************************************* 27 * Function : feature_panic 28 * Customised panic function with error logging mechanism to list the feature 29 * not supported by the PE. 30 ******************************************************************************/ 31 static inline void feature_panic(char *feat_name) 32 { 33 ERROR("FEAT_%s not supported by the PE\n", feat_name); 34 panic(); 35 } 36 37 /******************************************************************************* 38 * Function : check_feature 39 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and 40 * feature availability on the hardware. <min> is the smallest feature 41 * ID field value that is required for that feature. 42 * Triggers a panic later if a feature is forcefully enabled, but not 43 * available on the PE. Also will panic if the hardware feature ID field 44 * is larger than the maximum known and supported number, specified by <max>. 45 * 46 * We force inlining here to let the compiler optimise away the whole check 47 * if the feature is disabled at build time (FEAT_STATE_DISABLED). 48 ******************************************************************************/ 49 static inline bool __attribute((__always_inline__)) 50 check_feature(int state, unsigned long field, const char *feat_name, 51 unsigned int min, unsigned int max) 52 { 53 if (state == FEAT_STATE_ALWAYS && field < min) { 54 ERROR("FEAT_%s not supported by the PE\n", feat_name); 55 return true; 56 } 57 if (state >= FEAT_STATE_ALWAYS && field > max) { 58 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n", 59 feat_name, field, max); 60 return true; 61 } 62 63 return false; 64 } 65 66 static unsigned int read_feat_rng_trap_id_field(void) 67 { 68 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 69 ID_AA64PFR1_EL1_RNDR_TRAP_MASK); 70 } 71 72 static unsigned int read_feat_bti_id_field(void) 73 { 74 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, 75 ID_AA64PFR1_EL1_BT_MASK); 76 } 77 78 static unsigned int read_feat_sb_id_field(void) 79 { 80 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, 81 ID_AA64ISAR1_SB_MASK); 82 } 83 84 static unsigned int read_feat_csv2_id_field(void) 85 { 86 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, 87 ID_AA64PFR0_CSV2_MASK); 88 } 89 90 static unsigned int read_feat_debugv8p9_id_field(void) 91 { 92 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT, 93 ID_AA64DFR0_DEBUGVER_MASK); 94 } 95 96 static unsigned int read_feat_pmuv3_id_field(void) 97 { 98 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, 99 ID_AA64DFR0_PMUVER_MASK); 100 } 101 102 static unsigned int read_feat_vhe_id_field(void) 103 { 104 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, 105 ID_AA64MMFR1_EL1_VHE_MASK); 106 } 107 108 static unsigned int read_feat_sve_id_field(void) 109 { 110 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, 111 ID_AA64PFR0_SVE_MASK); 112 } 113 114 static unsigned int read_feat_ras_id_field(void) 115 { 116 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, 117 ID_AA64PFR0_RAS_MASK); 118 } 119 120 static unsigned int read_feat_dit_id_field(void) 121 { 122 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, 123 ID_AA64PFR0_DIT_MASK); 124 } 125 126 static unsigned int read_feat_amu_id_field(void) 127 { 128 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, 129 ID_AA64PFR0_AMU_MASK); 130 } 131 132 static unsigned int read_feat_mpam_version(void) 133 { 134 return (unsigned int)((((read_id_aa64pfr0_el1() >> 135 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 136 ((read_id_aa64pfr1_el1() >> 137 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 138 } 139 140 static unsigned int read_feat_nv_id_field(void) 141 { 142 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, 143 ID_AA64MMFR2_EL1_NV_MASK); 144 } 145 146 static unsigned int read_feat_sel2_id_field(void) 147 { 148 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, 149 ID_AA64PFR0_SEL2_MASK); 150 } 151 152 static unsigned int read_feat_trf_id_field(void) 153 { 154 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, 155 ID_AA64DFR0_TRACEFILT_MASK); 156 } 157 static unsigned int get_armv8_5_mte_support(void) 158 { 159 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, 160 ID_AA64PFR1_EL1_MTE_MASK); 161 } 162 static unsigned int read_feat_rng_id_field(void) 163 { 164 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, 165 ID_AA64ISAR0_RNDR_MASK); 166 } 167 static unsigned int read_feat_fgt_id_field(void) 168 { 169 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, 170 ID_AA64MMFR0_EL1_FGT_MASK); 171 } 172 static unsigned int read_feat_ecv_id_field(void) 173 { 174 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, 175 ID_AA64MMFR0_EL1_ECV_MASK); 176 } 177 static unsigned int read_feat_twed_id_field(void) 178 { 179 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, 180 ID_AA64MMFR1_EL1_TWED_MASK); 181 } 182 183 static unsigned int read_feat_hcx_id_field(void) 184 { 185 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, 186 ID_AA64MMFR1_EL1_HCX_MASK); 187 } 188 static unsigned int read_feat_ls64_id_field(void) 189 { 190 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT, 191 ID_AA64ISAR1_LS64_MASK); 192 } 193 static unsigned int read_feat_aie_id_field(void) 194 { 195 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT, 196 ID_AA64MMFR3_EL1_AIE_MASK); 197 } 198 static unsigned int read_feat_pfar_id_field(void) 199 { 200 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT, 201 ID_AA64PFR1_EL1_PFAR_MASK); 202 } 203 static unsigned int read_feat_tcr2_id_field(void) 204 { 205 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, 206 ID_AA64MMFR3_EL1_TCRX_MASK); 207 } 208 static unsigned int read_feat_s2pie_id_field(void) 209 { 210 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, 211 ID_AA64MMFR3_EL1_S2PIE_MASK); 212 } 213 static unsigned int read_feat_s1pie_id_field(void) 214 { 215 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, 216 ID_AA64MMFR3_EL1_S1PIE_MASK); 217 } 218 static unsigned int read_feat_s2poe_id_field(void) 219 { 220 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, 221 ID_AA64MMFR3_EL1_S2POE_MASK); 222 } 223 static unsigned int read_feat_s1poe_id_field(void) 224 { 225 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, 226 ID_AA64MMFR3_EL1_S1POE_MASK); 227 } 228 static unsigned int read_feat_brbe_id_field(void) 229 { 230 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, 231 ID_AA64DFR0_BRBE_MASK); 232 } 233 static unsigned int read_feat_trbe_id_field(void) 234 { 235 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, 236 ID_AA64DFR0_TRACEBUFFER_MASK); 237 } 238 static unsigned int read_feat_sme_id_field(void) 239 { 240 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, 241 ID_AA64PFR1_EL1_SME_MASK); 242 } 243 static unsigned int read_feat_gcs_id_field(void) 244 { 245 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, 246 ID_AA64PFR1_EL1_GCS_MASK); 247 } 248 249 static unsigned int read_feat_rme_id_field(void) 250 { 251 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, 252 ID_AA64PFR0_FEAT_RME_MASK); 253 } 254 255 static unsigned int read_feat_pan_id_field(void) 256 { 257 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, 258 ID_AA64MMFR1_EL1_PAN_MASK); 259 } 260 261 static unsigned int read_feat_mtpmu_id_field(void) 262 { 263 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 264 ID_AA64DFR0_MTPMU_MASK); 265 266 } 267 268 static unsigned int read_feat_the_id_field(void) 269 { 270 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT, 271 ID_AA64PFR1_EL1_THE_MASK); 272 } 273 274 static unsigned int read_feat_sctlr2_id_field(void) 275 { 276 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 277 ID_AA64MMFR3_EL1_SCTLR2_MASK); 278 } 279 280 static unsigned int read_feat_d128_id_field(void) 281 { 282 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT, 283 ID_AA64MMFR3_EL1_D128_MASK); 284 } 285 static unsigned int read_feat_gcie_id_field(void) 286 { 287 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT, 288 ID_AA64PFR2_EL1_GCIE_MASK); 289 } 290 291 static unsigned int read_feat_fpmr_id_field(void) 292 { 293 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT, 294 ID_AA64PFR2_EL1_FPMR_MASK); 295 } 296 297 static unsigned int read_feat_mops_id_field(void) 298 { 299 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT, 300 ID_AA64ISAR2_EL1_MOPS_MASK); 301 } 302 303 static unsigned int read_feat_fgwte3_id_field(void) 304 { 305 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 306 ID_AA64MMFR4_EL1_FGWTE3_MASK); 307 } 308 309 static unsigned int read_feat_cpa_id_field(void) 310 { 311 return ISOLATE_FIELD(read_id_aa64isar3_el1(), 312 ID_AA64ISAR3_EL1_CPA_SHIFT, 313 ID_AA64ISAR3_EL1_CPA_MASK); 314 } 315 316 /*********************************************************************************** 317 * TF-A supports many Arm architectural features starting from arch version 318 * (8.0 till 8.7+). These features are mostly enabled through build flags. This 319 * mechanism helps in validating these build flags in the early boot phase 320 * either in BL1 or BL31 depending on the platform and assists in identifying 321 * and notifying the features which are enabled but not supported by the PE. 322 * 323 * It reads all the enabled features ID-registers and ensures the features 324 * are supported by the PE. 325 * In case if they aren't it stops booting at an early phase and logs the error 326 * messages, notifying the platforms about the features that are not supported. 327 * 328 * Further the procedure is implemented with a tri-state approach for each feature: 329 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time 330 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. 331 * There will be panic if feature is not present at cold boot. 332 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime 333 * depending on hardware capability. 334 * 335 * For better readability, state values are defined with macros, namely: 336 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values 337 * { 0, 1, 2 }, respectively, as their naming. 338 **********************************************************************************/ 339 void detect_arch_features(unsigned int core_pos) 340 { 341 /* No need to keep checking after the first time for each core. */ 342 if (detection_done[core_pos]) { 343 return; 344 } 345 346 bool tainted = false; 347 348 /* v8.0 features */ 349 tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), 350 "SB", 1, 1); 351 tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), 352 "CSV2_2", 2, 3); 353 /* 354 * Even though the PMUv3 is an OPTIONAL feature, it is always 355 * implemented and Arm prescribes so. So assume it will be there and do 356 * away with a flag for it. This is used to check minor PMUv3px 357 * revisions so that we catch them as they come along 358 */ 359 tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), 360 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9); 361 362 /* v8.1 features */ 363 tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), 364 "PAN", 1, 3); 365 tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), 366 "VHE", 1, 1); 367 368 /* v8.2 features */ 369 tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), 370 "SVE", 1, 1); 371 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), 372 "RAS", 1, 2); 373 374 /* v8.3 features */ 375 /* the PAuth fields are very complicated, no min/max is checked */ 376 tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(), 377 "PAUTH", 1, 1); 378 379 /* v8.4 features */ 380 tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), 381 "DIT", 1, 1); 382 tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), 383 "AMUv1", 1, 2); 384 tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(), 385 "MOPS", 1, 1); 386 tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), 387 "MPAM", 1, 17); 388 tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), 389 "NV2", 2, 2); 390 tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), 391 "SEL2", 1, 1); 392 tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), 393 "TRF", 1, 1); 394 395 /* v8.5 features */ 396 tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), 397 "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); 398 tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), 399 "RNG", 1, 1); 400 tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(), 401 "BTI", 1, 1); 402 tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), 403 "RNG_TRAP", 1, 1); 404 405 /* v8.6 features */ 406 tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), 407 "AMUv1p1", 2, 2); 408 tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), 409 "FGT", 1, 2); 410 tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), 411 "FGT2", 2, 2); 412 tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), 413 "ECV", 1, 2); 414 tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), 415 "TWED", 1, 1); 416 417 /* 418 * even though this is a "DISABLE" it does confusingly perform feature 419 * enablement duties like all other flags here. Check it against the HW 420 * feature when we intend to diverge from the default behaviour 421 */ 422 tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), 423 "MTPMU", 1, 1); 424 425 /* v8.7 features */ 426 tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), 427 "HCX", 1, 1); 428 tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), 429 "LS64", 1, 3); 430 431 /* v8.9 features */ 432 tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), 433 "TCR2", 1, 1); 434 tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), 435 "S2PIE", 1, 1); 436 tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), 437 "S1PIE", 1, 1); 438 tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), 439 "S2POE", 1, 1); 440 tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), 441 "S1POE", 1, 1); 442 tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), 443 "CSV2_3", 3, 3); 444 tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(), 445 "DEBUGV8P9", 11, 11); 446 tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(), 447 "THE", 1, 1); 448 tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(), 449 "SCTLR2", 1, 1); 450 tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(), 451 "AIE", 1, 1); 452 tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(), 453 "PFAR", 1, 1); 454 455 /* v9.0 features */ 456 tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), 457 "BRBE", 1, 2); 458 tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), 459 "TRBE", 1, 1); 460 461 /* v9.2 features */ 462 tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), 463 "SME", 1, 2); 464 tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), 465 "SME2", 2, 2); 466 tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(), 467 "FPMR", 1, 1); 468 469 /* v9.3 features */ 470 tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(), 471 "D128", 1, 1); 472 tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(), 473 "GCIE", 1, 1); 474 tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL, 475 is_feat_mpam_pe_bw_ctrl_present(), 476 "MPAM_PE_BW_CTRL", 1, 1); 477 478 /* v9.4 features */ 479 tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), 480 "GCS", 1, 1); 481 tainted |= check_feature(ENABLE_RME, read_feat_rme_id_field(), 482 "RME", 1, 1); 483 tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), 484 "PAUTH_LR", 1, 1); 485 tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(), 486 "FGWTE3", 1, 1); 487 tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(), 488 "CPA2", 2, 2); 489 490 if (tainted) { 491 panic(); 492 } 493 494 detection_done[core_pos] = true; 495 } 496