1 /* 2 * Copyright (c) 2022-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_features.h> 8 #include <common/debug.h> 9 #include <common/feat_detect.h> 10 #include <plat/common/platform.h> 11 12 static bool detection_done[PLATFORM_CORE_COUNT] = { false }; 13 14 /******************************************************************************* 15 * Function : check_feature 16 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and 17 * feature availability on the hardware. <min> is the smallest feature 18 * ID field value that is required for that feature. 19 * Triggers a panic later if a feature is forcefully enabled, but not 20 * available on the PE. Also will panic if the hardware feature ID field 21 * is larger than the maximum known and supported number, specified by <max>. 22 * 23 * We force inlining here to let the compiler optimise away the whole check 24 * if the feature is disabled at build time (FEAT_STATE_DISABLED). 25 ******************************************************************************/ 26 static inline bool __attribute((__always_inline__)) 27 check_feature(int state, unsigned long field, const char *feat_name, 28 unsigned int min, unsigned int max) 29 { 30 if (state == FEAT_STATE_ALWAYS && field < min) { 31 ERROR("FEAT_%s not supported by the PE\n", feat_name); 32 return true; 33 } 34 if (state >= FEAT_STATE_ALWAYS && field > max) { 35 ERROR("FEAT_%s is version %lu, but is only known up to version %u\n", 36 feat_name, field, max); 37 return true; 38 } 39 40 return false; 41 } 42 43 static unsigned int read_feat_rng_trap_id_field(void) 44 { 45 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 46 ID_AA64PFR1_EL1_RNDR_TRAP_MASK); 47 } 48 49 static unsigned int read_feat_bti_id_field(void) 50 { 51 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, 52 ID_AA64PFR1_EL1_BT_MASK); 53 } 54 55 static unsigned int read_feat_sb_id_field(void) 56 { 57 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, 58 ID_AA64ISAR1_SB_MASK); 59 } 60 61 static unsigned int read_feat_csv2_id_field(void) 62 { 63 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, 64 ID_AA64PFR0_CSV2_MASK); 65 } 66 67 static unsigned int read_feat_debugv8p9_id_field(void) 68 { 69 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT, 70 ID_AA64DFR0_DEBUGVER_MASK); 71 } 72 73 static unsigned int read_feat_step2_id_field(void) 74 { 75 return ISOLATE_FIELD(read_id_aa64dfr2_el1(), ID_AA64DFR2_STEP_SHIFT, 76 ID_AA64DFR2_STEP_MASK); 77 } 78 79 static unsigned int read_feat_pmuv3_id_field(void) 80 { 81 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, 82 ID_AA64DFR0_PMUVER_MASK); 83 } 84 85 static unsigned int read_feat_vhe_id_field(void) 86 { 87 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, 88 ID_AA64MMFR1_EL1_VHE_MASK); 89 } 90 91 static unsigned int read_feat_spe_id_field(void) 92 { 93 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS_SHIFT, 94 ID_AA64DFR0_PMS_MASK); 95 } 96 97 static unsigned int read_feat_sve_id_field(void) 98 { 99 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, 100 ID_AA64PFR0_SVE_MASK); 101 } 102 103 static unsigned int read_feat_ras_id_field(void) 104 { 105 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, 106 ID_AA64PFR0_RAS_MASK); 107 } 108 109 static unsigned int read_feat_iesb_id_field(void) 110 { 111 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_IESB_SHIFT, 112 ID_AA64MMFR2_EL1_IESB_MASK); 113 } 114 115 static unsigned int read_feat_dit_id_field(void) 116 { 117 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, 118 ID_AA64PFR0_DIT_MASK); 119 } 120 121 static unsigned int read_feat_amu_id_field(void) 122 { 123 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, 124 ID_AA64PFR0_AMU_MASK); 125 } 126 127 static unsigned int read_feat_mpam_version(void) 128 { 129 return (unsigned int)((((read_id_aa64pfr0_el1() >> 130 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 131 ((read_id_aa64pfr1_el1() >> 132 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 133 } 134 135 static unsigned int read_feat_nv_id_field(void) 136 { 137 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, 138 ID_AA64MMFR2_EL1_NV_MASK); 139 } 140 141 static unsigned int read_feat_sel2_id_field(void) 142 { 143 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, 144 ID_AA64PFR0_SEL2_MASK); 145 } 146 147 static unsigned int read_feat_trf_id_field(void) 148 { 149 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, 150 ID_AA64DFR0_TRACEFILT_MASK); 151 } 152 static unsigned int get_armv8_5_mte_support(void) 153 { 154 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, 155 ID_AA64PFR1_EL1_MTE_MASK); 156 } 157 static unsigned int read_feat_rng_id_field(void) 158 { 159 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, 160 ID_AA64ISAR0_RNDR_MASK); 161 } 162 static unsigned int read_feat_fgt_id_field(void) 163 { 164 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, 165 ID_AA64MMFR0_EL1_FGT_MASK); 166 } 167 static unsigned int read_feat_ecv_id_field(void) 168 { 169 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, 170 ID_AA64MMFR0_EL1_ECV_MASK); 171 } 172 static unsigned int read_feat_twed_id_field(void) 173 { 174 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, 175 ID_AA64MMFR1_EL1_TWED_MASK); 176 } 177 178 static unsigned int read_feat_hcx_id_field(void) 179 { 180 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, 181 ID_AA64MMFR1_EL1_HCX_MASK); 182 } 183 static unsigned int read_feat_ls64_id_field(void) 184 { 185 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT, 186 ID_AA64ISAR1_LS64_MASK); 187 } 188 static unsigned int read_feat_aie_id_field(void) 189 { 190 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT, 191 ID_AA64MMFR3_EL1_AIE_MASK); 192 } 193 static unsigned int read_feat_pfar_id_field(void) 194 { 195 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT, 196 ID_AA64PFR1_EL1_PFAR_MASK); 197 } 198 static unsigned int read_feat_tcr2_id_field(void) 199 { 200 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, 201 ID_AA64MMFR3_EL1_TCRX_MASK); 202 } 203 static unsigned int read_feat_s2pie_id_field(void) 204 { 205 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, 206 ID_AA64MMFR3_EL1_S2PIE_MASK); 207 } 208 static unsigned int read_feat_s1pie_id_field(void) 209 { 210 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, 211 ID_AA64MMFR3_EL1_S1PIE_MASK); 212 } 213 static unsigned int read_feat_s2poe_id_field(void) 214 { 215 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, 216 ID_AA64MMFR3_EL1_S2POE_MASK); 217 } 218 static unsigned int read_feat_s1poe_id_field(void) 219 { 220 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, 221 ID_AA64MMFR3_EL1_S1POE_MASK); 222 } 223 static unsigned int read_feat_brbe_id_field(void) 224 { 225 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, 226 ID_AA64DFR0_BRBE_MASK); 227 } 228 static unsigned int read_feat_trbe_id_field(void) 229 { 230 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, 231 ID_AA64DFR0_TRACEBUFFER_MASK); 232 } 233 static unsigned int read_feat_sme_id_field(void) 234 { 235 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, 236 ID_AA64PFR1_EL1_SME_MASK); 237 } 238 static unsigned int read_feat_gcs_id_field(void) 239 { 240 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, 241 ID_AA64PFR1_EL1_GCS_MASK); 242 } 243 244 static unsigned int read_feat_rme_id_field(void) 245 { 246 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, 247 ID_AA64PFR0_FEAT_RME_MASK); 248 } 249 250 static unsigned int read_feat_pan_id_field(void) 251 { 252 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, 253 ID_AA64MMFR1_EL1_PAN_MASK); 254 } 255 256 static unsigned int read_feat_mtpmu_id_field(void) 257 { 258 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 259 ID_AA64DFR0_MTPMU_MASK); 260 261 } 262 263 static unsigned int read_feat_the_id_field(void) 264 { 265 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT, 266 ID_AA64PFR1_EL1_THE_MASK); 267 } 268 269 static unsigned int read_feat_sctlr2_id_field(void) 270 { 271 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 272 ID_AA64MMFR3_EL1_SCTLR2_MASK); 273 } 274 275 static unsigned int read_feat_d128_id_field(void) 276 { 277 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT, 278 ID_AA64MMFR3_EL1_D128_MASK); 279 } 280 static unsigned int read_feat_gcie_id_field(void) 281 { 282 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT, 283 ID_AA64PFR2_EL1_GCIE_MASK); 284 } 285 286 static unsigned int read_feat_ebep_id_field(void) 287 { 288 return ISOLATE_FIELD(read_id_aa64dfr1_el1(), ID_AA64DFR1_EBEP_SHIFT, 289 ID_AA64DFR1_EBEP_MASK); 290 } 291 292 static unsigned int read_feat_fpmr_id_field(void) 293 { 294 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT, 295 ID_AA64PFR2_EL1_FPMR_MASK); 296 } 297 298 static unsigned int read_feat_mops_id_field(void) 299 { 300 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT, 301 ID_AA64ISAR2_EL1_MOPS_MASK); 302 } 303 304 static unsigned int read_feat_fgwte3_id_field(void) 305 { 306 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 307 ID_AA64MMFR4_EL1_FGWTE3_MASK); 308 } 309 310 static unsigned int read_feat_cpa_id_field(void) 311 { 312 return ISOLATE_FIELD(read_id_aa64isar3_el1(), 313 ID_AA64ISAR3_EL1_CPA_SHIFT, 314 ID_AA64ISAR3_EL1_CPA_MASK); 315 } 316 317 static unsigned int read_feat_clrbhb_id_field(void) 318 { 319 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_CLRBHB_SHIFT, 320 ID_AA64ISAR2_CLRBHB_MASK); 321 } 322 323 static unsigned int read_feat_rme_gdi_id_field(void) 324 { 325 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), 326 ID_AA64MMFR4_EL1_RME_GDI_SHIFT, 327 ID_AA64MMFR4_EL1_RME_GDI_MASK); 328 } 329 330 static unsigned int read_feat_idte3_id_field(void) 331 { 332 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_IDS_SHIFT, 333 ID_AA64MMFR2_EL1_IDS_MASK); 334 } 335 336 static unsigned int read_feat_uinj_id_field(void) 337 { 338 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), 339 ID_AA64PFR2_EL1_UINJ_SHIFT, 340 ID_AA64PFR2_EL1_UINJ_MASK); 341 } 342 343 static unsigned int read_feat_lse_id_field(void) 344 { 345 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_ATOMIC_SHIFT, 346 ID_AA64ISAR0_ATOMIC_MASK); 347 } 348 349 static unsigned int read_feat_morello_field(void) 350 { 351 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_CE_SHIFT, 352 ID_AA64PFR1_EL1_CE_MASK); 353 } 354 355 static unsigned int read_feat_hdbss_id_field(void) 356 { 357 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 358 ID_AA64MMFR1_EL1_HAFDBS_MASK); 359 } 360 361 static unsigned int read_feat_hacdbs_id_field(void) 362 { 363 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_HACDBS_SHIFT, 364 ID_AA64MMFR4_EL1_HACDBS_MASK); 365 } 366 367 /*********************************************************************************** 368 * TF-A supports many Arm architectural features starting from arch version 369 * (8.0 till 8.7+). These features are mostly enabled through build flags. This 370 * mechanism helps in validating these build flags in the early boot phase 371 * either in BL1 or BL31 depending on the platform and assists in identifying 372 * and notifying the features which are enabled but not supported by the PE. 373 * 374 * It reads all the enabled features ID-registers and ensures the features 375 * are supported by the PE. 376 * In case if they aren't it stops booting at an early phase and logs the error 377 * messages, notifying the platforms about the features that are not supported. 378 * 379 * Further the procedure is implemented with a tri-state approach for each feature: 380 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time 381 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. 382 * There will be panic if feature is not present at cold boot. 383 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime 384 * depending on hardware capability. 385 * 386 * For better readability, state values are defined with macros, namely: 387 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values 388 * { 0, 1, 2 }, respectively, as their naming. 389 **********************************************************************************/ 390 void detect_arch_features(unsigned int core_pos) 391 { 392 /* No need to keep checking after the first time for each core. */ 393 if (detection_done[core_pos]) { 394 return; 395 } 396 397 bool tainted = false; 398 399 /* v8.0 features */ 400 tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), 401 "SB", 1, 1); 402 tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), 403 "CSV2_2", 2, 3); 404 tainted |= check_feature(ENABLE_FEAT_CLRBHB, read_feat_clrbhb_id_field(), 405 "CLRBHB", 1, 1); 406 /* 407 * Even though the PMUv3 is an OPTIONAL feature, it is always 408 * implemented and Arm prescribes so. So assume it will be there and do 409 * away with a flag for it. This is used to check minor PMUv3px 410 * revisions so that we catch them as they come along 411 */ 412 tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), 413 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9); 414 415 tainted |= check_feature(USE_SPINLOCK_CAS, read_feat_lse_id_field(), 416 "LSE", 2, 3); 417 418 /* v8.1 features */ 419 tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), 420 "PAN", 1, 3); 421 tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), 422 "VHE", 1, 1); 423 tainted |= check_feature(ENABLE_SPE_FOR_NS, read_feat_spe_id_field(), 424 "SPE", 1, 6); 425 426 /* v8.2 features */ 427 tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), 428 "SVE", 1, 3); 429 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), 430 "RAS", 1, 3); 431 /* FEAT_RAS's enablement hinges on FEAT_IESB also being present */ 432 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_iesb_id_field(), 433 "IESB", 1, 2); 434 435 /* v8.3 features */ 436 /* the PAuth fields are very complicated, no min/max is checked */ 437 tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(), 438 "PAUTH", 1, 1); 439 440 /* v8.4 features */ 441 tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), 442 "DIT", 1, 1); 443 tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), 444 "AMUv1", 1, 2); 445 tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(), 446 "MOPS", 1, 1); 447 tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), 448 "MPAM", 1, 17); 449 tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), 450 "NV2", 2, 2); 451 tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), 452 "SEL2", 1, 1); 453 tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), 454 "TRF", 1, 1); 455 456 /* v8.5 features */ 457 tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), 458 "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); 459 tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), 460 "RNG", 1, 1); 461 tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(), 462 "BTI", 1, 1); 463 tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), 464 "RNG_TRAP", 1, 1); 465 466 /* v8.6 features */ 467 tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), 468 "AMUv1p1", 2, 2); 469 tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), 470 "FGT", 1, 2); 471 tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), 472 "FGT2", 2, 2); 473 tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), 474 "ECV", 1, 2); 475 tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), 476 "TWED", 1, 1); 477 478 /* 479 * even though this is a "DISABLE" it does confusingly perform feature 480 * enablement duties like all other flags here. Check it against the HW 481 * feature when we intend to diverge from the default behaviour 482 */ 483 tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), 484 "MTPMU", 1, 15); 485 if (read_feat_mtpmu_id_field() == 15) { 486 WARN("DISABLE_MTPMU is implemented in hardware, flag is redundant.\n"); 487 } 488 489 /* v8.7 features */ 490 tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), 491 "HCX", 1, 1); 492 tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), 493 "LS64", 1, 3); 494 495 /* v8.9 features */ 496 tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), 497 "TCR2", 1, 1); 498 tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), 499 "S2PIE", 1, 1); 500 tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), 501 "S1PIE", 1, 1); 502 tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), 503 "S2POE", 1, 1); 504 tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), 505 "S1POE", 1, 1); 506 tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), 507 "CSV2_3", 3, 3); 508 tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(), 509 "DEBUGV8P9", 11, 11); 510 tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(), 511 "THE", 1, 1); 512 tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(), 513 "SCTLR2", 1, 1); 514 tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(), 515 "AIE", 1, 1); 516 tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(), 517 "PFAR", 1, 1); 518 519 /* v9.0 features */ 520 tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), 521 "BRBE", 1, 2); 522 tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), 523 "TRBE", 1, 2); 524 tainted |= check_feature(ENABLE_FEAT_UINJ, read_feat_uinj_id_field(), 525 "UINJ", 1, 1); 526 527 /* v9.2 features */ 528 tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), 529 "SME", 1, 2); 530 tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), 531 "SME2", 2, 3); 532 tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(), 533 "FPMR", 1, 1); 534 tainted |= check_feature(ENABLE_FEAT_RME, read_feat_rme_id_field(), 535 "RME", 1, 2); 536 537 /* v9.3 features */ 538 tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(), 539 "D128", 1, 1); 540 tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(), 541 "GCIE", 1, 1); 542 tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL, 543 is_feat_mpam_pe_bw_ctrl_present(), 544 "MPAM_PE_BW_CTRL", 1, 1); 545 tainted |= check_feature(ENABLE_FEAT_EBEP, read_feat_ebep_id_field(), 546 "EBEP", 1, 1); 547 548 /* v9.4 features */ 549 tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), 550 "GCS", 1, 1); 551 tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), 552 "PAUTH_LR", 1, 1); 553 tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(), 554 "FGWTE3", 1, 1); 555 tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(), 556 "CPA2", 2, 2); 557 tainted |= check_feature(ENABLE_FEAT_RME_GDI, read_feat_rme_gdi_id_field(), 558 "RME_GDI", 1, 1); 559 tainted |= check_feature(ENABLE_FEAT_IDTE3, read_feat_idte3_id_field(), 560 "IDTE3", 2, 2); 561 tainted |= check_feature(ENABLE_FEAT_STEP2, read_feat_step2_id_field(), 562 "STEP2", 1, 1); 563 tainted |= check_feature(ENABLE_FEAT_HDBSS, read_feat_hdbss_id_field(), 564 "HDBSS", 4, 4); 565 tainted |= check_feature(ENABLE_FEAT_HACDBS, read_feat_hacdbs_id_field(), 566 "HACDBS", 1, 1); 567 568 /* Morello Arch feature */ 569 tainted |= check_feature(ENABLE_FEAT_MORELLO, read_feat_morello_field(), 570 "MORELLO_ARCH", 1, 1); 571 572 if (tainted) { 573 panic(); 574 } 575 576 detection_done[core_pos] = true; 577 } 578