1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <bl_common.h> 33 #include <bl32.h> 34 #include <debug.h> 35 #include <platform.h> 36 #include <spinlock.h> 37 #include <stdio.h> 38 #include <tsp.h> 39 40 /******************************************************************************* 41 * Declarations of linker defined symbols which will help us find the layout 42 * of trusted SRAM 43 ******************************************************************************/ 44 extern unsigned long __RO_START__; 45 extern unsigned long __COHERENT_RAM_END__; 46 47 /******************************************************************************* 48 * Lock to control access to the console 49 ******************************************************************************/ 50 spinlock_t console_lock; 51 52 /******************************************************************************* 53 * Per cpu data structure to populate parameters for an SMC in C code and use 54 * a pointer to this structure in assembler code to populate x0-x7 55 ******************************************************************************/ 56 static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; 57 58 /******************************************************************************* 59 * Per cpu data structure to keep track of TSP activity 60 ******************************************************************************/ 61 work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; 62 63 /******************************************************************************* 64 * Single reference to the various entry points exported by the test secure 65 * payload. A single copy should suffice for all cpus as they are not expected 66 * to change. 67 ******************************************************************************/ 68 static const entry_info_t tsp_entry_info = { 69 tsp_std_smc_entry, 70 tsp_fast_smc_entry, 71 tsp_cpu_on_entry, 72 tsp_cpu_off_entry, 73 tsp_cpu_resume_entry, 74 tsp_cpu_suspend_entry, 75 tsp_fiq_entry, 76 }; 77 78 79 /******************************************************************************* 80 * The BL32 memory footprint starts with an RO sections and ends 81 * with a section for coherent RAM. Use it to find the memory size 82 ******************************************************************************/ 83 #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) 84 85 #define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 86 87 static tsp_args_t *set_smc_args(uint64_t arg0, 88 uint64_t arg1, 89 uint64_t arg2, 90 uint64_t arg3, 91 uint64_t arg4, 92 uint64_t arg5, 93 uint64_t arg6, 94 uint64_t arg7) 95 { 96 uint64_t mpidr = read_mpidr(); 97 uint32_t linear_id; 98 tsp_args_t *pcpu_smc_args; 99 100 /* 101 * Return to Secure Monitor by raising an SMC. The results of the 102 * service are passed as an arguments to the SMC 103 */ 104 linear_id = platform_get_core_pos(mpidr); 105 pcpu_smc_args = &tsp_smc_args[linear_id]; 106 write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); 107 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); 108 write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); 109 write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); 110 write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); 111 write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); 112 write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); 113 write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); 114 115 return pcpu_smc_args; 116 } 117 118 /******************************************************************************* 119 * TSP main entry point where it gets the opportunity to initialize its secure 120 * state/applications. Once the state is initialized, it must return to the 121 * SPD with a pointer to the 'tsp_entry_info' structure. 122 ******************************************************************************/ 123 uint64_t tsp_main(void) 124 { 125 uint64_t mpidr = read_mpidr(); 126 uint32_t linear_id = platform_get_core_pos(mpidr); 127 128 /* Initialize the platform */ 129 bl32_platform_setup(); 130 131 /* Initialize secure/applications state here */ 132 tsp_generic_timer_start(); 133 134 /* Update this cpu's statistics */ 135 tsp_stats[linear_id].smc_count++; 136 tsp_stats[linear_id].eret_count++; 137 tsp_stats[linear_id].cpu_on_count++; 138 139 spin_lock(&console_lock); 140 printf("TSP %s\n\r", build_message); 141 INFO("Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE); 142 INFO("Total memory size : 0x%x bytes\n", 143 (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE)); 144 INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, 145 tsp_stats[linear_id].smc_count, 146 tsp_stats[linear_id].eret_count, 147 tsp_stats[linear_id].cpu_on_count); 148 spin_unlock(&console_lock); 149 150 /* 151 * TODO: There is a massive assumption that the SPD and SP can see each 152 * other's memory without issues so it is safe to pass pointers to 153 * internal memory. Replace this with a shared communication buffer. 154 */ 155 return (uint64_t) &tsp_entry_info; 156 } 157 158 /******************************************************************************* 159 * This function performs any remaining book keeping in the test secure payload 160 * after this cpu's architectural state has been setup in response to an earlier 161 * psci cpu_on request. 162 ******************************************************************************/ 163 tsp_args_t *tsp_cpu_on_main(void) 164 { 165 uint64_t mpidr = read_mpidr(); 166 uint32_t linear_id = platform_get_core_pos(mpidr); 167 168 /* Initialize secure/applications state here */ 169 tsp_generic_timer_start(); 170 171 /* Update this cpu's statistics */ 172 tsp_stats[linear_id].smc_count++; 173 tsp_stats[linear_id].eret_count++; 174 tsp_stats[linear_id].cpu_on_count++; 175 176 spin_lock(&console_lock); 177 printf("SP: cpu 0x%x turned on\n\r", mpidr); 178 INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, 179 tsp_stats[linear_id].smc_count, 180 tsp_stats[linear_id].eret_count, 181 tsp_stats[linear_id].cpu_on_count); 182 spin_unlock(&console_lock); 183 184 /* Indicate to the SPD that we have completed turned ourselves on */ 185 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); 186 } 187 188 /******************************************************************************* 189 * This function performs any remaining book keeping in the test secure payload 190 * before this cpu is turned off in response to a psci cpu_off request. 191 ******************************************************************************/ 192 tsp_args_t *tsp_cpu_off_main(uint64_t arg0, 193 uint64_t arg1, 194 uint64_t arg2, 195 uint64_t arg3, 196 uint64_t arg4, 197 uint64_t arg5, 198 uint64_t arg6, 199 uint64_t arg7) 200 { 201 uint64_t mpidr = read_mpidr(); 202 uint32_t linear_id = platform_get_core_pos(mpidr); 203 204 /* 205 * This cpu is being turned off, so disable the timer to prevent the 206 * secure timer interrupt from interfering with power down. A pending 207 * interrupt will be lost but we do not care as we are turning off. 208 */ 209 tsp_generic_timer_stop(); 210 211 /* Update this cpu's statistics */ 212 tsp_stats[linear_id].smc_count++; 213 tsp_stats[linear_id].eret_count++; 214 tsp_stats[linear_id].cpu_off_count++; 215 216 spin_lock(&console_lock); 217 printf("SP: cpu 0x%x off request\n\r", mpidr); 218 INFO("cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, 219 tsp_stats[linear_id].smc_count, 220 tsp_stats[linear_id].eret_count, 221 tsp_stats[linear_id].cpu_off_count); 222 spin_unlock(&console_lock); 223 224 225 /* Indicate to the SPD that we have completed this request */ 226 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); 227 } 228 229 /******************************************************************************* 230 * This function performs any book keeping in the test secure payload before 231 * this cpu's architectural state is saved in response to an earlier psci 232 * cpu_suspend request. 233 ******************************************************************************/ 234 tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state, 235 uint64_t arg1, 236 uint64_t arg2, 237 uint64_t arg3, 238 uint64_t arg4, 239 uint64_t arg5, 240 uint64_t arg6, 241 uint64_t arg7) 242 { 243 uint64_t mpidr = read_mpidr(); 244 uint32_t linear_id = platform_get_core_pos(mpidr); 245 246 /* 247 * Save the time context and disable it to prevent the secure timer 248 * interrupt from interfering with wakeup from the suspend state. 249 */ 250 tsp_generic_timer_save(); 251 tsp_generic_timer_stop(); 252 253 /* Update this cpu's statistics */ 254 tsp_stats[linear_id].smc_count++; 255 tsp_stats[linear_id].eret_count++; 256 tsp_stats[linear_id].cpu_suspend_count++; 257 258 spin_lock(&console_lock); 259 printf("SP: cpu 0x%x suspend request. power state: 0x%x\n\r", 260 mpidr, power_state); 261 INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, 262 tsp_stats[linear_id].smc_count, 263 tsp_stats[linear_id].eret_count, 264 tsp_stats[linear_id].cpu_suspend_count); 265 spin_unlock(&console_lock); 266 267 /* Indicate to the SPD that we have completed this request */ 268 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); 269 } 270 271 /******************************************************************************* 272 * This function performs any book keeping in the test secure payload after this 273 * cpu's architectural state has been restored after wakeup from an earlier psci 274 * cpu_suspend request. 275 ******************************************************************************/ 276 tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, 277 uint64_t arg1, 278 uint64_t arg2, 279 uint64_t arg3, 280 uint64_t arg4, 281 uint64_t arg5, 282 uint64_t arg6, 283 uint64_t arg7) 284 { 285 uint64_t mpidr = read_mpidr(); 286 uint32_t linear_id = platform_get_core_pos(mpidr); 287 288 /* Restore the generic timer context */ 289 tsp_generic_timer_restore(); 290 291 /* Update this cpu's statistics */ 292 tsp_stats[linear_id].smc_count++; 293 tsp_stats[linear_id].eret_count++; 294 tsp_stats[linear_id].cpu_resume_count++; 295 296 spin_lock(&console_lock); 297 printf("SP: cpu 0x%x resumed. suspend level %d \n\r", 298 mpidr, suspend_level); 299 INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, 300 tsp_stats[linear_id].smc_count, 301 tsp_stats[linear_id].eret_count, 302 tsp_stats[linear_id].cpu_suspend_count); 303 spin_unlock(&console_lock); 304 305 /* Indicate to the SPD that we have completed this request */ 306 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); 307 } 308 309 /******************************************************************************* 310 * TSP fast smc handler. The secure monitor jumps to this function by 311 * doing the ERET after populating X0-X7 registers. The arguments are received 312 * in the function arguments in order. Once the service is rendered, this 313 * function returns to Secure Monitor by raising SMC. 314 ******************************************************************************/ 315 tsp_args_t *tsp_smc_handler(uint64_t func, 316 uint64_t arg1, 317 uint64_t arg2, 318 uint64_t arg3, 319 uint64_t arg4, 320 uint64_t arg5, 321 uint64_t arg6, 322 uint64_t arg7) 323 { 324 uint64_t results[2]; 325 uint64_t service_args[2]; 326 uint64_t mpidr = read_mpidr(); 327 uint32_t linear_id = platform_get_core_pos(mpidr); 328 const char *smc_type; 329 330 /* Update this cpu's statistics */ 331 tsp_stats[linear_id].smc_count++; 332 tsp_stats[linear_id].eret_count++; 333 334 smc_type = ((func >> 31) & 1) == 1 ? "fast" : "standard"; 335 336 printf("SP: cpu 0x%x received %s smc 0x%x\n", read_mpidr(), smc_type, func); 337 INFO("cpu 0x%x: %d smcs, %d erets\n", mpidr, 338 tsp_stats[linear_id].smc_count, 339 tsp_stats[linear_id].eret_count); 340 341 /* Render secure services and obtain results here */ 342 results[0] = arg1; 343 results[1] = arg2; 344 345 /* 346 * Request a service back from dispatcher/secure monitor. This call 347 * return and thereafter resume exectuion 348 */ 349 tsp_get_magic(service_args); 350 351 /* Determine the function to perform based on the function ID */ 352 switch (TSP_BARE_FID(func)) { 353 case TSP_ADD: 354 results[0] += service_args[0]; 355 results[1] += service_args[1]; 356 break; 357 case TSP_SUB: 358 results[0] -= service_args[0]; 359 results[1] -= service_args[1]; 360 break; 361 case TSP_MUL: 362 results[0] *= service_args[0]; 363 results[1] *= service_args[1]; 364 break; 365 case TSP_DIV: 366 results[0] /= service_args[0] ? service_args[0] : 1; 367 results[1] /= service_args[1] ? service_args[1] : 1; 368 break; 369 default: 370 break; 371 } 372 373 return set_smc_args(func, 0, 374 results[0], 375 results[1], 376 0, 0, 0, 0); 377 } 378 379