17c88f3f6SAchin Gupta /* 27c88f3f6SAchin Gupta * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 37c88f3f6SAchin Gupta * 47c88f3f6SAchin Gupta * Redistribution and use in source and binary forms, with or without 57c88f3f6SAchin Gupta * modification, are permitted provided that the following conditions are met: 67c88f3f6SAchin Gupta * 77c88f3f6SAchin Gupta * Redistributions of source code must retain the above copyright notice, this 87c88f3f6SAchin Gupta * list of conditions and the following disclaimer. 97c88f3f6SAchin Gupta * 107c88f3f6SAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 117c88f3f6SAchin Gupta * this list of conditions and the following disclaimer in the documentation 127c88f3f6SAchin Gupta * and/or other materials provided with the distribution. 137c88f3f6SAchin Gupta * 147c88f3f6SAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 157c88f3f6SAchin Gupta * to endorse or promote products derived from this software without specific 167c88f3f6SAchin Gupta * prior written permission. 177c88f3f6SAchin Gupta * 187c88f3f6SAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 197c88f3f6SAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 207c88f3f6SAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 217c88f3f6SAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 227c88f3f6SAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 237c88f3f6SAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 247c88f3f6SAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 257c88f3f6SAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 267c88f3f6SAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 277c88f3f6SAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 287c88f3f6SAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 297c88f3f6SAchin Gupta */ 307c88f3f6SAchin Gupta 317c88f3f6SAchin Gupta #include <bl32.h> 327c88f3f6SAchin Gupta #include <tsp.h> 337c88f3f6SAchin Gupta #include <arch_helpers.h> 347c88f3f6SAchin Gupta #include <stdio.h> 357c88f3f6SAchin Gupta #include <platform.h> 367c88f3f6SAchin Gupta #include <debug.h> 377c88f3f6SAchin Gupta #include <spinlock.h> 387c88f3f6SAchin Gupta 397c88f3f6SAchin Gupta /******************************************************************************* 407c88f3f6SAchin Gupta * Lock to control access to the console 417c88f3f6SAchin Gupta ******************************************************************************/ 427c88f3f6SAchin Gupta spinlock_t console_lock; 437c88f3f6SAchin Gupta 447c88f3f6SAchin Gupta /******************************************************************************* 457c88f3f6SAchin Gupta * Per cpu data structure to populate parameters for an SMC in C code and use 467c88f3f6SAchin Gupta * a pointer to this structure in assembler code to populate x0-x7 477c88f3f6SAchin Gupta ******************************************************************************/ 487c88f3f6SAchin Gupta static tsp_args tsp_smc_args[PLATFORM_CORE_COUNT]; 497c88f3f6SAchin Gupta 507c88f3f6SAchin Gupta /******************************************************************************* 517c88f3f6SAchin Gupta * Per cpu data structure to keep track of TSP activity 527c88f3f6SAchin Gupta ******************************************************************************/ 537c88f3f6SAchin Gupta static work_statistics tsp_stats[PLATFORM_CORE_COUNT]; 547c88f3f6SAchin Gupta 557c88f3f6SAchin Gupta /******************************************************************************* 567c88f3f6SAchin Gupta * Single reference to the various entry points exported by the test secure 577c88f3f6SAchin Gupta * payload. A single copy should suffice for all cpus as they are not expected 587c88f3f6SAchin Gupta * to change. 597c88f3f6SAchin Gupta ******************************************************************************/ 607c88f3f6SAchin Gupta static const entry_info tsp_entry_info = { 617c88f3f6SAchin Gupta tsp_fast_smc_entry, 627c88f3f6SAchin Gupta tsp_cpu_on_entry, 637c88f3f6SAchin Gupta tsp_cpu_off_entry, 647c88f3f6SAchin Gupta tsp_cpu_resume_entry, 657c88f3f6SAchin Gupta tsp_cpu_suspend_entry, 667c88f3f6SAchin Gupta }; 677c88f3f6SAchin Gupta 687c88f3f6SAchin Gupta static tsp_args *set_smc_args(uint64_t arg0, 697c88f3f6SAchin Gupta uint64_t arg1, 707c88f3f6SAchin Gupta uint64_t arg2, 717c88f3f6SAchin Gupta uint64_t arg3, 727c88f3f6SAchin Gupta uint64_t arg4, 737c88f3f6SAchin Gupta uint64_t arg5, 747c88f3f6SAchin Gupta uint64_t arg6, 757c88f3f6SAchin Gupta uint64_t arg7) 767c88f3f6SAchin Gupta { 777c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 787c88f3f6SAchin Gupta uint32_t linear_id; 797c88f3f6SAchin Gupta tsp_args *pcpu_smc_args; 807c88f3f6SAchin Gupta 817c88f3f6SAchin Gupta /* 827c88f3f6SAchin Gupta * Return to Secure Monitor by raising an SMC. The results of the 837c88f3f6SAchin Gupta * service are passed as an arguments to the SMC 847c88f3f6SAchin Gupta */ 857c88f3f6SAchin Gupta linear_id = platform_get_core_pos(mpidr); 867c88f3f6SAchin Gupta pcpu_smc_args = &tsp_smc_args[linear_id]; 877c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); 887c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); 897c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); 907c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); 917c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); 927c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); 937c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); 947c88f3f6SAchin Gupta write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); 957c88f3f6SAchin Gupta 967c88f3f6SAchin Gupta return pcpu_smc_args; 977c88f3f6SAchin Gupta } 987c88f3f6SAchin Gupta 997c88f3f6SAchin Gupta /******************************************************************************* 1007c88f3f6SAchin Gupta * TSP main entry point where it gets the opportunity to initialize its secure 1017c88f3f6SAchin Gupta * state/applications. Once the state is initialized, it must return to the 1027c88f3f6SAchin Gupta * SPD with a pointer to the 'tsp_entry_info' structure. 1037c88f3f6SAchin Gupta ******************************************************************************/ 1047c88f3f6SAchin Gupta uint64_t tsp_main(void) 1057c88f3f6SAchin Gupta { 1067c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 1077c88f3f6SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 1087c88f3f6SAchin Gupta 1097c88f3f6SAchin Gupta #if DEBUG 1107c88f3f6SAchin Gupta meminfo *mem_layout = bl32_plat_sec_mem_layout(); 1117c88f3f6SAchin Gupta #endif 1127c88f3f6SAchin Gupta 1137c88f3f6SAchin Gupta /* Initialize the platform */ 1147c88f3f6SAchin Gupta bl32_platform_setup(); 1157c88f3f6SAchin Gupta 1167c88f3f6SAchin Gupta /* Initialize secure/applications state here */ 1177c88f3f6SAchin Gupta 1187c88f3f6SAchin Gupta /* Update this cpu's statistics */ 1197c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count++; 1207c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count++; 1217c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_on_count++; 1227c88f3f6SAchin Gupta 1237c88f3f6SAchin Gupta spin_lock(&console_lock); 124*fb052462SJon Medhurst printf("TSP %s\n\r", build_message); 1257c88f3f6SAchin Gupta INFO("Total memory base : 0x%x\n", mem_layout->total_base); 1267c88f3f6SAchin Gupta INFO("Total memory size : 0x%x bytes\n", mem_layout->total_size); 1277c88f3f6SAchin Gupta INFO("Free memory base : 0x%x\n", mem_layout->free_base); 1287c88f3f6SAchin Gupta INFO("Free memory size : 0x%x bytes\n", mem_layout->free_size); 1297c88f3f6SAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, 1307c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count, 1317c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count, 1327c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_on_count); 1337c88f3f6SAchin Gupta spin_unlock(&console_lock); 1347c88f3f6SAchin Gupta 1357c88f3f6SAchin Gupta /* 1367c88f3f6SAchin Gupta * TODO: There is a massive assumption that the SPD and SP can see each 1377c88f3f6SAchin Gupta * other's memory without issues so it is safe to pass pointers to 1387c88f3f6SAchin Gupta * internal memory. Replace this with a shared communication buffer. 1397c88f3f6SAchin Gupta */ 1407c88f3f6SAchin Gupta return (uint64_t) &tsp_entry_info; 1417c88f3f6SAchin Gupta } 1427c88f3f6SAchin Gupta 1437c88f3f6SAchin Gupta /******************************************************************************* 1447c88f3f6SAchin Gupta * This function performs any remaining book keeping in the test secure payload 1457c88f3f6SAchin Gupta * after this cpu's architectural state has been setup in response to an earlier 1467c88f3f6SAchin Gupta * psci cpu_on request. 1477c88f3f6SAchin Gupta ******************************************************************************/ 1487c88f3f6SAchin Gupta tsp_args *tsp_cpu_on_main(void) 1497c88f3f6SAchin Gupta { 1507c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 1517c88f3f6SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 1527c88f3f6SAchin Gupta 1537c88f3f6SAchin Gupta /* Update this cpu's statistics */ 1547c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count++; 1557c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count++; 1567c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_on_count++; 1577c88f3f6SAchin Gupta 1587c88f3f6SAchin Gupta spin_lock(&console_lock); 1597c88f3f6SAchin Gupta printf("SP: cpu 0x%x turned on\n\r", mpidr); 1607c88f3f6SAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, 1617c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count, 1627c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count, 1637c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_on_count); 1647c88f3f6SAchin Gupta spin_unlock(&console_lock); 1657c88f3f6SAchin Gupta 1667c88f3f6SAchin Gupta /* Indicate to the SPD that we have completed turned ourselves on */ 1677c88f3f6SAchin Gupta return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); 1687c88f3f6SAchin Gupta } 1697c88f3f6SAchin Gupta 1707c88f3f6SAchin Gupta /******************************************************************************* 1717c88f3f6SAchin Gupta * This function performs any remaining book keeping in the test secure payload 1727c88f3f6SAchin Gupta * before this cpu is turned off in response to a psci cpu_off request. 1737c88f3f6SAchin Gupta ******************************************************************************/ 1747c88f3f6SAchin Gupta tsp_args *tsp_cpu_off_main(uint64_t arg0, 1757c88f3f6SAchin Gupta uint64_t arg1, 1767c88f3f6SAchin Gupta uint64_t arg2, 1777c88f3f6SAchin Gupta uint64_t arg3, 1787c88f3f6SAchin Gupta uint64_t arg4, 1797c88f3f6SAchin Gupta uint64_t arg5, 1807c88f3f6SAchin Gupta uint64_t arg6, 1817c88f3f6SAchin Gupta uint64_t arg7) 1827c88f3f6SAchin Gupta { 1837c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 1847c88f3f6SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 1857c88f3f6SAchin Gupta 1867c88f3f6SAchin Gupta /* Update this cpu's statistics */ 1877c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count++; 1887c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count++; 1897c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_off_count++; 1907c88f3f6SAchin Gupta 1917c88f3f6SAchin Gupta spin_lock(&console_lock); 1927c88f3f6SAchin Gupta printf("SP: cpu 0x%x off request\n\r", mpidr); 1937c88f3f6SAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, 1947c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count, 1957c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count, 1967c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_off_count); 1977c88f3f6SAchin Gupta spin_unlock(&console_lock); 1987c88f3f6SAchin Gupta 1997c88f3f6SAchin Gupta 200607084eeSAchin Gupta /* Indicate to the SPD that we have completed this request */ 2017c88f3f6SAchin Gupta return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); 2027c88f3f6SAchin Gupta } 2037c88f3f6SAchin Gupta 2047c88f3f6SAchin Gupta /******************************************************************************* 2057c88f3f6SAchin Gupta * This function performs any book keeping in the test secure payload before 2067c88f3f6SAchin Gupta * this cpu's architectural state is saved in response to an earlier psci 2077c88f3f6SAchin Gupta * cpu_suspend request. 2087c88f3f6SAchin Gupta ******************************************************************************/ 2097c88f3f6SAchin Gupta tsp_args *tsp_cpu_suspend_main(uint64_t power_state, 2107c88f3f6SAchin Gupta uint64_t arg1, 2117c88f3f6SAchin Gupta uint64_t arg2, 2127c88f3f6SAchin Gupta uint64_t arg3, 2137c88f3f6SAchin Gupta uint64_t arg4, 2147c88f3f6SAchin Gupta uint64_t arg5, 2157c88f3f6SAchin Gupta uint64_t arg6, 2167c88f3f6SAchin Gupta uint64_t arg7) 2177c88f3f6SAchin Gupta { 2187c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 2197c88f3f6SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 2207c88f3f6SAchin Gupta 2217c88f3f6SAchin Gupta /* Update this cpu's statistics */ 2227c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count++; 2237c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count++; 2247c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_suspend_count++; 2257c88f3f6SAchin Gupta 2267c88f3f6SAchin Gupta spin_lock(&console_lock); 2277c88f3f6SAchin Gupta printf("SP: cpu 0x%x suspend request. power state: 0x%x\n\r", 2287c88f3f6SAchin Gupta mpidr, power_state); 2297c88f3f6SAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, 2307c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count, 2317c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count, 2327c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_suspend_count); 2337c88f3f6SAchin Gupta spin_unlock(&console_lock); 2347c88f3f6SAchin Gupta 235607084eeSAchin Gupta /* Indicate to the SPD that we have completed this request */ 2367c88f3f6SAchin Gupta return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); 2377c88f3f6SAchin Gupta } 2387c88f3f6SAchin Gupta 2397c88f3f6SAchin Gupta /******************************************************************************* 2407c88f3f6SAchin Gupta * This function performs any book keeping in the test secure payload after this 2417c88f3f6SAchin Gupta * cpu's architectural state has been restored after wakeup from an earlier psci 2427c88f3f6SAchin Gupta * cpu_suspend request. 2437c88f3f6SAchin Gupta ******************************************************************************/ 2447c88f3f6SAchin Gupta tsp_args *tsp_cpu_resume_main(uint64_t suspend_level, 2457c88f3f6SAchin Gupta uint64_t arg1, 2467c88f3f6SAchin Gupta uint64_t arg2, 2477c88f3f6SAchin Gupta uint64_t arg3, 2487c88f3f6SAchin Gupta uint64_t arg4, 2497c88f3f6SAchin Gupta uint64_t arg5, 2507c88f3f6SAchin Gupta uint64_t arg6, 2517c88f3f6SAchin Gupta uint64_t arg7) 2527c88f3f6SAchin Gupta { 2537c88f3f6SAchin Gupta uint64_t mpidr = read_mpidr(); 2547c88f3f6SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 2557c88f3f6SAchin Gupta 2567c88f3f6SAchin Gupta /* Update this cpu's statistics */ 2577c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count++; 2587c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count++; 2597c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_resume_count++; 2607c88f3f6SAchin Gupta 2617c88f3f6SAchin Gupta spin_lock(&console_lock); 2627c88f3f6SAchin Gupta printf("SP: cpu 0x%x resumed. suspend level %d \n\r", 2637c88f3f6SAchin Gupta mpidr, suspend_level); 2647c88f3f6SAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, 2657c88f3f6SAchin Gupta tsp_stats[linear_id].smc_count, 2667c88f3f6SAchin Gupta tsp_stats[linear_id].eret_count, 2677c88f3f6SAchin Gupta tsp_stats[linear_id].cpu_suspend_count); 2687c88f3f6SAchin Gupta spin_unlock(&console_lock); 2697c88f3f6SAchin Gupta 270607084eeSAchin Gupta /* Indicate to the SPD that we have completed this request */ 2717c88f3f6SAchin Gupta return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); 2727c88f3f6SAchin Gupta } 2737c88f3f6SAchin Gupta 2747c88f3f6SAchin Gupta /******************************************************************************* 2757c88f3f6SAchin Gupta * TSP fast smc handler. The secure monitor jumps to this function by 2767c88f3f6SAchin Gupta * doing the ERET after populating X0-X7 registers. The arguments are received 2777c88f3f6SAchin Gupta * in the function arguments in order. Once the service is rendered, this 2787c88f3f6SAchin Gupta * function returns to Secure Monitor by raising SMC 2797c88f3f6SAchin Gupta ******************************************************************************/ 2807c88f3f6SAchin Gupta tsp_args *tsp_fast_smc_handler(uint64_t func, 2817c88f3f6SAchin Gupta uint64_t arg1, 2827c88f3f6SAchin Gupta uint64_t arg2, 2837c88f3f6SAchin Gupta uint64_t arg3, 2847c88f3f6SAchin Gupta uint64_t arg4, 2857c88f3f6SAchin Gupta uint64_t arg5, 2867c88f3f6SAchin Gupta uint64_t arg6, 2877c88f3f6SAchin Gupta uint64_t arg7) 2887c88f3f6SAchin Gupta { 289916a2c1eSAchin Gupta uint64_t results[2]; 290916a2c1eSAchin Gupta uint64_t service_args[2]; 291916a2c1eSAchin Gupta uint64_t mpidr = read_mpidr(); 292916a2c1eSAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 2937c88f3f6SAchin Gupta 294916a2c1eSAchin Gupta /* Update this cpu's statistics */ 295916a2c1eSAchin Gupta tsp_stats[linear_id].smc_count++; 296916a2c1eSAchin Gupta tsp_stats[linear_id].eret_count++; 2977c88f3f6SAchin Gupta 298916a2c1eSAchin Gupta printf("SP: cpu 0x%x received fast smc 0x%x\n", read_mpidr(), func); 299916a2c1eSAchin Gupta INFO("cpu 0x%x: %d smcs, %d erets\n", mpidr, 300916a2c1eSAchin Gupta tsp_stats[linear_id].smc_count, 301916a2c1eSAchin Gupta tsp_stats[linear_id].eret_count); 302916a2c1eSAchin Gupta 303916a2c1eSAchin Gupta /* Render secure services and obtain results here */ 3047c88f3f6SAchin Gupta 3057c88f3f6SAchin Gupta results[0] = arg1; 3067c88f3f6SAchin Gupta results[1] = arg2; 3077c88f3f6SAchin Gupta 3087c88f3f6SAchin Gupta /* 3097c88f3f6SAchin Gupta * Request a service back from dispatcher/secure monitor. This call 3107c88f3f6SAchin Gupta * return and thereafter resume exectuion 3117c88f3f6SAchin Gupta */ 3127c88f3f6SAchin Gupta tsp_get_magic(service_args); 3137c88f3f6SAchin Gupta 3147c88f3f6SAchin Gupta /* Determine the function to perform based on the function ID */ 3157c88f3f6SAchin Gupta switch (func) { 3167c88f3f6SAchin Gupta case TSP_FID_ADD: 3177c88f3f6SAchin Gupta results[0] += service_args[0]; 3187c88f3f6SAchin Gupta results[1] += service_args[1]; 3197c88f3f6SAchin Gupta break; 3207c88f3f6SAchin Gupta case TSP_FID_SUB: 3217c88f3f6SAchin Gupta results[0] -= service_args[0]; 3227c88f3f6SAchin Gupta results[1] -= service_args[1]; 3237c88f3f6SAchin Gupta break; 3247c88f3f6SAchin Gupta case TSP_FID_MUL: 3257c88f3f6SAchin Gupta results[0] *= service_args[0]; 3267c88f3f6SAchin Gupta results[1] *= service_args[1]; 3277c88f3f6SAchin Gupta break; 3287c88f3f6SAchin Gupta case TSP_FID_DIV: 3297c88f3f6SAchin Gupta results[0] /= service_args[0] ? service_args[0] : 1; 3307c88f3f6SAchin Gupta results[1] /= service_args[1] ? service_args[1] : 1; 3317c88f3f6SAchin Gupta break; 3327c88f3f6SAchin Gupta default: 3337c88f3f6SAchin Gupta break; 3347c88f3f6SAchin Gupta } 3357c88f3f6SAchin Gupta 336916a2c1eSAchin Gupta return set_smc_args(func, 3377c88f3f6SAchin Gupta results[0], 3387c88f3f6SAchin Gupta results[1], 339916a2c1eSAchin Gupta 0, 0, 0, 0, 0); 3407c88f3f6SAchin Gupta } 3417c88f3f6SAchin Gupta 342