1 /* 2 * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <inttypes.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <bl32/tsp/tsp.h> 14 #include <common/debug.h> 15 #include <plat/common/platform.h> 16 17 #include "tsp_private.h" 18 19 /******************************************************************************* 20 * This function updates the TSP statistics for S-EL1 interrupts handled 21 * synchronously i.e the ones that have been handed over by the TSPD. It also 22 * keeps count of the number of times control was passed back to the TSPD 23 * after handling the interrupt. In the future it will be possible that the 24 * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to 25 * return execution. This statistic will be useful to distinguish between these 26 * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter 27 * contains the address of the instruction in normal world where this S-EL1 28 * interrupt was generated. 29 ******************************************************************************/ 30 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) 31 { 32 uint32_t linear_id = plat_my_core_pos(); 33 34 tsp_stats[linear_id].sync_sel1_intr_count++; 35 if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN) 36 tsp_stats[linear_id].sync_sel1_intr_ret_count++; 37 38 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n", 39 read_mpidr(), elr_el3); 40 VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests," 41 " %d sync s-el1 interrupt returns\n", 42 read_mpidr(), 43 tsp_stats[linear_id].sync_sel1_intr_count, 44 tsp_stats[linear_id].sync_sel1_intr_ret_count); 45 } 46 47 /****************************************************************************** 48 * This function is invoked when a non S-EL1 interrupt is received and causes 49 * the preemption of TSP. This function returns TSP_PREEMPTED and results 50 * in the control being handed over to EL3 for handling the interrupt. 51 *****************************************************************************/ 52 int32_t tsp_handle_preemption(void) 53 { 54 uint32_t linear_id = plat_my_core_pos(); 55 56 tsp_stats[linear_id].preempt_intr_count++; 57 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", 58 read_mpidr(), tsp_stats[linear_id].preempt_intr_count); 59 return TSP_PREEMPTED; 60 } 61 62 /******************************************************************************* 63 * TSP interrupt handler is called as a part of both synchronous and 64 * asynchronous handling of TSP interrupts. Currently the physical timer 65 * interrupt is the only S-EL1 interrupt that this handler expects. It returns 66 * 0 upon successfully handling the expected interrupt and all other 67 * interrupts are treated as normal world or EL3 interrupts. 68 ******************************************************************************/ 69 int32_t tsp_common_int_handler(void) 70 { 71 uint32_t linear_id = plat_my_core_pos(), id; 72 73 /* 74 * Get the highest priority pending interrupt id and see if it is the 75 * secure physical generic timer interrupt in which case, handle it. 76 * Otherwise throw this interrupt at the EL3 firmware. 77 * 78 * There is a small time window between reading the highest priority 79 * pending interrupt and acknowledging it during which another 80 * interrupt of higher priority could become the highest pending 81 * interrupt. This is not expected to happen currently for TSP. 82 */ 83 id = plat_ic_get_pending_interrupt_id(); 84 85 /* TSP can only handle the secure physical timer interrupt */ 86 if (id != TSP_IRQ_SEC_PHY_TIMER) { 87 #if SPMC_AT_EL3 88 /* 89 * With the EL3 FF-A SPMC we expect only Timer secure interrupt to fire in 90 * the TSP, so panic if any other interrupt does. 91 */ 92 ERROR("Unexpected interrupt id %u\n", id); 93 panic(); 94 #else 95 return tsp_handle_preemption(); 96 #endif 97 } 98 99 /* 100 * Acknowledge and handle the secure timer interrupt. Also sanity check 101 * if it has been preempted by another interrupt through an assertion. 102 */ 103 id = plat_ic_acknowledge_interrupt(); 104 assert(id == TSP_IRQ_SEC_PHY_TIMER); 105 tsp_generic_timer_handler(); 106 plat_ic_end_of_interrupt(id); 107 108 /* Update the statistics and print some messages */ 109 tsp_stats[linear_id].sel1_intr_count++; 110 VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n", 111 read_mpidr(), id); 112 VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n", 113 read_mpidr(), tsp_stats[linear_id].sel1_intr_count); 114 return 0; 115 } 116