1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <gic_v2.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <tsp.h> 38 #include "tsp_private.h" 39 40 /******************************************************************************* 41 * This function updates the TSP statistics for FIQs handled synchronously i.e 42 * the ones that have been handed over by the TSPD. It also keeps count of the 43 * number of times control was passed back to the TSPD after handling an FIQ. 44 * In the future it will be possible that the TSPD hands over an FIQ to the TSP 45 * but does not expect it to return execution. This statistic will be useful to 46 * distinguish between these two models of synchronous FIQ handling. 47 * The 'elr_el3' parameter contains the address of the instruction in normal 48 * world where this FIQ was generated. 49 ******************************************************************************/ 50 void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) 51 { 52 uint32_t linear_id = plat_my_core_pos(); 53 54 tsp_stats[linear_id].sync_fiq_count++; 55 if (type == TSP_HANDLE_FIQ_AND_RETURN) 56 tsp_stats[linear_id].sync_fiq_ret_count++; 57 58 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 59 spin_lock(&console_lock); 60 VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n", 61 read_mpidr(), elr_el3); 62 VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n", 63 read_mpidr(), 64 tsp_stats[linear_id].sync_fiq_count, 65 tsp_stats[linear_id].sync_fiq_ret_count); 66 spin_unlock(&console_lock); 67 #endif 68 } 69 70 /****************************************************************************** 71 * This function is invoked when a non S-EL1 interrupt is received and causes 72 * the preemption of TSP. This function returns TSP_PREEMPTED and results 73 * in the control being handed over to EL3 for handling the interrupt. 74 *****************************************************************************/ 75 int32_t tsp_handle_preemption(void) 76 { 77 uint32_t linear_id = plat_my_core_pos(); 78 79 tsp_stats[linear_id].preempt_intr_count++; 80 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 81 spin_lock(&console_lock); 82 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", 83 read_mpidr(), tsp_stats[linear_id].preempt_intr_count); 84 spin_unlock(&console_lock); 85 #endif 86 return TSP_PREEMPTED; 87 } 88 89 /******************************************************************************* 90 * TSP FIQ handler called as a part of both synchronous and asynchronous 91 * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 92 * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC 93 * architecture version in v2.0 and the secure physical timer interrupt is the 94 * only S-EL1 interrupt that it needs to handle. 95 ******************************************************************************/ 96 int32_t tsp_fiq_handler(void) 97 { 98 uint32_t linear_id = plat_my_core_pos(), id; 99 100 /* 101 * Get the highest priority pending interrupt id and see if it is the 102 * secure physical generic timer interrupt in which case, handle it. 103 * Otherwise throw this interrupt at the EL3 firmware. 104 * 105 * There is a small time window between reading the highest priority 106 * pending interrupt and acknowledging it during which another 107 * interrupt of higher priority could become the highest pending 108 * interrupt. This is not expected to happen currently for TSP. 109 */ 110 id = plat_ic_get_pending_interrupt_id(); 111 112 /* TSP can only handle the secure physical timer interrupt */ 113 if (id != TSP_IRQ_SEC_PHY_TIMER) 114 return tsp_handle_preemption(); 115 116 /* 117 * Acknowledge and handle the secure timer interrupt. Also sanity check 118 * if it has been preempted by another interrupt through an assertion. 119 */ 120 id = plat_ic_acknowledge_interrupt(); 121 assert(id == TSP_IRQ_SEC_PHY_TIMER); 122 tsp_generic_timer_handler(); 123 plat_ic_end_of_interrupt(id); 124 125 /* Update the statistics and print some messages */ 126 tsp_stats[linear_id].fiq_count++; 127 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 128 spin_lock(&console_lock); 129 VERBOSE("TSP: cpu 0x%lx handled fiq %d\n", 130 read_mpidr(), id); 131 VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n", 132 read_mpidr(), tsp_stats[linear_id].fiq_count); 133 spin_unlock(&console_lock); 134 #endif 135 return 0; 136 } 137