1*6cf89021SAchin Gupta /* 2*6cf89021SAchin Gupta * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3*6cf89021SAchin Gupta * 4*6cf89021SAchin Gupta * Redistribution and use in source and binary forms, with or without 5*6cf89021SAchin Gupta * modification, are permitted provided that the following conditions are met: 6*6cf89021SAchin Gupta * 7*6cf89021SAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*6cf89021SAchin Gupta * list of conditions and the following disclaimer. 9*6cf89021SAchin Gupta * 10*6cf89021SAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*6cf89021SAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*6cf89021SAchin Gupta * and/or other materials provided with the distribution. 13*6cf89021SAchin Gupta * 14*6cf89021SAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*6cf89021SAchin Gupta * to endorse or promote products derived from this software without specific 16*6cf89021SAchin Gupta * prior written permission. 17*6cf89021SAchin Gupta * 18*6cf89021SAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*6cf89021SAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*6cf89021SAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*6cf89021SAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*6cf89021SAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*6cf89021SAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*6cf89021SAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*6cf89021SAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*6cf89021SAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*6cf89021SAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*6cf89021SAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*6cf89021SAchin Gupta */ 30*6cf89021SAchin Gupta 31*6cf89021SAchin Gupta #include <arch_helpers.h> 32*6cf89021SAchin Gupta #include <assert.h> 33*6cf89021SAchin Gupta #include <debug.h> 34*6cf89021SAchin Gupta #include <gic_v2.h> 35*6cf89021SAchin Gupta #include <tsp.h> 36*6cf89021SAchin Gupta #include <platform.h> 37*6cf89021SAchin Gupta 38*6cf89021SAchin Gupta /******************************************************************************* 39*6cf89021SAchin Gupta * This function updates the TSP statistics for FIQs handled synchronously i.e 40*6cf89021SAchin Gupta * the ones that have been handed over by the TSPD. It also keeps count of the 41*6cf89021SAchin Gupta * number of times control was passed back to the TSPD after handling an FIQ. 42*6cf89021SAchin Gupta * In the future it will be possible that the TSPD hands over an FIQ to the TSP 43*6cf89021SAchin Gupta * but does not expect it to return execution. This statistic will be useful to 44*6cf89021SAchin Gupta * distinguish between these two models of synchronous FIQ handling. 45*6cf89021SAchin Gupta * The 'elr_el3' parameter contains the address of the instruction in normal 46*6cf89021SAchin Gupta * world where this FIQ was generated. 47*6cf89021SAchin Gupta ******************************************************************************/ 48*6cf89021SAchin Gupta void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) 49*6cf89021SAchin Gupta { 50*6cf89021SAchin Gupta uint64_t mpidr = read_mpidr(); 51*6cf89021SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr); 52*6cf89021SAchin Gupta 53*6cf89021SAchin Gupta tsp_stats[linear_id].sync_fiq_count++; 54*6cf89021SAchin Gupta if (type == TSP_HANDLE_FIQ_AND_RETURN) 55*6cf89021SAchin Gupta tsp_stats[linear_id].sync_fiq_ret_count++; 56*6cf89021SAchin Gupta 57*6cf89021SAchin Gupta spin_lock(&console_lock); 58*6cf89021SAchin Gupta printf("TSP: cpu 0x%x sync fiq request from 0x%llx \n\r", 59*6cf89021SAchin Gupta mpidr, elr_el3); 60*6cf89021SAchin Gupta INFO("cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n", 61*6cf89021SAchin Gupta mpidr, 62*6cf89021SAchin Gupta tsp_stats[linear_id].sync_fiq_count, 63*6cf89021SAchin Gupta tsp_stats[linear_id].sync_fiq_ret_count); 64*6cf89021SAchin Gupta spin_unlock(&console_lock); 65*6cf89021SAchin Gupta } 66*6cf89021SAchin Gupta 67*6cf89021SAchin Gupta /******************************************************************************* 68*6cf89021SAchin Gupta * TSP FIQ handler called as a part of both synchronous and asynchronous 69*6cf89021SAchin Gupta * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 70*6cf89021SAchin Gupta * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC 71*6cf89021SAchin Gupta * architecture version in v2.0 and the secure physical timer interrupt is the 72*6cf89021SAchin Gupta * only S-EL1 interrupt that it needs to handle. 73*6cf89021SAchin Gupta ******************************************************************************/ 74*6cf89021SAchin Gupta int32_t tsp_fiq_handler() 75*6cf89021SAchin Gupta { 76*6cf89021SAchin Gupta uint64_t mpidr = read_mpidr(); 77*6cf89021SAchin Gupta uint32_t linear_id = platform_get_core_pos(mpidr), id; 78*6cf89021SAchin Gupta 79*6cf89021SAchin Gupta /* 80*6cf89021SAchin Gupta * Get the highest priority pending interrupt id and see if it is the 81*6cf89021SAchin Gupta * secure physical generic timer interrupt in which case, handle it. 82*6cf89021SAchin Gupta * Otherwise throw this interrupt at the EL3 firmware. 83*6cf89021SAchin Gupta */ 84*6cf89021SAchin Gupta id = ic_get_pending_interrupt_id(); 85*6cf89021SAchin Gupta 86*6cf89021SAchin Gupta /* TSP can only handle the secure physical timer interrupt */ 87*6cf89021SAchin Gupta if (id != IRQ_SEC_PHY_TIMER) 88*6cf89021SAchin Gupta return TSP_EL3_FIQ; 89*6cf89021SAchin Gupta 90*6cf89021SAchin Gupta /* 91*6cf89021SAchin Gupta * Handle the interrupt. Also sanity check if it has been preempted by 92*6cf89021SAchin Gupta * another secure interrupt through an assertion. 93*6cf89021SAchin Gupta */ 94*6cf89021SAchin Gupta id = ic_acknowledge_interrupt(); 95*6cf89021SAchin Gupta assert(id == IRQ_SEC_PHY_TIMER); 96*6cf89021SAchin Gupta tsp_generic_timer_handler(); 97*6cf89021SAchin Gupta ic_end_of_interrupt(id); 98*6cf89021SAchin Gupta 99*6cf89021SAchin Gupta /* Update the statistics and print some messages */ 100*6cf89021SAchin Gupta tsp_stats[linear_id].fiq_count++; 101*6cf89021SAchin Gupta spin_lock(&console_lock); 102*6cf89021SAchin Gupta printf("TSP: cpu 0x%x handled fiq %d \n\r", 103*6cf89021SAchin Gupta mpidr, id); 104*6cf89021SAchin Gupta INFO("cpu 0x%x: %d fiq requests \n", 105*6cf89021SAchin Gupta mpidr, tsp_stats[linear_id].fiq_count); 106*6cf89021SAchin Gupta spin_unlock(&console_lock); 107*6cf89021SAchin Gupta 108*6cf89021SAchin Gupta return 0; 109*6cf89021SAchin Gupta } 110