1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(elf32-littlearm) 12OUTPUT_ARCH(arm) 13ENTRY(sp_min_vector_table) 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 17} 18 19 20SECTIONS 21{ 22 . = BL32_BASE; 23 ASSERT(. == ALIGN(PAGE_SIZE), 24 "BL32_BASE address is not aligned on a page boundary.") 25 26#if SEPARATE_CODE_AND_RODATA 27 .text . : { 28 __TEXT_START__ = .; 29 *entrypoint.o(.text*) 30 *(.text*) 31 *(.vectors) 32 . = ALIGN(PAGE_SIZE); 33 __TEXT_END__ = .; 34 } >RAM 35 36 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 37 .ARM.extab . : { 38 *(.ARM.extab* .gnu.linkonce.armextab.*) 39 } >RAM 40 41 .ARM.exidx . : { 42 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 43 } >RAM 44 45 .rodata . : { 46 __RODATA_START__ = .; 47 *(.rodata*) 48 49 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 50 . = ALIGN(4); 51 __RT_SVC_DESCS_START__ = .; 52 KEEP(*(rt_svc_descs)) 53 __RT_SVC_DESCS_END__ = .; 54 55 /* 56 * Ensure 4-byte alignment for cpu_ops so that its fields are also 57 * aligned. Also ensure cpu_ops inclusion. 58 */ 59 . = ALIGN(4); 60 __CPU_OPS_START__ = .; 61 KEEP(*(cpu_ops)) 62 __CPU_OPS_END__ = .; 63 64 /* Place pubsub sections for events */ 65 . = ALIGN(8); 66#include <lib/el3_runtime/pubsub_events.h> 67 68 . = ALIGN(PAGE_SIZE); 69 __RODATA_END__ = .; 70 } >RAM 71#else 72 ro . : { 73 __RO_START__ = .; 74 *entrypoint.o(.text*) 75 *(.text*) 76 *(.rodata*) 77 78 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 79 . = ALIGN(4); 80 __RT_SVC_DESCS_START__ = .; 81 KEEP(*(rt_svc_descs)) 82 __RT_SVC_DESCS_END__ = .; 83 84 /* 85 * Ensure 4-byte alignment for cpu_ops so that its fields are also 86 * aligned. Also ensure cpu_ops inclusion. 87 */ 88 . = ALIGN(4); 89 __CPU_OPS_START__ = .; 90 KEEP(*(cpu_ops)) 91 __CPU_OPS_END__ = .; 92 93 /* Place pubsub sections for events */ 94 . = ALIGN(8); 95#include <lib/el3_runtime/pubsub_events.h> 96 97 *(.vectors) 98 __RO_END_UNALIGNED__ = .; 99 100 /* 101 * Memory page(s) mapped to this section will be marked as 102 * read-only, executable. No RW data from the next section must 103 * creep in. Ensure the rest of the current memory block is unused. 104 */ 105 . = ALIGN(PAGE_SIZE); 106 __RO_END__ = .; 107 } >RAM 108#endif 109 110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 111 "cpu_ops not defined for this platform.") 112 /* 113 * Define a linker symbol to mark start of the RW memory area for this 114 * image. 115 */ 116 __RW_START__ = . ; 117 118 .data . : { 119 __DATA_START__ = .; 120 *(.data*) 121 __DATA_END__ = .; 122 } >RAM 123 124#ifdef BL32_PROGBITS_LIMIT 125 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 126#endif 127 128 stacks (NOLOAD) : { 129 __STACKS_START__ = .; 130 *(tzfw_normal_stacks) 131 __STACKS_END__ = .; 132 } >RAM 133 134 /* 135 * The .bss section gets initialised to 0 at runtime. 136 * Its base address should be 8-byte aligned for better performance of the 137 * zero-initialization code. 138 */ 139 .bss (NOLOAD) : ALIGN(8) { 140 __BSS_START__ = .; 141 *(.bss*) 142 *(COMMON) 143#if !USE_COHERENT_MEM 144 /* 145 * Bakery locks are stored in normal .bss memory 146 * 147 * Each lock's data is spread across multiple cache lines, one per CPU, 148 * but multiple locks can share the same cache line. 149 * The compiler will allocate enough memory for one CPU's bakery locks, 150 * the remaining cache lines are allocated by the linker script 151 */ 152 . = ALIGN(CACHE_WRITEBACK_GRANULE); 153 __BAKERY_LOCK_START__ = .; 154 __PERCPU_BAKERY_LOCK_START__ = .; 155 *(bakery_lock) 156 . = ALIGN(CACHE_WRITEBACK_GRANULE); 157 __PERCPU_BAKERY_LOCK_END__ = .; 158 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 159 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 160 __BAKERY_LOCK_END__ = .; 161#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 162 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 163 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 164#endif 165#endif 166 167#if ENABLE_PMF 168 /* 169 * Time-stamps are stored in normal .bss memory 170 * 171 * The compiler will allocate enough memory for one CPU's time-stamps, 172 * the remaining memory for other CPUs is allocated by the 173 * linker script 174 */ 175 . = ALIGN(CACHE_WRITEBACK_GRANULE); 176 __PMF_TIMESTAMP_START__ = .; 177 KEEP(*(pmf_timestamp_array)) 178 . = ALIGN(CACHE_WRITEBACK_GRANULE); 179 __PMF_PERCPU_TIMESTAMP_END__ = .; 180 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 181 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 182 __PMF_TIMESTAMP_END__ = .; 183#endif /* ENABLE_PMF */ 184 185 __BSS_END__ = .; 186 } >RAM 187 188 /* 189 * The xlat_table section is for full, aligned page tables (4K). 190 * Removing them from .bss avoids forcing 4K alignment on 191 * the .bss section. The tables are initialized to zero by the translation 192 * tables library. 193 */ 194 xlat_table (NOLOAD) : { 195 *(xlat_table) 196 } >RAM 197 198 __BSS_SIZE__ = SIZEOF(.bss); 199 200#if USE_COHERENT_MEM 201 /* 202 * The base address of the coherent memory section must be page-aligned (4K) 203 * to guarantee that the coherent data are stored on their own pages and 204 * are not mixed with normal data. This is required to set up the correct 205 * memory attributes for the coherent data page tables. 206 */ 207 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 208 __COHERENT_RAM_START__ = .; 209 /* 210 * Bakery locks are stored in coherent memory 211 * 212 * Each lock's data is contiguous and fully allocated by the compiler 213 */ 214 *(bakery_lock) 215 *(tzfw_coherent_mem) 216 __COHERENT_RAM_END_UNALIGNED__ = .; 217 /* 218 * Memory page(s) mapped to this section will be marked 219 * as device memory. No other unexpected data must creep in. 220 * Ensure the rest of the current memory page is unused. 221 */ 222 . = ALIGN(PAGE_SIZE); 223 __COHERENT_RAM_END__ = .; 224 } >RAM 225 226 __COHERENT_RAM_UNALIGNED_SIZE__ = 227 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 228#endif 229 230 /* 231 * Define a linker symbol to mark end of the RW memory area for this 232 * image. 233 */ 234 __RW_END__ = .; 235 236 __BL32_END__ = .; 237} 238