1/* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(elf32-littlearm) 11OUTPUT_ARCH(arm) 12ENTRY(sp_min_vector_table) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 16} 17 18#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 19# include <plat_sp_min.ld.S> 20#endif /* PLAT_SP_MIN_EXTRA_LD_SCRIPT */ 21 22SECTIONS { 23 RAM_REGION_START = ORIGIN(RAM); 24 RAM_REGION_LENGTH = LENGTH(RAM); 25 . = BL32_BASE; 26 27 ASSERT(. == ALIGN(PAGE_SIZE), 28 "BL32_BASE address is not aligned on a page boundary.") 29 30#if SEPARATE_CODE_AND_RODATA 31 .text . : { 32 __TEXT_START__ = .; 33 34 *entrypoint.o(.text*) 35 *(SORT_BY_ALIGNMENT(.text*)) 36 *(.vectors) 37 38 . = ALIGN(PAGE_SIZE); 39 40 __TEXT_END__ = .; 41 } >RAM 42 43 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */ 44 .ARM.extab . : { 45 *(.ARM.extab* .gnu.linkonce.armextab.*) 46 } >RAM 47 48 .ARM.exidx . : { 49 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 50 } >RAM 51 52 .rodata . : { 53 __RODATA_START__ = .; 54 *(SORT_BY_ALIGNMENT(.rodata*)) 55 56 RODATA_COMMON 57 58 . = ALIGN(8); 59 60# include <lib/el3_runtime/pubsub_events.h> 61 62 . = ALIGN(PAGE_SIZE); 63 64 __RODATA_END__ = .; 65 } >RAM 66#else /* SEPARATE_CODE_AND_RODATA */ 67 .ro . : { 68 __RO_START__ = .; 69 70 *entrypoint.o(.text*) 71 *(SORT_BY_ALIGNMENT(.text*)) 72 *(SORT_BY_ALIGNMENT(.rodata*)) 73 74 RODATA_COMMON 75 76 . = ALIGN(8); 77 78# include <lib/el3_runtime/pubsub_events.h> 79 80 *(.vectors) 81 82 __RO_END_UNALIGNED__ = .; 83 84 /* 85 * Memory page(s) mapped to this section will be marked as device 86 * memory. No other unexpected data must creep in. Ensure that the rest 87 * of the current memory page is unused. 88 */ 89 . = ALIGN(PAGE_SIZE); 90 91 __RO_END__ = .; 92 } >RAM 93#endif /* SEPARATE_CODE_AND_RODATA */ 94 95 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 96 "cpu_ops not defined for this platform.") 97 98 __RW_START__ = .; 99 100 DATA_SECTION >RAM 101 RELA_SECTION >RAM 102 103#ifdef BL32_PROGBITS_LIMIT 104 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 105#endif /* BL32_PROGBITS_LIMIT */ 106 107 STACK_SECTION >RAM 108 BSS_SECTION >RAM 109 XLAT_TABLE_SECTION >RAM 110 111 __BSS_SIZE__ = SIZEOF(.bss); 112 113#if USE_COHERENT_MEM 114 /* 115 * The base address of the coherent memory section must be page-aligned to 116 * guarantee that the coherent data are stored on their own pages and are 117 * not mixed with normal data. This is required to set up the correct 118 * memory attributes for the coherent data page tables. 119 */ 120 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 121 __COHERENT_RAM_START__ = .; 122 123 /* 124 * Bakery locks are stored in coherent memory. Each lock's data is 125 * contiguous and fully allocated by the compiler. 126 */ 127 *(.bakery_lock) 128 *(.tzfw_coherent_mem) 129 130 __COHERENT_RAM_END_UNALIGNED__ = .; 131 132 /* 133 * Memory page(s) mapped to this section will be marked as device 134 * memory. No other unexpected data must creep in. Ensure that the rest 135 * of the current memory page is unused. 136 */ 137 . = ALIGN(PAGE_SIZE); 138 139 __COHERENT_RAM_END__ = .; 140 } >RAM 141 142 __COHERENT_RAM_UNALIGNED_SIZE__ = 143 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 144#endif /* USE_COHERENT_MEM */ 145 146 __RW_END__ = .; 147 __BL32_END__ = .; 148 149 /DISCARD/ : { 150 *(.dynsym .dynstr .hash .gnu.hash) 151 } 152 153 ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") 154 RAM_REGION_END = .; 155} 156