1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(elf32-littlearm) 12OUTPUT_ARCH(arm) 13ENTRY(sp_min_vector_table) 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 17} 18 19#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 20#include <plat_sp_min.ld.S> 21#endif 22 23SECTIONS 24{ 25 . = BL32_BASE; 26 ASSERT(. == ALIGN(PAGE_SIZE), 27 "BL32_BASE address is not aligned on a page boundary.") 28 29#if SEPARATE_CODE_AND_RODATA 30 .text . : { 31 __TEXT_START__ = .; 32 *entrypoint.o(.text*) 33 *(.text*) 34 *(.vectors) 35 . = ALIGN(PAGE_SIZE); 36 __TEXT_END__ = .; 37 } >RAM 38 39 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 40 .ARM.extab . : { 41 *(.ARM.extab* .gnu.linkonce.armextab.*) 42 } >RAM 43 44 .ARM.exidx . : { 45 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 46 } >RAM 47 48 .rodata . : { 49 __RODATA_START__ = .; 50 *(.rodata*) 51 52 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 53 . = ALIGN(4); 54 __RT_SVC_DESCS_START__ = .; 55 KEEP(*(rt_svc_descs)) 56 __RT_SVC_DESCS_END__ = .; 57 58 /* 59 * Ensure 4-byte alignment for cpu_ops so that its fields are also 60 * aligned. Also ensure cpu_ops inclusion. 61 */ 62 . = ALIGN(4); 63 __CPU_OPS_START__ = .; 64 KEEP(*(cpu_ops)) 65 __CPU_OPS_END__ = .; 66 67 /* Place pubsub sections for events */ 68 . = ALIGN(8); 69#include <lib/el3_runtime/pubsub_events.h> 70 71 . = ALIGN(PAGE_SIZE); 72 __RODATA_END__ = .; 73 } >RAM 74#else 75 ro . : { 76 __RO_START__ = .; 77 *entrypoint.o(.text*) 78 *(.text*) 79 *(.rodata*) 80 81 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 82 . = ALIGN(4); 83 __RT_SVC_DESCS_START__ = .; 84 KEEP(*(rt_svc_descs)) 85 __RT_SVC_DESCS_END__ = .; 86 87 /* 88 * Ensure 4-byte alignment for cpu_ops so that its fields are also 89 * aligned. Also ensure cpu_ops inclusion. 90 */ 91 . = ALIGN(4); 92 __CPU_OPS_START__ = .; 93 KEEP(*(cpu_ops)) 94 __CPU_OPS_END__ = .; 95 96 /* Place pubsub sections for events */ 97 . = ALIGN(8); 98#include <lib/el3_runtime/pubsub_events.h> 99 100 *(.vectors) 101 __RO_END_UNALIGNED__ = .; 102 103 /* 104 * Memory page(s) mapped to this section will be marked as 105 * read-only, executable. No RW data from the next section must 106 * creep in. Ensure the rest of the current memory block is unused. 107 */ 108 . = ALIGN(PAGE_SIZE); 109 __RO_END__ = .; 110 } >RAM 111#endif 112 113 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 114 "cpu_ops not defined for this platform.") 115 /* 116 * Define a linker symbol to mark start of the RW memory area for this 117 * image. 118 */ 119 __RW_START__ = . ; 120 121 .data . : { 122 __DATA_START__ = .; 123 *(.data*) 124 __DATA_END__ = .; 125 } >RAM 126 127#ifdef BL32_PROGBITS_LIMIT 128 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 129#endif 130 131 stacks (NOLOAD) : { 132 __STACKS_START__ = .; 133 *(tzfw_normal_stacks) 134 __STACKS_END__ = .; 135 } >RAM 136 137 /* 138 * The .bss section gets initialised to 0 at runtime. 139 * Its base address should be 8-byte aligned for better performance of the 140 * zero-initialization code. 141 */ 142 .bss (NOLOAD) : ALIGN(8) { 143 __BSS_START__ = .; 144 *(.bss*) 145 *(COMMON) 146#if !USE_COHERENT_MEM 147 /* 148 * Bakery locks are stored in normal .bss memory 149 * 150 * Each lock's data is spread across multiple cache lines, one per CPU, 151 * but multiple locks can share the same cache line. 152 * The compiler will allocate enough memory for one CPU's bakery locks, 153 * the remaining cache lines are allocated by the linker script 154 */ 155 . = ALIGN(CACHE_WRITEBACK_GRANULE); 156 __BAKERY_LOCK_START__ = .; 157 __PERCPU_BAKERY_LOCK_START__ = .; 158 *(bakery_lock) 159 . = ALIGN(CACHE_WRITEBACK_GRANULE); 160 __PERCPU_BAKERY_LOCK_END__ = .; 161 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 162 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 163 __BAKERY_LOCK_END__ = .; 164#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 165 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 166 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 167#endif 168#endif 169 170#if ENABLE_PMF 171 /* 172 * Time-stamps are stored in normal .bss memory 173 * 174 * The compiler will allocate enough memory for one CPU's time-stamps, 175 * the remaining memory for other CPUs is allocated by the 176 * linker script 177 */ 178 . = ALIGN(CACHE_WRITEBACK_GRANULE); 179 __PMF_TIMESTAMP_START__ = .; 180 KEEP(*(pmf_timestamp_array)) 181 . = ALIGN(CACHE_WRITEBACK_GRANULE); 182 __PMF_PERCPU_TIMESTAMP_END__ = .; 183 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 184 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 185 __PMF_TIMESTAMP_END__ = .; 186#endif /* ENABLE_PMF */ 187 188 __BSS_END__ = .; 189 } >RAM 190 191 /* 192 * The xlat_table section is for full, aligned page tables (4K). 193 * Removing them from .bss avoids forcing 4K alignment on 194 * the .bss section. The tables are initialized to zero by the translation 195 * tables library. 196 */ 197 xlat_table (NOLOAD) : { 198 *(xlat_table) 199 } >RAM 200 201 __BSS_SIZE__ = SIZEOF(.bss); 202 203#if USE_COHERENT_MEM 204 /* 205 * The base address of the coherent memory section must be page-aligned (4K) 206 * to guarantee that the coherent data are stored on their own pages and 207 * are not mixed with normal data. This is required to set up the correct 208 * memory attributes for the coherent data page tables. 209 */ 210 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 211 __COHERENT_RAM_START__ = .; 212 /* 213 * Bakery locks are stored in coherent memory 214 * 215 * Each lock's data is contiguous and fully allocated by the compiler 216 */ 217 *(bakery_lock) 218 *(tzfw_coherent_mem) 219 __COHERENT_RAM_END_UNALIGNED__ = .; 220 /* 221 * Memory page(s) mapped to this section will be marked 222 * as device memory. No other unexpected data must creep in. 223 * Ensure the rest of the current memory page is unused. 224 */ 225 . = ALIGN(PAGE_SIZE); 226 __COHERENT_RAM_END__ = .; 227 } >RAM 228 229 __COHERENT_RAM_UNALIGNED_SIZE__ = 230 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 231#endif 232 233 /* 234 * Define a linker symbol to mark end of the RW memory area for this 235 * image. 236 */ 237 __RW_END__ = .; 238 239 __BL32_END__ = .; 240} 241