1/* 2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <common/bl_common.ld.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12OUTPUT_FORMAT(elf32-littlearm) 13OUTPUT_ARCH(arm) 14ENTRY(sp_min_vector_table) 15 16MEMORY { 17 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 18} 19 20#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 21#include <plat_sp_min.ld.S> 22#endif 23 24SECTIONS 25{ 26 . = BL32_BASE; 27 ASSERT(. == ALIGN(PAGE_SIZE), 28 "BL32_BASE address is not aligned on a page boundary.") 29 30#if SEPARATE_CODE_AND_RODATA 31 .text . : { 32 __TEXT_START__ = .; 33 *entrypoint.o(.text*) 34 *(.text*) 35 *(.vectors) 36 . = ALIGN(PAGE_SIZE); 37 __TEXT_END__ = .; 38 } >RAM 39 40 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 41 .ARM.extab . : { 42 *(.ARM.extab* .gnu.linkonce.armextab.*) 43 } >RAM 44 45 .ARM.exidx . : { 46 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 47 } >RAM 48 49 .rodata . : { 50 __RODATA_START__ = .; 51 *(.rodata*) 52 53 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 54 . = ALIGN(4); 55 __RT_SVC_DESCS_START__ = .; 56 KEEP(*(rt_svc_descs)) 57 __RT_SVC_DESCS_END__ = .; 58 59#if ENABLE_PMF 60 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 61 . = ALIGN(4); 62 __PMF_SVC_DESCS_START__ = .; 63 KEEP(*(pmf_svc_descs)) 64 __PMF_SVC_DESCS_END__ = .; 65#endif /* ENABLE_PMF */ 66 67 /* 68 * Ensure 4-byte alignment for cpu_ops so that its fields are also 69 * aligned. Also ensure cpu_ops inclusion. 70 */ 71 . = ALIGN(4); 72 __CPU_OPS_START__ = .; 73 KEEP(*(cpu_ops)) 74 __CPU_OPS_END__ = .; 75 76 /* Place pubsub sections for events */ 77 . = ALIGN(8); 78#include <lib/el3_runtime/pubsub_events.h> 79 80 . = ALIGN(PAGE_SIZE); 81 __RODATA_END__ = .; 82 } >RAM 83#else 84 ro . : { 85 __RO_START__ = .; 86 *entrypoint.o(.text*) 87 *(.text*) 88 *(.rodata*) 89 90 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 91 . = ALIGN(4); 92 __RT_SVC_DESCS_START__ = .; 93 KEEP(*(rt_svc_descs)) 94 __RT_SVC_DESCS_END__ = .; 95 96 /* 97 * Ensure 4-byte alignment for cpu_ops so that its fields are also 98 * aligned. Also ensure cpu_ops inclusion. 99 */ 100 . = ALIGN(4); 101 __CPU_OPS_START__ = .; 102 KEEP(*(cpu_ops)) 103 __CPU_OPS_END__ = .; 104 105 /* Place pubsub sections for events */ 106 . = ALIGN(8); 107#include <lib/el3_runtime/pubsub_events.h> 108 109 *(.vectors) 110 __RO_END_UNALIGNED__ = .; 111 112 /* 113 * Memory page(s) mapped to this section will be marked as 114 * read-only, executable. No RW data from the next section must 115 * creep in. Ensure the rest of the current memory block is unused. 116 */ 117 . = ALIGN(PAGE_SIZE); 118 __RO_END__ = .; 119 } >RAM 120#endif 121 122 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 123 "cpu_ops not defined for this platform.") 124 /* 125 * Define a linker symbol to mark start of the RW memory area for this 126 * image. 127 */ 128 __RW_START__ = . ; 129 130 .data . : { 131 __DATA_START__ = .; 132 *(.data*) 133 __DATA_END__ = .; 134 } >RAM 135 136#ifdef BL32_PROGBITS_LIMIT 137 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 138#endif 139 140 stacks (NOLOAD) : { 141 __STACKS_START__ = .; 142 *(tzfw_normal_stacks) 143 __STACKS_END__ = .; 144 } >RAM 145 146 /* 147 * The .bss section gets initialised to 0 at runtime. 148 * Its base address should be 8-byte aligned for better performance of the 149 * zero-initialization code. 150 */ 151 .bss (NOLOAD) : ALIGN(8) { 152 __BSS_START__ = .; 153 *(.bss*) 154 *(COMMON) 155#if !USE_COHERENT_MEM 156 /* 157 * Bakery locks are stored in normal .bss memory 158 * 159 * Each lock's data is spread across multiple cache lines, one per CPU, 160 * but multiple locks can share the same cache line. 161 * The compiler will allocate enough memory for one CPU's bakery locks, 162 * the remaining cache lines are allocated by the linker script 163 */ 164 . = ALIGN(CACHE_WRITEBACK_GRANULE); 165 __BAKERY_LOCK_START__ = .; 166 __PERCPU_BAKERY_LOCK_START__ = .; 167 *(bakery_lock) 168 . = ALIGN(CACHE_WRITEBACK_GRANULE); 169 __PERCPU_BAKERY_LOCK_END__ = .; 170 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 171 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 172 __BAKERY_LOCK_END__ = .; 173#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 174 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 175 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 176#endif 177#endif 178 179#if ENABLE_PMF 180 /* 181 * Time-stamps are stored in normal .bss memory 182 * 183 * The compiler will allocate enough memory for one CPU's time-stamps, 184 * the remaining memory for other CPUs is allocated by the 185 * linker script 186 */ 187 . = ALIGN(CACHE_WRITEBACK_GRANULE); 188 __PMF_TIMESTAMP_START__ = .; 189 KEEP(*(pmf_timestamp_array)) 190 . = ALIGN(CACHE_WRITEBACK_GRANULE); 191 __PMF_PERCPU_TIMESTAMP_END__ = .; 192 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 193 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 194 __PMF_TIMESTAMP_END__ = .; 195#endif /* ENABLE_PMF */ 196 197 __BSS_END__ = .; 198 } >RAM 199 200 XLAT_TABLE_SECTION >RAM 201 202 __BSS_SIZE__ = SIZEOF(.bss); 203 204#if USE_COHERENT_MEM 205 /* 206 * The base address of the coherent memory section must be page-aligned (4K) 207 * to guarantee that the coherent data are stored on their own pages and 208 * are not mixed with normal data. This is required to set up the correct 209 * memory attributes for the coherent data page tables. 210 */ 211 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 212 __COHERENT_RAM_START__ = .; 213 /* 214 * Bakery locks are stored in coherent memory 215 * 216 * Each lock's data is contiguous and fully allocated by the compiler 217 */ 218 *(bakery_lock) 219 *(tzfw_coherent_mem) 220 __COHERENT_RAM_END_UNALIGNED__ = .; 221 /* 222 * Memory page(s) mapped to this section will be marked 223 * as device memory. No other unexpected data must creep in. 224 * Ensure the rest of the current memory page is unused. 225 */ 226 . = ALIGN(PAGE_SIZE); 227 __COHERENT_RAM_END__ = .; 228 } >RAM 229 230 __COHERENT_RAM_UNALIGNED_SIZE__ = 231 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 232#endif 233 234 /* 235 * Define a linker symbol to mark end of the RW memory area for this 236 * image. 237 */ 238 __RW_END__ = .; 239 240 __BL32_END__ = .; 241} 242