xref: /rk3399_ARM-atf/bl32/sp_min/sp_min.ld.S (revision 6bb49c876c7593ed5f61c20ef3d989dcff8e8d8c) 
1/*
2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(elf32-littlearm)
11OUTPUT_ARCH(arm)
12ENTRY(sp_min_vector_table)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
16}
17
18#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT
19#   include <plat_sp_min.ld.S>
20#endif /* PLAT_SP_MIN_EXTRA_LD_SCRIPT */
21
22SECTIONS {
23    . = BL32_BASE;
24
25    ASSERT(. == ALIGN(PAGE_SIZE),
26        "BL32_BASE address is not aligned on a page boundary.")
27
28#if SEPARATE_CODE_AND_RODATA
29    .text . : {
30        __TEXT_START__ = .;
31
32        *entrypoint.o(.text*)
33        *(SORT_BY_ALIGNMENT(.text*))
34        *(.vectors)
35
36        . = ALIGN(PAGE_SIZE);
37
38        __TEXT_END__ = .;
39    } >RAM
40
41    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
42    .ARM.extab . : {
43        *(.ARM.extab* .gnu.linkonce.armextab.*)
44    } >RAM
45
46    .ARM.exidx . : {
47        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
48    } >RAM
49
50    .rodata . : {
51        __RODATA_START__ = .;
52        *(SORT_BY_ALIGNMENT(.rodata*))
53
54        RODATA_COMMON
55
56        . = ALIGN(8);
57
58#   include <lib/el3_runtime/pubsub_events.h>
59
60        . = ALIGN(PAGE_SIZE);
61
62        __RODATA_END__ = .;
63    } >RAM
64#else /* SEPARATE_CODE_AND_RODATA */
65    .ro . : {
66        __RO_START__ = .;
67
68        *entrypoint.o(.text*)
69        *(SORT_BY_ALIGNMENT(.text*))
70        *(SORT_BY_ALIGNMENT(.rodata*))
71
72        RODATA_COMMON
73
74        . = ALIGN(8);
75
76#   include <lib/el3_runtime/pubsub_events.h>
77
78        *(.vectors)
79
80        __RO_END_UNALIGNED__ = .;
81
82        /*
83         * Memory page(s) mapped to this section will be marked as device
84         * memory. No other unexpected data must creep in. Ensure that the rest
85         * of the current memory page is unused.
86         */
87        . = ALIGN(PAGE_SIZE);
88
89        __RO_END__ = .;
90    } >RAM
91#endif /* SEPARATE_CODE_AND_RODATA */
92
93    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
94        "cpu_ops not defined for this platform.")
95
96    __RW_START__ = .;
97
98    DATA_SECTION >RAM
99    RELA_SECTION >RAM
100
101#ifdef BL32_PROGBITS_LIMIT
102    ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
103#endif /* BL32_PROGBITS_LIMIT */
104
105    STACK_SECTION >RAM
106    BSS_SECTION >RAM
107    XLAT_TABLE_SECTION >RAM
108
109    __BSS_SIZE__ = SIZEOF(.bss);
110
111#if USE_COHERENT_MEM
112    /*
113     * The base address of the coherent memory section must be page-aligned to
114     * guarantee that the coherent data are stored on their own pages and are
115     * not mixed with normal data.  This is required to set up the correct
116     * memory attributes for the coherent data page tables.
117     */
118    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
119        __COHERENT_RAM_START__ = .;
120
121        /*
122         * Bakery locks are stored in coherent memory. Each lock's data is
123         * contiguous and fully allocated by the compiler.
124         */
125        *(.bakery_lock)
126        *(.tzfw_coherent_mem)
127
128        __COHERENT_RAM_END_UNALIGNED__ = .;
129
130        /*
131         * Memory page(s) mapped to this section will be marked as device
132         * memory. No other unexpected data must creep in. Ensure that the rest
133         * of the current memory page is unused.
134         */
135        . = ALIGN(PAGE_SIZE);
136
137        __COHERENT_RAM_END__ = .;
138    } >RAM
139
140    __COHERENT_RAM_UNALIGNED_SIZE__ =
141        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
142#endif /* USE_COHERENT_MEM */
143
144    __RW_END__ = .;
145    __BL32_END__ = .;
146
147    /DISCARD/ : {
148        *(.dynsym .dynstr .hash .gnu.hash)
149    }
150
151    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
152}
153