1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8#include <xlat_tables_defs.h> 9 10OUTPUT_FORMAT(elf32-littlearm) 11OUTPUT_ARCH(arm) 12ENTRY(sp_min_vector_table) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 16} 17 18 19SECTIONS 20{ 21 . = BL32_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL32_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *entrypoint.o(.text*) 29 *(.text*) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >RAM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >RAM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >RAM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(.rodata*) 47 48 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 49 . = ALIGN(4); 50 __RT_SVC_DESCS_START__ = .; 51 KEEP(*(rt_svc_descs)) 52 __RT_SVC_DESCS_END__ = .; 53 54 /* 55 * Ensure 4-byte alignment for cpu_ops so that its fields are also 56 * aligned. Also ensure cpu_ops inclusion. 57 */ 58 . = ALIGN(4); 59 __CPU_OPS_START__ = .; 60 KEEP(*(cpu_ops)) 61 __CPU_OPS_END__ = .; 62 63 /* Place pubsub sections for events */ 64 . = ALIGN(8); 65#include <pubsub_events.h> 66 67 . = ALIGN(PAGE_SIZE); 68 __RODATA_END__ = .; 69 } >RAM 70#else 71 ro . : { 72 __RO_START__ = .; 73 *entrypoint.o(.text*) 74 *(.text*) 75 *(.rodata*) 76 77 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 78 . = ALIGN(4); 79 __RT_SVC_DESCS_START__ = .; 80 KEEP(*(rt_svc_descs)) 81 __RT_SVC_DESCS_END__ = .; 82 83 /* 84 * Ensure 4-byte alignment for cpu_ops so that its fields are also 85 * aligned. Also ensure cpu_ops inclusion. 86 */ 87 . = ALIGN(4); 88 __CPU_OPS_START__ = .; 89 KEEP(*(cpu_ops)) 90 __CPU_OPS_END__ = .; 91 92 /* Place pubsub sections for events */ 93 . = ALIGN(8); 94#include <pubsub_events.h> 95 96 *(.vectors) 97 __RO_END_UNALIGNED__ = .; 98 99 /* 100 * Memory page(s) mapped to this section will be marked as 101 * read-only, executable. No RW data from the next section must 102 * creep in. Ensure the rest of the current memory block is unused. 103 */ 104 . = ALIGN(PAGE_SIZE); 105 __RO_END__ = .; 106 } >RAM 107#endif 108 109 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 110 "cpu_ops not defined for this platform.") 111 /* 112 * Define a linker symbol to mark start of the RW memory area for this 113 * image. 114 */ 115 __RW_START__ = . ; 116 117 .data . : { 118 __DATA_START__ = .; 119 *(.data*) 120 __DATA_END__ = .; 121 } >RAM 122 123#ifdef BL32_PROGBITS_LIMIT 124 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 125#endif 126 127 stacks (NOLOAD) : { 128 __STACKS_START__ = .; 129 *(tzfw_normal_stacks) 130 __STACKS_END__ = .; 131 } >RAM 132 133 /* 134 * The .bss section gets initialised to 0 at runtime. 135 * Its base address should be 8-byte aligned for better performance of the 136 * zero-initialization code. 137 */ 138 .bss (NOLOAD) : ALIGN(8) { 139 __BSS_START__ = .; 140 *(.bss*) 141 *(COMMON) 142#if !USE_COHERENT_MEM 143 /* 144 * Bakery locks are stored in normal .bss memory 145 * 146 * Each lock's data is spread across multiple cache lines, one per CPU, 147 * but multiple locks can share the same cache line. 148 * The compiler will allocate enough memory for one CPU's bakery locks, 149 * the remaining cache lines are allocated by the linker script 150 */ 151 . = ALIGN(CACHE_WRITEBACK_GRANULE); 152 __BAKERY_LOCK_START__ = .; 153 *(bakery_lock) 154 . = ALIGN(CACHE_WRITEBACK_GRANULE); 155 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 156 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 157 __BAKERY_LOCK_END__ = .; 158#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 159 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 160 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 161#endif 162#endif 163 164#if ENABLE_PMF 165 /* 166 * Time-stamps are stored in normal .bss memory 167 * 168 * The compiler will allocate enough memory for one CPU's time-stamps, 169 * the remaining memory for other CPU's is allocated by the 170 * linker script 171 */ 172 . = ALIGN(CACHE_WRITEBACK_GRANULE); 173 __PMF_TIMESTAMP_START__ = .; 174 KEEP(*(pmf_timestamp_array)) 175 . = ALIGN(CACHE_WRITEBACK_GRANULE); 176 __PMF_PERCPU_TIMESTAMP_END__ = .; 177 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 178 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 179 __PMF_TIMESTAMP_END__ = .; 180#endif /* ENABLE_PMF */ 181 182 __BSS_END__ = .; 183 } >RAM 184 185 /* 186 * The xlat_table section is for full, aligned page tables (4K). 187 * Removing them from .bss avoids forcing 4K alignment on 188 * the .bss section. The tables are initialized to zero by the translation 189 * tables library. 190 */ 191 xlat_table (NOLOAD) : { 192 *(xlat_table) 193 } >RAM 194 195 __BSS_SIZE__ = SIZEOF(.bss); 196 197#if USE_COHERENT_MEM 198 /* 199 * The base address of the coherent memory section must be page-aligned (4K) 200 * to guarantee that the coherent data are stored on their own pages and 201 * are not mixed with normal data. This is required to set up the correct 202 * memory attributes for the coherent data page tables. 203 */ 204 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 205 __COHERENT_RAM_START__ = .; 206 /* 207 * Bakery locks are stored in coherent memory 208 * 209 * Each lock's data is contiguous and fully allocated by the compiler 210 */ 211 *(bakery_lock) 212 *(tzfw_coherent_mem) 213 __COHERENT_RAM_END_UNALIGNED__ = .; 214 /* 215 * Memory page(s) mapped to this section will be marked 216 * as device memory. No other unexpected data must creep in. 217 * Ensure the rest of the current memory page is unused. 218 */ 219 . = ALIGN(PAGE_SIZE); 220 __COHERENT_RAM_END__ = .; 221 } >RAM 222 223 __COHERENT_RAM_UNALIGNED_SIZE__ = 224 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 225#endif 226 227 /* 228 * Define a linker symbol to mark end of the RW memory area for this 229 * image. 230 */ 231 __RW_END__ = .; 232 233 __BL32_END__ = .; 234} 235