1/* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9OUTPUT_FORMAT(elf32-littlearm) 10OUTPUT_ARCH(arm) 11ENTRY(sp_min_vector_table) 12 13MEMORY { 14 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 15} 16 17 18SECTIONS 19{ 20 . = BL32_BASE; 21 ASSERT(. == ALIGN(4096), 22 "BL32_BASE address is not aligned on a page boundary.") 23 24#if SEPARATE_CODE_AND_RODATA 25 .text . : { 26 __TEXT_START__ = .; 27 *entrypoint.o(.text*) 28 *(.text*) 29 *(.vectors) 30 . = NEXT(4096); 31 __TEXT_END__ = .; 32 } >RAM 33 34 .rodata . : { 35 __RODATA_START__ = .; 36 *(.rodata*) 37 38 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 39 . = ALIGN(4); 40 __RT_SVC_DESCS_START__ = .; 41 KEEP(*(rt_svc_descs)) 42 __RT_SVC_DESCS_END__ = .; 43 44 /* 45 * Ensure 4-byte alignment for cpu_ops so that its fields are also 46 * aligned. Also ensure cpu_ops inclusion. 47 */ 48 . = ALIGN(4); 49 __CPU_OPS_START__ = .; 50 KEEP(*(cpu_ops)) 51 __CPU_OPS_END__ = .; 52 53 /* Place pubsub sections for events */ 54 . = ALIGN(8); 55#include <pubsub_events.h> 56 57 . = NEXT(4096); 58 __RODATA_END__ = .; 59 } >RAM 60#else 61 ro . : { 62 __RO_START__ = .; 63 *entrypoint.o(.text*) 64 *(.text*) 65 *(.rodata*) 66 67 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 68 . = ALIGN(4); 69 __RT_SVC_DESCS_START__ = .; 70 KEEP(*(rt_svc_descs)) 71 __RT_SVC_DESCS_END__ = .; 72 73 /* 74 * Ensure 4-byte alignment for cpu_ops so that its fields are also 75 * aligned. Also ensure cpu_ops inclusion. 76 */ 77 . = ALIGN(4); 78 __CPU_OPS_START__ = .; 79 KEEP(*(cpu_ops)) 80 __CPU_OPS_END__ = .; 81 82 /* Place pubsub sections for events */ 83 . = ALIGN(8); 84#include <pubsub_events.h> 85 86 *(.vectors) 87 __RO_END_UNALIGNED__ = .; 88 89 /* 90 * Memory page(s) mapped to this section will be marked as 91 * read-only, executable. No RW data from the next section must 92 * creep in. Ensure the rest of the current memory block is unused. 93 */ 94 . = NEXT(4096); 95 __RO_END__ = .; 96 } >RAM 97#endif 98 99 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 100 "cpu_ops not defined for this platform.") 101 /* 102 * Define a linker symbol to mark start of the RW memory area for this 103 * image. 104 */ 105 __RW_START__ = . ; 106 107 .data . : { 108 __DATA_START__ = .; 109 *(.data*) 110 __DATA_END__ = .; 111 } >RAM 112 113#ifdef BL32_PROGBITS_LIMIT 114 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 115#endif 116 117 stacks (NOLOAD) : { 118 __STACKS_START__ = .; 119 *(tzfw_normal_stacks) 120 __STACKS_END__ = .; 121 } >RAM 122 123 /* 124 * The .bss section gets initialised to 0 at runtime. 125 * Its base address should be 8-byte aligned for better performance of the 126 * zero-initialization code. 127 */ 128 .bss (NOLOAD) : ALIGN(8) { 129 __BSS_START__ = .; 130 *(.bss*) 131 *(COMMON) 132#if !USE_COHERENT_MEM 133 /* 134 * Bakery locks are stored in normal .bss memory 135 * 136 * Each lock's data is spread across multiple cache lines, one per CPU, 137 * but multiple locks can share the same cache line. 138 * The compiler will allocate enough memory for one CPU's bakery locks, 139 * the remaining cache lines are allocated by the linker script 140 */ 141 . = ALIGN(CACHE_WRITEBACK_GRANULE); 142 __BAKERY_LOCK_START__ = .; 143 *(bakery_lock) 144 . = ALIGN(CACHE_WRITEBACK_GRANULE); 145 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 146 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 147 __BAKERY_LOCK_END__ = .; 148#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 149 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 150 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 151#endif 152#endif 153 154#if ENABLE_PMF 155 /* 156 * Time-stamps are stored in normal .bss memory 157 * 158 * The compiler will allocate enough memory for one CPU's time-stamps, 159 * the remaining memory for other CPU's is allocated by the 160 * linker script 161 */ 162 . = ALIGN(CACHE_WRITEBACK_GRANULE); 163 __PMF_TIMESTAMP_START__ = .; 164 KEEP(*(pmf_timestamp_array)) 165 . = ALIGN(CACHE_WRITEBACK_GRANULE); 166 __PMF_PERCPU_TIMESTAMP_END__ = .; 167 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 168 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 169 __PMF_TIMESTAMP_END__ = .; 170#endif /* ENABLE_PMF */ 171 172 __BSS_END__ = .; 173 } >RAM 174 175 /* 176 * The xlat_table section is for full, aligned page tables (4K). 177 * Removing them from .bss avoids forcing 4K alignment on 178 * the .bss section and eliminates the unecessary zero init 179 */ 180 xlat_table (NOLOAD) : { 181 *(xlat_table) 182 } >RAM 183 184 __BSS_SIZE__ = SIZEOF(.bss); 185 186#if USE_COHERENT_MEM 187 /* 188 * The base address of the coherent memory section must be page-aligned (4K) 189 * to guarantee that the coherent data are stored on their own pages and 190 * are not mixed with normal data. This is required to set up the correct 191 * memory attributes for the coherent data page tables. 192 */ 193 coherent_ram (NOLOAD) : ALIGN(4096) { 194 __COHERENT_RAM_START__ = .; 195 /* 196 * Bakery locks are stored in coherent memory 197 * 198 * Each lock's data is contiguous and fully allocated by the compiler 199 */ 200 *(bakery_lock) 201 *(tzfw_coherent_mem) 202 __COHERENT_RAM_END_UNALIGNED__ = .; 203 /* 204 * Memory page(s) mapped to this section will be marked 205 * as device memory. No other unexpected data must creep in. 206 * Ensure the rest of the current memory page is unused. 207 */ 208 . = NEXT(4096); 209 __COHERENT_RAM_END__ = .; 210 } >RAM 211 212 __COHERENT_RAM_UNALIGNED_SIZE__ = 213 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 214#endif 215 216 /* 217 * Define a linker symbol to mark end of the RW memory area for this 218 * image. 219 */ 220 __RW_END__ = .; 221 222 __BL32_END__ = .; 223} 224