1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(elf32-littlearm) 34OUTPUT_ARCH(arm) 35ENTRY(sp_min_vector_table) 36 37MEMORY { 38 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 39} 40 41 42SECTIONS 43{ 44 . = BL32_BASE; 45 ASSERT(. == ALIGN(4096), 46 "BL32_BASE address is not aligned on a page boundary.") 47 48#if SEPARATE_CODE_AND_RODATA 49 .text . : { 50 __TEXT_START__ = .; 51 *entrypoint.o(.text*) 52 *(.text*) 53 . = NEXT(4096); 54 __TEXT_END__ = .; 55 } >RAM 56 57 .rodata . : { 58 __RODATA_START__ = .; 59 *(.rodata*) 60 61 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 62 . = ALIGN(4); 63 __RT_SVC_DESCS_START__ = .; 64 KEEP(*(rt_svc_descs)) 65 __RT_SVC_DESCS_END__ = .; 66 67 /* 68 * Ensure 4-byte alignment for cpu_ops so that its fields are also 69 * aligned. Also ensure cpu_ops inclusion. 70 */ 71 . = ALIGN(4); 72 __CPU_OPS_START__ = .; 73 KEEP(*(cpu_ops)) 74 __CPU_OPS_END__ = .; 75 76 . = NEXT(4096); 77 __RODATA_END__ = .; 78 } >RAM 79#else 80 ro . : { 81 __RO_START__ = .; 82 *entrypoint.o(.text*) 83 *(.text*) 84 *(.rodata*) 85 86 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 87 . = ALIGN(4); 88 __RT_SVC_DESCS_START__ = .; 89 KEEP(*(rt_svc_descs)) 90 __RT_SVC_DESCS_END__ = .; 91 92 /* 93 * Ensure 4-byte alignment for cpu_ops so that its fields are also 94 * aligned. Also ensure cpu_ops inclusion. 95 */ 96 . = ALIGN(4); 97 __CPU_OPS_START__ = .; 98 KEEP(*(cpu_ops)) 99 __CPU_OPS_END__ = .; 100 101 __RO_END_UNALIGNED__ = .; 102 103 /* 104 * Memory page(s) mapped to this section will be marked as 105 * read-only, executable. No RW data from the next section must 106 * creep in. Ensure the rest of the current memory block is unused. 107 */ 108 . = NEXT(4096); 109 __RO_END__ = .; 110 } >RAM 111#endif 112 113 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 114 "cpu_ops not defined for this platform.") 115 /* 116 * Define a linker symbol to mark start of the RW memory area for this 117 * image. 118 */ 119 __RW_START__ = . ; 120 121 .data . : { 122 __DATA_START__ = .; 123 *(.data*) 124 __DATA_END__ = .; 125 } >RAM 126 127 stacks (NOLOAD) : { 128 __STACKS_START__ = .; 129 *(tzfw_normal_stacks) 130 __STACKS_END__ = .; 131 } >RAM 132 133 /* 134 * The .bss section gets initialised to 0 at runtime. 135 * Its base address must be 16-byte aligned. 136 */ 137 .bss (NOLOAD) : ALIGN(16) { 138 __BSS_START__ = .; 139 *(.bss*) 140 *(COMMON) 141#if !USE_COHERENT_MEM 142 /* 143 * Bakery locks are stored in normal .bss memory 144 * 145 * Each lock's data is spread across multiple cache lines, one per CPU, 146 * but multiple locks can share the same cache line. 147 * The compiler will allocate enough memory for one CPU's bakery locks, 148 * the remaining cache lines are allocated by the linker script 149 */ 150 . = ALIGN(CACHE_WRITEBACK_GRANULE); 151 __BAKERY_LOCK_START__ = .; 152 *(bakery_lock) 153 . = ALIGN(CACHE_WRITEBACK_GRANULE); 154 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 155 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 156 __BAKERY_LOCK_END__ = .; 157#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 158 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 159 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 160#endif 161#endif 162 163#if ENABLE_PMF 164 /* 165 * Time-stamps are stored in normal .bss memory 166 * 167 * The compiler will allocate enough memory for one CPU's time-stamps, 168 * the remaining memory for other CPU's is allocated by the 169 * linker script 170 */ 171 . = ALIGN(CACHE_WRITEBACK_GRANULE); 172 __PMF_TIMESTAMP_START__ = .; 173 KEEP(*(pmf_timestamp_array)) 174 . = ALIGN(CACHE_WRITEBACK_GRANULE); 175 __PMF_PERCPU_TIMESTAMP_END__ = .; 176 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 177 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 178 __PMF_TIMESTAMP_END__ = .; 179#endif /* ENABLE_PMF */ 180 181 __BSS_END__ = .; 182 } >RAM 183 184 /* 185 * The xlat_table section is for full, aligned page tables (4K). 186 * Removing them from .bss avoids forcing 4K alignment on 187 * the .bss section and eliminates the unecessary zero init 188 */ 189 xlat_table (NOLOAD) : { 190 *(xlat_table) 191 } >RAM 192 193 __BSS_SIZE__ = SIZEOF(.bss); 194 195#if USE_COHERENT_MEM 196 /* 197 * The base address of the coherent memory section must be page-aligned (4K) 198 * to guarantee that the coherent data are stored on their own pages and 199 * are not mixed with normal data. This is required to set up the correct 200 * memory attributes for the coherent data page tables. 201 */ 202 coherent_ram (NOLOAD) : ALIGN(4096) { 203 __COHERENT_RAM_START__ = .; 204 /* 205 * Bakery locks are stored in coherent memory 206 * 207 * Each lock's data is contiguous and fully allocated by the compiler 208 */ 209 *(bakery_lock) 210 *(tzfw_coherent_mem) 211 __COHERENT_RAM_END_UNALIGNED__ = .; 212 /* 213 * Memory page(s) mapped to this section will be marked 214 * as device memory. No other unexpected data must creep in. 215 * Ensure the rest of the current memory page is unused. 216 */ 217 . = NEXT(4096); 218 __COHERENT_RAM_END__ = .; 219 } >RAM 220 221 __COHERENT_RAM_UNALIGNED_SIZE__ = 222 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 223#endif 224 225 /* 226 * Define a linker symbol to mark end of the RW memory area for this 227 * image. 228 */ 229 __RW_END__ = .; 230 231 __BL32_END__ = .; 232} 233