1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8#include <xlat_tables_defs.h> 9 10OUTPUT_FORMAT(elf32-littlearm) 11OUTPUT_ARCH(arm) 12ENTRY(sp_min_vector_table) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 16} 17 18 19SECTIONS 20{ 21 . = BL32_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL32_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *entrypoint.o(.text*) 29 *(.text*) 30 *(.vectors) 31 . = NEXT(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >RAM 34 35 .rodata . : { 36 __RODATA_START__ = .; 37 *(.rodata*) 38 39 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 40 . = ALIGN(4); 41 __RT_SVC_DESCS_START__ = .; 42 KEEP(*(rt_svc_descs)) 43 __RT_SVC_DESCS_END__ = .; 44 45 /* 46 * Ensure 4-byte alignment for cpu_ops so that its fields are also 47 * aligned. Also ensure cpu_ops inclusion. 48 */ 49 . = ALIGN(4); 50 __CPU_OPS_START__ = .; 51 KEEP(*(cpu_ops)) 52 __CPU_OPS_END__ = .; 53 54 /* Place pubsub sections for events */ 55 . = ALIGN(8); 56#include <pubsub_events.h> 57 58 . = NEXT(PAGE_SIZE); 59 __RODATA_END__ = .; 60 } >RAM 61#else 62 ro . : { 63 __RO_START__ = .; 64 *entrypoint.o(.text*) 65 *(.text*) 66 *(.rodata*) 67 68 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 69 . = ALIGN(4); 70 __RT_SVC_DESCS_START__ = .; 71 KEEP(*(rt_svc_descs)) 72 __RT_SVC_DESCS_END__ = .; 73 74 /* 75 * Ensure 4-byte alignment for cpu_ops so that its fields are also 76 * aligned. Also ensure cpu_ops inclusion. 77 */ 78 . = ALIGN(4); 79 __CPU_OPS_START__ = .; 80 KEEP(*(cpu_ops)) 81 __CPU_OPS_END__ = .; 82 83 /* Place pubsub sections for events */ 84 . = ALIGN(8); 85#include <pubsub_events.h> 86 87 *(.vectors) 88 __RO_END_UNALIGNED__ = .; 89 90 /* 91 * Memory page(s) mapped to this section will be marked as 92 * read-only, executable. No RW data from the next section must 93 * creep in. Ensure the rest of the current memory block is unused. 94 */ 95 . = NEXT(PAGE_SIZE); 96 __RO_END__ = .; 97 } >RAM 98#endif 99 100 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 101 "cpu_ops not defined for this platform.") 102 /* 103 * Define a linker symbol to mark start of the RW memory area for this 104 * image. 105 */ 106 __RW_START__ = . ; 107 108 .data . : { 109 __DATA_START__ = .; 110 *(.data*) 111 __DATA_END__ = .; 112 } >RAM 113 114#ifdef BL32_PROGBITS_LIMIT 115 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 116#endif 117 118 stacks (NOLOAD) : { 119 __STACKS_START__ = .; 120 *(tzfw_normal_stacks) 121 __STACKS_END__ = .; 122 } >RAM 123 124 /* 125 * The .bss section gets initialised to 0 at runtime. 126 * Its base address should be 8-byte aligned for better performance of the 127 * zero-initialization code. 128 */ 129 .bss (NOLOAD) : ALIGN(8) { 130 __BSS_START__ = .; 131 *(.bss*) 132 *(COMMON) 133#if !USE_COHERENT_MEM 134 /* 135 * Bakery locks are stored in normal .bss memory 136 * 137 * Each lock's data is spread across multiple cache lines, one per CPU, 138 * but multiple locks can share the same cache line. 139 * The compiler will allocate enough memory for one CPU's bakery locks, 140 * the remaining cache lines are allocated by the linker script 141 */ 142 . = ALIGN(CACHE_WRITEBACK_GRANULE); 143 __BAKERY_LOCK_START__ = .; 144 *(bakery_lock) 145 . = ALIGN(CACHE_WRITEBACK_GRANULE); 146 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 147 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 148 __BAKERY_LOCK_END__ = .; 149#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 150 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 151 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 152#endif 153#endif 154 155#if ENABLE_PMF 156 /* 157 * Time-stamps are stored in normal .bss memory 158 * 159 * The compiler will allocate enough memory for one CPU's time-stamps, 160 * the remaining memory for other CPU's is allocated by the 161 * linker script 162 */ 163 . = ALIGN(CACHE_WRITEBACK_GRANULE); 164 __PMF_TIMESTAMP_START__ = .; 165 KEEP(*(pmf_timestamp_array)) 166 . = ALIGN(CACHE_WRITEBACK_GRANULE); 167 __PMF_PERCPU_TIMESTAMP_END__ = .; 168 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 169 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 170 __PMF_TIMESTAMP_END__ = .; 171#endif /* ENABLE_PMF */ 172 173 __BSS_END__ = .; 174 } >RAM 175 176 /* 177 * The xlat_table section is for full, aligned page tables (4K). 178 * Removing them from .bss avoids forcing 4K alignment on 179 * the .bss section. The tables are initialized to zero by the translation 180 * tables library. 181 */ 182 xlat_table (NOLOAD) : { 183 *(xlat_table) 184 } >RAM 185 186 __BSS_SIZE__ = SIZEOF(.bss); 187 188#if USE_COHERENT_MEM 189 /* 190 * The base address of the coherent memory section must be page-aligned (4K) 191 * to guarantee that the coherent data are stored on their own pages and 192 * are not mixed with normal data. This is required to set up the correct 193 * memory attributes for the coherent data page tables. 194 */ 195 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 196 __COHERENT_RAM_START__ = .; 197 /* 198 * Bakery locks are stored in coherent memory 199 * 200 * Each lock's data is contiguous and fully allocated by the compiler 201 */ 202 *(bakery_lock) 203 *(tzfw_coherent_mem) 204 __COHERENT_RAM_END_UNALIGNED__ = .; 205 /* 206 * Memory page(s) mapped to this section will be marked 207 * as device memory. No other unexpected data must creep in. 208 * Ensure the rest of the current memory page is unused. 209 */ 210 . = NEXT(PAGE_SIZE); 211 __COHERENT_RAM_END__ = .; 212 } >RAM 213 214 __COHERENT_RAM_UNALIGNED_SIZE__ = 215 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 216#endif 217 218 /* 219 * Define a linker symbol to mark end of the RW memory area for this 220 * image. 221 */ 222 __RW_END__ = .; 223 224 __BL32_END__ = .; 225} 226