1/* 2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(elf32-littlearm) 12OUTPUT_ARCH(arm) 13ENTRY(sp_min_vector_table) 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 17} 18 19#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 20#include <plat_sp_min.ld.S> 21#endif 22 23SECTIONS 24{ 25 . = BL32_BASE; 26 ASSERT(. == ALIGN(PAGE_SIZE), 27 "BL32_BASE address is not aligned on a page boundary.") 28 29#if SEPARATE_CODE_AND_RODATA 30 .text . : { 31 __TEXT_START__ = .; 32 *entrypoint.o(.text*) 33 *(.text*) 34 *(.vectors) 35 . = ALIGN(PAGE_SIZE); 36 __TEXT_END__ = .; 37 } >RAM 38 39 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 40 .ARM.extab . : { 41 *(.ARM.extab* .gnu.linkonce.armextab.*) 42 } >RAM 43 44 .ARM.exidx . : { 45 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 46 } >RAM 47 48 .rodata . : { 49 __RODATA_START__ = .; 50 *(.rodata*) 51 52 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 53 . = ALIGN(4); 54 __RT_SVC_DESCS_START__ = .; 55 KEEP(*(rt_svc_descs)) 56 __RT_SVC_DESCS_END__ = .; 57 58 . = ALIGN(8); 59 __FCONF_POPULATOR_START__ = .; 60 KEEP(*(.fconf_populator)) 61 __FCONF_POPULATOR_END__ = .; 62 63#if ENABLE_PMF 64 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 65 . = ALIGN(4); 66 __PMF_SVC_DESCS_START__ = .; 67 KEEP(*(pmf_svc_descs)) 68 __PMF_SVC_DESCS_END__ = .; 69#endif /* ENABLE_PMF */ 70 71 /* 72 * Ensure 4-byte alignment for cpu_ops so that its fields are also 73 * aligned. Also ensure cpu_ops inclusion. 74 */ 75 . = ALIGN(4); 76 __CPU_OPS_START__ = .; 77 KEEP(*(cpu_ops)) 78 __CPU_OPS_END__ = .; 79 80 /* Place pubsub sections for events */ 81 . = ALIGN(8); 82#include <lib/el3_runtime/pubsub_events.h> 83 84 . = ALIGN(PAGE_SIZE); 85 __RODATA_END__ = .; 86 } >RAM 87#else 88 ro . : { 89 __RO_START__ = .; 90 *entrypoint.o(.text*) 91 *(.text*) 92 *(.rodata*) 93 94 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 95 . = ALIGN(4); 96 __RT_SVC_DESCS_START__ = .; 97 KEEP(*(rt_svc_descs)) 98 __RT_SVC_DESCS_END__ = .; 99 100 . = ALIGN(8); 101 __FCONF_POPULATOR_START__ = .; 102 KEEP(*(.fconf_populator)) 103 __FCONF_POPULATOR_END__ = .; 104 105 /* 106 * Ensure 4-byte alignment for cpu_ops so that its fields are also 107 * aligned. Also ensure cpu_ops inclusion. 108 */ 109 . = ALIGN(4); 110 __CPU_OPS_START__ = .; 111 KEEP(*(cpu_ops)) 112 __CPU_OPS_END__ = .; 113 114 /* Place pubsub sections for events */ 115 . = ALIGN(8); 116#include <lib/el3_runtime/pubsub_events.h> 117 118 *(.vectors) 119 __RO_END_UNALIGNED__ = .; 120 121 /* 122 * Memory page(s) mapped to this section will be marked as 123 * read-only, executable. No RW data from the next section must 124 * creep in. Ensure the rest of the current memory block is unused. 125 */ 126 . = ALIGN(PAGE_SIZE); 127 __RO_END__ = .; 128 } >RAM 129#endif 130 131 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 132 "cpu_ops not defined for this platform.") 133 /* 134 * Define a linker symbol to mark start of the RW memory area for this 135 * image. 136 */ 137 __RW_START__ = . ; 138 139 .data . : { 140 __DATA_START__ = .; 141 *(.data*) 142 __DATA_END__ = .; 143 } >RAM 144 145#ifdef BL32_PROGBITS_LIMIT 146 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 147#endif 148 149 stacks (NOLOAD) : { 150 __STACKS_START__ = .; 151 *(tzfw_normal_stacks) 152 __STACKS_END__ = .; 153 } >RAM 154 155 /* 156 * The .bss section gets initialised to 0 at runtime. 157 * Its base address should be 8-byte aligned for better performance of the 158 * zero-initialization code. 159 */ 160 .bss (NOLOAD) : ALIGN(8) { 161 __BSS_START__ = .; 162 *(.bss*) 163 *(COMMON) 164#if !USE_COHERENT_MEM 165 /* 166 * Bakery locks are stored in normal .bss memory 167 * 168 * Each lock's data is spread across multiple cache lines, one per CPU, 169 * but multiple locks can share the same cache line. 170 * The compiler will allocate enough memory for one CPU's bakery locks, 171 * the remaining cache lines are allocated by the linker script 172 */ 173 . = ALIGN(CACHE_WRITEBACK_GRANULE); 174 __BAKERY_LOCK_START__ = .; 175 __PERCPU_BAKERY_LOCK_START__ = .; 176 *(bakery_lock) 177 . = ALIGN(CACHE_WRITEBACK_GRANULE); 178 __PERCPU_BAKERY_LOCK_END__ = .; 179 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 180 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 181 __BAKERY_LOCK_END__ = .; 182#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 183 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 184 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 185#endif 186#endif 187 188#if ENABLE_PMF 189 /* 190 * Time-stamps are stored in normal .bss memory 191 * 192 * The compiler will allocate enough memory for one CPU's time-stamps, 193 * the remaining memory for other CPUs is allocated by the 194 * linker script 195 */ 196 . = ALIGN(CACHE_WRITEBACK_GRANULE); 197 __PMF_TIMESTAMP_START__ = .; 198 KEEP(*(pmf_timestamp_array)) 199 . = ALIGN(CACHE_WRITEBACK_GRANULE); 200 __PMF_PERCPU_TIMESTAMP_END__ = .; 201 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 202 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 203 __PMF_TIMESTAMP_END__ = .; 204#endif /* ENABLE_PMF */ 205 206 __BSS_END__ = .; 207 } >RAM 208 209 /* 210 * The xlat_table section is for full, aligned page tables (4K). 211 * Removing them from .bss avoids forcing 4K alignment on 212 * the .bss section. The tables are initialized to zero by the translation 213 * tables library. 214 */ 215 xlat_table (NOLOAD) : { 216 *(xlat_table) 217 } >RAM 218 219 __BSS_SIZE__ = SIZEOF(.bss); 220 221#if USE_COHERENT_MEM 222 /* 223 * The base address of the coherent memory section must be page-aligned (4K) 224 * to guarantee that the coherent data are stored on their own pages and 225 * are not mixed with normal data. This is required to set up the correct 226 * memory attributes for the coherent data page tables. 227 */ 228 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 229 __COHERENT_RAM_START__ = .; 230 /* 231 * Bakery locks are stored in coherent memory 232 * 233 * Each lock's data is contiguous and fully allocated by the compiler 234 */ 235 *(bakery_lock) 236 *(tzfw_coherent_mem) 237 __COHERENT_RAM_END_UNALIGNED__ = .; 238 /* 239 * Memory page(s) mapped to this section will be marked 240 * as device memory. No other unexpected data must creep in. 241 * Ensure the rest of the current memory page is unused. 242 */ 243 . = ALIGN(PAGE_SIZE); 244 __COHERENT_RAM_END__ = .; 245 } >RAM 246 247 __COHERENT_RAM_UNALIGNED_SIZE__ = 248 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 249#endif 250 251 /* 252 * Define a linker symbol to mark end of the RW memory area for this 253 * image. 254 */ 255 __RW_END__ = .; 256 257 __BL32_END__ = .; 258} 259