xref: /rk3399_ARM-atf/bl31/bl31_main.c (revision f426fc0519103defb3dcf4a9d86d985d48204424)
1 /*
2  * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <arch.h>
32 #include <arch_helpers.h>
33 #include <assert.h>
34 #include <bl_common.h>
35 #include <bl31.h>
36 #include <context_mgmt.h>
37 #include <debug.h>
38 #include <platform.h>
39 #include <runtime_svc.h>
40 #include <string.h>
41 
42 /*******************************************************************************
43  * This function pointer is used to initialise the BL32 image. It's initialized
44  * by SPD calling bl31_register_bl32_init after setting up all things necessary
45  * for SP execution. In cases where both SPD and SP are absent, or when SPD
46  * finds it impossible to execute SP, this pointer is left as NULL
47  ******************************************************************************/
48 static int32_t (*bl32_init)(void);
49 
50 /*******************************************************************************
51  * Variable to indicate whether next image to execute after BL31 is BL33
52  * (non-secure & default) or BL32 (secure).
53  ******************************************************************************/
54 static uint32_t next_image_type = NON_SECURE;
55 
56 /*******************************************************************************
57  * Simple function to initialise all BL31 helper libraries.
58  ******************************************************************************/
59 void bl31_lib_init(void)
60 {
61 	/* Setup the arguments for PSCI Library */
62 	DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, bl31_warm_entrypoint);
63 
64 	cm_init();
65 
66 	/*
67 	 * Initialize the PSCI library here. This also does EL3 architectural
68 	 * setup.
69 	 */
70 	psci_setup(&psci_args);
71 }
72 
73 /*******************************************************************************
74  * BL31 is responsible for setting up the runtime services for the primary cpu
75  * before passing control to the bootloader or an Operating System. This
76  * function calls runtime_svc_init() which initializes all registered runtime
77  * services. The run time services would setup enough context for the core to
78  * swtich to the next exception level. When this function returns, the core will
79  * switch to the programmed exception level via. an ERET.
80  ******************************************************************************/
81 void bl31_main(void)
82 {
83 	NOTICE("BL31: %s\n", version_string);
84 	NOTICE("BL31: %s\n", build_message);
85 
86 	/* Perform platform setup in BL31 */
87 	bl31_platform_setup();
88 
89 	/* Initialise helper libraries */
90 	bl31_lib_init();
91 
92 	/* Initialize the runtime services e.g. psci */
93 	INFO("BL31: Initializing runtime services\n");
94 	runtime_svc_init();
95 
96 	/*
97 	 * All the cold boot actions on the primary cpu are done. We now need to
98 	 * decide which is the next image (BL32 or BL33) and how to execute it.
99 	 * If the SPD runtime service is present, it would want to pass control
100 	 * to BL32 first in S-EL1. In that case, SPD would have registered a
101 	 * function to intialize bl32 where it takes responsibility of entering
102 	 * S-EL1 and returning control back to bl31_main. Once this is done we
103 	 * can prepare entry into BL33 as normal.
104 	 */
105 
106 	/*
107 	 * If SPD had registerd an init hook, invoke it.
108 	 */
109 	if (bl32_init) {
110 		INFO("BL31: Initializing BL32\n");
111 		(*bl32_init)();
112 	}
113 	/*
114 	 * We are ready to enter the next EL. Prepare entry into the image
115 	 * corresponding to the desired security state after the next ERET.
116 	 */
117 	bl31_prepare_next_image_entry();
118 
119 	/*
120 	 * Perform any platform specific runtime setup prior to cold boot exit
121 	 * from BL31
122 	 */
123 	bl31_plat_runtime_setup();
124 }
125 
126 /*******************************************************************************
127  * Accessor functions to help runtime services decide which image should be
128  * executed after BL31. This is BL33 or the non-secure bootloader image by
129  * default but the Secure payload dispatcher could override this by requesting
130  * an entry into BL32 (Secure payload) first. If it does so then it should use
131  * the same API to program an entry into BL33 once BL32 initialisation is
132  * complete.
133  ******************************************************************************/
134 void bl31_set_next_image_type(uint32_t security_state)
135 {
136 	assert(sec_state_is_valid(security_state));
137 	next_image_type = security_state;
138 }
139 
140 uint32_t bl31_get_next_image_type(void)
141 {
142 	return next_image_type;
143 }
144 
145 /*******************************************************************************
146  * This function programs EL3 registers and performs other setup to enable entry
147  * into the next image after BL31 at the next ERET.
148  ******************************************************************************/
149 void bl31_prepare_next_image_entry(void)
150 {
151 	entry_point_info_t *next_image_info;
152 	uint32_t image_type;
153 
154 #if CTX_INCLUDE_AARCH32_REGS
155 	/*
156 	 * Ensure that the build flag to save AArch32 system registers in CPU
157 	 * context is not set for AArch64-only platforms.
158 	 */
159 	if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
160 			& ID_AA64PFR0_ELX_MASK) == 0x1) {
161 		ERROR("EL1 supports AArch64-only. Please set build flag "
162 				"CTX_INCLUDE_AARCH32_REGS = 0");
163 		panic();
164 	}
165 #endif
166 
167 	/* Determine which image to execute next */
168 	image_type = bl31_get_next_image_type();
169 
170 	/* Program EL3 registers to enable entry into the next EL */
171 	next_image_info = bl31_plat_get_next_image_ep_info(image_type);
172 	assert(next_image_info);
173 	assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
174 
175 	INFO("BL31: Preparing for EL3 exit to %s world\n",
176 		(image_type == SECURE) ? "secure" : "normal");
177 	print_entry_point_info(next_image_info);
178 	cm_init_my_context(next_image_info);
179 	cm_prepare_el3_exit(image_type);
180 }
181 
182 /*******************************************************************************
183  * This function initializes the pointer to BL32 init function. This is expected
184  * to be called by the SPD after it finishes all its initialization
185  ******************************************************************************/
186 void bl31_register_bl32_init(int32_t (*func)(void))
187 {
188 	bl32_init = func;
189 }
190