xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision f43e09a12e4f4f32185d3e2accceb65895d1f16b) 
1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL2_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL2_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29
30#if ENABLE_RME
31        *bl2_rme_entrypoint.o(.text*)
32#else /* ENABLE_RME */
33        *bl2_entrypoint.o(.text*)
34#endif /* ENABLE_RME */
35
36        *(SORT_BY_ALIGNMENT(.text*))
37        *(.vectors)
38
39        . = ALIGN(PAGE_SIZE);
40
41        __TEXT_END__ = .;
42    } >RAM
43
44    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
45    .ARM.extab . : {
46        *(.ARM.extab* .gnu.linkonce.armextab.*)
47    } >RAM
48
49    .ARM.exidx . : {
50        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
51    } >RAM
52
53    .rodata . : {
54        __RODATA_START__ = .;
55
56        *(SORT_BY_ALIGNMENT(.rodata*))
57
58        RODATA_COMMON
59
60        . = ALIGN(PAGE_SIZE);
61
62        __RODATA_END__ = .;
63    } >RAM
64#else /* SEPARATE_CODE_AND_RODATA */
65    .ro . : {
66        __RO_START__ = .;
67
68        *bl2_entrypoint.o(.text*)
69        *(SORT_BY_ALIGNMENT(.text*))
70        *(SORT_BY_ALIGNMENT(.rodata*))
71
72        RODATA_COMMON
73
74        *(.vectors)
75
76        __RO_END_UNALIGNED__ = .;
77
78        /*
79         * Memory page(s) mapped to this section will be marked as read-only,
80         * executable. No RW data from the next section must creep in. Ensure
81         * that the rest of the current memory page is unused.
82         */
83        . = ALIGN(PAGE_SIZE);
84
85        __RO_END__ = .;
86    } >RAM
87#endif /* SEPARATE_CODE_AND_RODATA */
88
89    __RW_START__ = .;
90
91    DATA_SECTION >RAM
92    STACK_SECTION >RAM
93    BSS_SECTION >RAM
94    XLAT_TABLE_SECTION >RAM
95
96#if USE_COHERENT_MEM
97    /*
98     * The base address of the coherent memory section must be page-aligned to
99     * guarantee that the coherent data are stored on their own pages and are
100     * not mixed with normal data.  This is required to set up the correct
101     * memory attributes for the coherent data page tables.
102     */
103    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
104        __COHERENT_RAM_START__ = .;
105        *(.tzfw_coherent_mem)
106        __COHERENT_RAM_END_UNALIGNED__ = .;
107
108        /*
109         * Memory page(s) mapped to this section will be marked as device
110         * memory. No other unexpected data must creep in. Ensure the rest of
111         * the current memory page is unused.
112         */
113        . = ALIGN(PAGE_SIZE);
114
115        __COHERENT_RAM_END__ = .;
116    } >RAM
117#endif /* USE_COHERENT_MEM */
118
119    __RW_END__ = .;
120    __BL2_END__ = .;
121    RAM_REGION_END = .;
122
123    __BSS_SIZE__ = SIZEOF(.bss);
124
125#if USE_COHERENT_MEM
126    __COHERENT_RAM_UNALIGNED_SIZE__ =
127        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
128#endif /* USE_COHERENT_MEM */
129
130    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
131}
132