xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision e83b0cadc67882c1ba7f430d16dab80c9b3a0228) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36MEMORY {
37    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
38}
39
40
41SECTIONS
42{
43    . = BL2_BASE;
44    ASSERT(. == ALIGN(4096),
45           "BL2_BASE address is not aligned on a page boundary.")
46
47    ro . : {
48        __RO_START__ = .;
49        *bl2_entrypoint.o(.text)
50        *(.text)
51        *(.rodata*)
52        __RO_END_UNALIGNED__ = .;
53        /*
54         * Memory page(s) mapped to this section will be marked as
55         * read-only, executable.  No RW data from the next section must
56         * creep in.  Ensure the rest of the current memory page is unused.
57         */
58        . = NEXT(4096);
59        __RO_END__ = .;
60    } >RAM
61
62    .data . : {
63        __DATA_START__ = .;
64        *(.data)
65        __DATA_END__ = .;
66    } >RAM
67
68    stacks (NOLOAD) : {
69        __STACKS_START__ = .;
70        *(tzfw_normal_stacks)
71        __STACKS_END__ = .;
72    } >RAM
73
74    /*
75     * The .bss section gets initialised to 0 at runtime.
76     * Its base address must be 16-byte aligned.
77     */
78    .bss : ALIGN(16) {
79        __BSS_START__ = .;
80        *(SORT_BY_ALIGNMENT(.bss))
81        *(COMMON)
82        __BSS_END__ = .;
83    } >RAM
84
85    /*
86     * The base address of the coherent memory section must be page-aligned (4K)
87     * to guarantee that the coherent data are stored on their own pages and
88     * are not mixed with normal data.  This is required to set up the correct
89     * memory attributes for the coherent data page tables.
90     */
91    coherent_ram (NOLOAD) : ALIGN(4096) {
92        __COHERENT_RAM_START__ = .;
93        *(tzfw_coherent_mem)
94        __COHERENT_RAM_END_UNALIGNED__ = .;
95        /*
96         * Memory page(s) mapped to this section will be marked
97         * as device memory.  No other unexpected data must creep in.
98         * Ensure the rest of the current memory page is unused.
99         */
100        . = NEXT(4096);
101        __COHERENT_RAM_END__ = .;
102    } >RAM
103
104    __BL2_END__ = .;
105
106    __BSS_SIZE__ = SIZEOF(.bss);
107    __COHERENT_RAM_UNALIGNED_SIZE__ =
108        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
109}
110