xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision cd529320988a559c3408292f09e443233d2157c3) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36MEMORY {
37    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
38}
39
40
41SECTIONS
42{
43    . = BL2_BASE;
44    ASSERT(. == ALIGN(4096),
45           "BL2_BASE address is not aligned on a page boundary.")
46
47    ro . : {
48        __RO_START__ = .;
49        *bl2_entrypoint.o(.text)
50        *(.text)
51        *(.rodata*)
52        *(.vectors)
53        __RO_END_UNALIGNED__ = .;
54        /*
55         * Memory page(s) mapped to this section will be marked as
56         * read-only, executable.  No RW data from the next section must
57         * creep in.  Ensure the rest of the current memory page is unused.
58         */
59        . = NEXT(4096);
60        __RO_END__ = .;
61    } >RAM
62
63    /*
64     * The xlat_table section is for full, aligned page tables (4K).
65     * Removing them from .bss avoids forcing 4K alignment on
66     * the .bss section and eliminates the unecessary zero init
67     */
68    xlat_table (NOLOAD) : {
69        *(xlat_table)
70    } >RAM
71
72    .data . : {
73        __DATA_START__ = .;
74        *(.data)
75        __DATA_END__ = .;
76    } >RAM
77
78    stacks (NOLOAD) : {
79        __STACKS_START__ = .;
80        *(tzfw_normal_stacks)
81        __STACKS_END__ = .;
82    } >RAM
83
84    /*
85     * The .bss section gets initialised to 0 at runtime.
86     * Its base address must be 16-byte aligned.
87     */
88    .bss : ALIGN(16) {
89        __BSS_START__ = .;
90        *(SORT_BY_ALIGNMENT(.bss))
91        *(COMMON)
92        __BSS_END__ = .;
93    } >RAM
94
95    /*
96     * The .xlat_table section is for full, aligned page tables (4K).
97     * Removing them from .bss avoids forcing 4K alignment on
98     * the .bss section and eliminates the unecessary zero init
99     */
100    xlat_table (NOLOAD) : {
101        *(xlat_table)
102    } >RAM
103
104    /*
105     * The base address of the coherent memory section must be page-aligned (4K)
106     * to guarantee that the coherent data are stored on their own pages and
107     * are not mixed with normal data.  This is required to set up the correct
108     * memory attributes for the coherent data page tables.
109     */
110    coherent_ram (NOLOAD) : ALIGN(4096) {
111        __COHERENT_RAM_START__ = .;
112        *(tzfw_coherent_mem)
113        __COHERENT_RAM_END_UNALIGNED__ = .;
114        /*
115         * Memory page(s) mapped to this section will be marked
116         * as device memory.  No other unexpected data must creep in.
117         * Ensure the rest of the current memory page is unused.
118         */
119        . = NEXT(4096);
120        __COHERENT_RAM_END__ = .;
121    } >RAM
122
123    __BL2_END__ = .;
124
125    __BSS_SIZE__ = SIZEOF(.bss);
126    __COHERENT_RAM_UNALIGNED_SIZE__ =
127        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
128}
129