1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35 36MEMORY { 37 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE 38} 39 40 41SECTIONS 42{ 43 . = BL2_BASE; 44 ASSERT(. == ALIGN(4096), 45 "BL2_BASE address is not aligned on a page boundary.") 46 47 ro . : { 48 __RO_START__ = .; 49 *bl2_entrypoint.o(.text) 50 *(.text) 51 *(.rodata*) 52 __RO_END_UNALIGNED__ = .; 53 /* 54 * Memory page(s) mapped to this section will be marked as 55 * read-only, executable. No RW data from the next section must 56 * creep in. Ensure the rest of the current memory page is unused. 57 */ 58 . = NEXT(4096); 59 __RO_END__ = .; 60 } >RAM 61 62 /* 63 * The .xlat_table section is for full, aligned page tables (4K). 64 * Removing them from .bss avoids forcing 4K alignment on 65 * the .bss section and eliminates the unecessary zero init 66 */ 67 xlat_table (NOLOAD) : { 68 *(xlat_table) 69 } >RAM 70 71 .data . : { 72 __DATA_START__ = .; 73 *(.data) 74 __DATA_END__ = .; 75 } >RAM 76 77 stacks (NOLOAD) : { 78 __STACKS_START__ = .; 79 *(tzfw_normal_stacks) 80 __STACKS_END__ = .; 81 } >RAM 82 83 /* 84 * The .bss section gets initialised to 0 at runtime. 85 * Its base address must be 16-byte aligned. 86 */ 87 .bss : ALIGN(16) { 88 __BSS_START__ = .; 89 *(SORT_BY_ALIGNMENT(.bss)) 90 *(COMMON) 91 __BSS_END__ = .; 92 } >RAM 93 94 /* 95 * The base address of the coherent memory section must be page-aligned (4K) 96 * to guarantee that the coherent data are stored on their own pages and 97 * are not mixed with normal data. This is required to set up the correct 98 * memory attributes for the coherent data page tables. 99 */ 100 coherent_ram (NOLOAD) : ALIGN(4096) { 101 __COHERENT_RAM_START__ = .; 102 *(tzfw_coherent_mem) 103 __COHERENT_RAM_END_UNALIGNED__ = .; 104 /* 105 * Memory page(s) mapped to this section will be marked 106 * as device memory. No other unexpected data must creep in. 107 * Ensure the rest of the current memory page is unused. 108 */ 109 . = NEXT(4096); 110 __COHERENT_RAM_END__ = .; 111 } >RAM 112 113 __BL2_END__ = .; 114 115 __BSS_SIZE__ = SIZEOF(.bss); 116 __COHERENT_RAM_UNALIGNED_SIZE__ = 117 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 118} 119