xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision 61f72a34250d063da67f4fc2b0eb8c3fda3376be) 
1/*
2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8#include <xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18
19SECTIONS
20{
21    . = BL2_BASE;
22    ASSERT(. == ALIGN(PAGE_SIZE),
23           "BL2_BASE address is not aligned on a page boundary.")
24
25#if SEPARATE_CODE_AND_RODATA
26    .text . : {
27        __TEXT_START__ = .;
28        *bl2_entrypoint.o(.text*)
29        *(.text*)
30        *(.vectors)
31        . = ALIGN(PAGE_SIZE);
32        __TEXT_END__ = .;
33     } >RAM
34
35     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
36     .ARM.extab . : {
37        *(.ARM.extab* .gnu.linkonce.armextab.*)
38     } >RAM
39
40     .ARM.exidx . : {
41        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
42     } >RAM
43
44    .rodata . : {
45        __RODATA_START__ = .;
46        *(.rodata*)
47
48        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
49        . = ALIGN(8);
50        __PARSER_LIB_DESCS_START__ = .;
51        KEEP(*(.img_parser_lib_descs))
52        __PARSER_LIB_DESCS_END__ = .;
53
54        . = ALIGN(PAGE_SIZE);
55        __RODATA_END__ = .;
56    } >RAM
57#else
58    ro . : {
59        __RO_START__ = .;
60        *bl2_entrypoint.o(.text*)
61        *(.text*)
62        *(.rodata*)
63
64        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
65        . = ALIGN(8);
66        __PARSER_LIB_DESCS_START__ = .;
67        KEEP(*(.img_parser_lib_descs))
68        __PARSER_LIB_DESCS_END__ = .;
69
70        *(.vectors)
71        __RO_END_UNALIGNED__ = .;
72        /*
73         * Memory page(s) mapped to this section will be marked as
74         * read-only, executable.  No RW data from the next section must
75         * creep in.  Ensure the rest of the current memory page is unused.
76         */
77        . = ALIGN(PAGE_SIZE);
78        __RO_END__ = .;
79    } >RAM
80#endif
81
82    /*
83     * Define a linker symbol to mark start of the RW memory area for this
84     * image.
85     */
86    __RW_START__ = . ;
87
88    /*
89     * .data must be placed at a lower address than the stacks if the stack
90     * protector is enabled. Alternatively, the .data.stack_protector_canary
91     * section can be placed independently of the main .data section.
92     */
93    .data . : {
94        __DATA_START__ = .;
95        *(.data*)
96        __DATA_END__ = .;
97    } >RAM
98
99    stacks (NOLOAD) : {
100        __STACKS_START__ = .;
101        *(tzfw_normal_stacks)
102        __STACKS_END__ = .;
103    } >RAM
104
105    /*
106     * The .bss section gets initialised to 0 at runtime.
107     * Its base address should be 16-byte aligned for better performance of the
108     * zero-initialization code.
109     */
110    .bss : ALIGN(16) {
111        __BSS_START__ = .;
112        *(SORT_BY_ALIGNMENT(.bss*))
113        *(COMMON)
114        __BSS_END__ = .;
115    } >RAM
116
117    /*
118     * The xlat_table section is for full, aligned page tables (4K).
119     * Removing them from .bss avoids forcing 4K alignment on
120     * the .bss section. The tables are initialized to zero by the translation
121     * tables library.
122     */
123    xlat_table (NOLOAD) : {
124        *(xlat_table)
125    } >RAM
126
127#if USE_COHERENT_MEM
128    /*
129     * The base address of the coherent memory section must be page-aligned (4K)
130     * to guarantee that the coherent data are stored on their own pages and
131     * are not mixed with normal data.  This is required to set up the correct
132     * memory attributes for the coherent data page tables.
133     */
134    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
135        __COHERENT_RAM_START__ = .;
136        *(tzfw_coherent_mem)
137        __COHERENT_RAM_END_UNALIGNED__ = .;
138        /*
139         * Memory page(s) mapped to this section will be marked
140         * as device memory.  No other unexpected data must creep in.
141         * Ensure the rest of the current memory page is unused.
142         */
143        . = ALIGN(PAGE_SIZE);
144        __COHERENT_RAM_END__ = .;
145    } >RAM
146#endif
147
148    /*
149     * Define a linker symbol to mark end of the RW memory area for this
150     * image.
151     */
152    __RW_END__ = .;
153    __BL2_END__ = .;
154
155    __BSS_SIZE__ = SIZEOF(.bss);
156
157#if USE_COHERENT_MEM
158    __COHERENT_RAM_UNALIGNED_SIZE__ =
159        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
160#endif
161
162    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
163}
164