xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision 108e4df7f167bccc2c9ccef87bdd62d15c3aa74b) 
1/*
2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform_def.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35ENTRY(bl2_entrypoint)
36
37MEMORY {
38    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
39}
40
41
42SECTIONS
43{
44    . = BL2_BASE;
45    ASSERT(. == ALIGN(4096),
46           "BL2_BASE address is not aligned on a page boundary.")
47
48#if SEPARATE_CODE_AND_RODATA
49    .text . : {
50        __TEXT_START__ = .;
51        *bl2_entrypoint.o(.text*)
52        *(.text*)
53        *(.vectors)
54        . = NEXT(4096);
55        __TEXT_END__ = .;
56     } >RAM
57
58    .rodata . : {
59        __RODATA_START__ = .;
60        *(.rodata*)
61
62        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
63        . = ALIGN(8);
64        __PARSER_LIB_DESCS_START__ = .;
65        KEEP(*(.img_parser_lib_descs))
66        __PARSER_LIB_DESCS_END__ = .;
67
68        . = NEXT(4096);
69        __RODATA_END__ = .;
70    } >RAM
71#else
72    ro . : {
73        __RO_START__ = .;
74        *bl2_entrypoint.o(.text*)
75        *(.text*)
76        *(.rodata*)
77
78        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
79        . = ALIGN(8);
80        __PARSER_LIB_DESCS_START__ = .;
81        KEEP(*(.img_parser_lib_descs))
82        __PARSER_LIB_DESCS_END__ = .;
83
84        *(.vectors)
85        __RO_END_UNALIGNED__ = .;
86        /*
87         * Memory page(s) mapped to this section will be marked as
88         * read-only, executable.  No RW data from the next section must
89         * creep in.  Ensure the rest of the current memory page is unused.
90         */
91        . = NEXT(4096);
92        __RO_END__ = .;
93    } >RAM
94#endif
95
96    /*
97     * Define a linker symbol to mark start of the RW memory area for this
98     * image.
99     */
100    __RW_START__ = . ;
101
102    .data . : {
103        __DATA_START__ = .;
104        *(.data*)
105        __DATA_END__ = .;
106    } >RAM
107
108    stacks (NOLOAD) : {
109        __STACKS_START__ = .;
110        *(tzfw_normal_stacks)
111        __STACKS_END__ = .;
112    } >RAM
113
114    /*
115     * The .bss section gets initialised to 0 at runtime.
116     * Its base address should be 16-byte aligned for better performance of the
117     * zero-initialization code.
118     */
119    .bss : ALIGN(16) {
120        __BSS_START__ = .;
121        *(SORT_BY_ALIGNMENT(.bss*))
122        *(COMMON)
123        __BSS_END__ = .;
124    } >RAM
125
126    /*
127     * The xlat_table section is for full, aligned page tables (4K).
128     * Removing them from .bss avoids forcing 4K alignment on
129     * the .bss section and eliminates the unecessary zero init
130     */
131    xlat_table (NOLOAD) : {
132        *(xlat_table)
133    } >RAM
134
135#if USE_COHERENT_MEM
136    /*
137     * The base address of the coherent memory section must be page-aligned (4K)
138     * to guarantee that the coherent data are stored on their own pages and
139     * are not mixed with normal data.  This is required to set up the correct
140     * memory attributes for the coherent data page tables.
141     */
142    coherent_ram (NOLOAD) : ALIGN(4096) {
143        __COHERENT_RAM_START__ = .;
144        *(tzfw_coherent_mem)
145        __COHERENT_RAM_END_UNALIGNED__ = .;
146        /*
147         * Memory page(s) mapped to this section will be marked
148         * as device memory.  No other unexpected data must creep in.
149         * Ensure the rest of the current memory page is unused.
150         */
151        . = NEXT(4096);
152        __COHERENT_RAM_END__ = .;
153    } >RAM
154#endif
155
156    /*
157     * Define a linker symbol to mark end of the RW memory area for this
158     * image.
159     */
160    __RW_END__ = .;
161    __BL2_END__ = .;
162
163    __BSS_SIZE__ = SIZEOF(.bss);
164
165#if USE_COHERENT_MEM
166    __COHERENT_RAM_UNALIGNED_SIZE__ =
167        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
168#endif
169
170    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
171}
172