14f6ad66aSAchin Gupta/* 2308d359bSDouglas Raillard * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 75f0cdb05SDan Handley#include <platform_def.h> 84f6ad66aSAchin Gupta 94f6ad66aSAchin GuptaOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 104f6ad66aSAchin GuptaOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 119f98aa1aSJeenu ViswambharanENTRY(bl2_entrypoint) 124f6ad66aSAchin Gupta 134f6ad66aSAchin GuptaMEMORY { 14d7fbf132SJuan Castillo RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 154f6ad66aSAchin Gupta} 164f6ad66aSAchin Gupta 174f6ad66aSAchin Gupta 184f6ad66aSAchin GuptaSECTIONS 194f6ad66aSAchin Gupta{ 204f6ad66aSAchin Gupta . = BL2_BASE; 218d69a03fSSandrine Bailleux ASSERT(. == ALIGN(4096), 228d69a03fSSandrine Bailleux "BL2_BASE address is not aligned on a page boundary.") 234f6ad66aSAchin Gupta 245d1c104fSSandrine Bailleux#if SEPARATE_CODE_AND_RODATA 255d1c104fSSandrine Bailleux .text . : { 265d1c104fSSandrine Bailleux __TEXT_START__ = .; 275d1c104fSSandrine Bailleux *bl2_entrypoint.o(.text*) 285d1c104fSSandrine Bailleux *(.text*) 295d1c104fSSandrine Bailleux *(.vectors) 305d1c104fSSandrine Bailleux . = NEXT(4096); 315d1c104fSSandrine Bailleux __TEXT_END__ = .; 325d1c104fSSandrine Bailleux } >RAM 335d1c104fSSandrine Bailleux 345d1c104fSSandrine Bailleux .rodata . : { 355d1c104fSSandrine Bailleux __RODATA_START__ = .; 365d1c104fSSandrine Bailleux *(.rodata*) 375d1c104fSSandrine Bailleux 385d1c104fSSandrine Bailleux /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 395d1c104fSSandrine Bailleux . = ALIGN(8); 405d1c104fSSandrine Bailleux __PARSER_LIB_DESCS_START__ = .; 415d1c104fSSandrine Bailleux KEEP(*(.img_parser_lib_descs)) 425d1c104fSSandrine Bailleux __PARSER_LIB_DESCS_END__ = .; 435d1c104fSSandrine Bailleux 445d1c104fSSandrine Bailleux . = NEXT(4096); 455d1c104fSSandrine Bailleux __RODATA_END__ = .; 465d1c104fSSandrine Bailleux } >RAM 475d1c104fSSandrine Bailleux#else 488d69a03fSSandrine Bailleux ro . : { 498d69a03fSSandrine Bailleux __RO_START__ = .; 50dccc537aSAndrew Thoelke *bl2_entrypoint.o(.text*) 51dccc537aSAndrew Thoelke *(.text*) 528d69a03fSSandrine Bailleux *(.rodata*) 5305799ae0SJuan Castillo 5405799ae0SJuan Castillo /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 5505799ae0SJuan Castillo . = ALIGN(8); 5605799ae0SJuan Castillo __PARSER_LIB_DESCS_START__ = .; 5705799ae0SJuan Castillo KEEP(*(.img_parser_lib_descs)) 5805799ae0SJuan Castillo __PARSER_LIB_DESCS_END__ = .; 5905799ae0SJuan Castillo 60b739f22aSAchin Gupta *(.vectors) 618d69a03fSSandrine Bailleux __RO_END_UNALIGNED__ = .; 628d69a03fSSandrine Bailleux /* 638d69a03fSSandrine Bailleux * Memory page(s) mapped to this section will be marked as 648d69a03fSSandrine Bailleux * read-only, executable. No RW data from the next section must 658d69a03fSSandrine Bailleux * creep in. Ensure the rest of the current memory page is unused. 668d69a03fSSandrine Bailleux */ 674f6ad66aSAchin Gupta . = NEXT(4096); 688d69a03fSSandrine Bailleux __RO_END__ = .; 694f6ad66aSAchin Gupta } >RAM 705d1c104fSSandrine Bailleux#endif 714f6ad66aSAchin Gupta 7254dc71e7SAchin Gupta /* 7354dc71e7SAchin Gupta * Define a linker symbol to mark start of the RW memory area for this 7454dc71e7SAchin Gupta * image. 7554dc71e7SAchin Gupta */ 7654dc71e7SAchin Gupta __RW_START__ = . ; 7754dc71e7SAchin Gupta 7851faada7SDouglas Raillard /* 7951faada7SDouglas Raillard * .data must be placed at a lower address than the stacks if the stack 8051faada7SDouglas Raillard * protector is enabled. Alternatively, the .data.stack_protector_canary 8151faada7SDouglas Raillard * section can be placed independently of the main .data section. 8251faada7SDouglas Raillard */ 838d69a03fSSandrine Bailleux .data . : { 848d69a03fSSandrine Bailleux __DATA_START__ = .; 85dccc537aSAndrew Thoelke *(.data*) 868d69a03fSSandrine Bailleux __DATA_END__ = .; 878d69a03fSSandrine Bailleux } >RAM 888d69a03fSSandrine Bailleux 898d69a03fSSandrine Bailleux stacks (NOLOAD) : { 908d69a03fSSandrine Bailleux __STACKS_START__ = .; 918d69a03fSSandrine Bailleux *(tzfw_normal_stacks) 928d69a03fSSandrine Bailleux __STACKS_END__ = .; 938d69a03fSSandrine Bailleux } >RAM 948d69a03fSSandrine Bailleux 958d69a03fSSandrine Bailleux /* 968d69a03fSSandrine Bailleux * The .bss section gets initialised to 0 at runtime. 97308d359bSDouglas Raillard * Its base address should be 16-byte aligned for better performance of the 98308d359bSDouglas Raillard * zero-initialization code. 998d69a03fSSandrine Bailleux */ 1008d69a03fSSandrine Bailleux .bss : ALIGN(16) { 1018d69a03fSSandrine Bailleux __BSS_START__ = .; 102dccc537aSAndrew Thoelke *(SORT_BY_ALIGNMENT(.bss*)) 1034f6ad66aSAchin Gupta *(COMMON) 1048d69a03fSSandrine Bailleux __BSS_END__ = .; 1054f6ad66aSAchin Gupta } >RAM 1064f6ad66aSAchin Gupta 1078d69a03fSSandrine Bailleux /* 108e3fff153SJeenu Viswambharan * The xlat_table section is for full, aligned page tables (4K). 109a0cd989dSAchin Gupta * Removing them from .bss avoids forcing 4K alignment on 110a0cd989dSAchin Gupta * the .bss section and eliminates the unecessary zero init 111a0cd989dSAchin Gupta */ 112a0cd989dSAchin Gupta xlat_table (NOLOAD) : { 113a0cd989dSAchin Gupta *(xlat_table) 114a0cd989dSAchin Gupta } >RAM 115a0cd989dSAchin Gupta 116ab8707e6SSoby Mathew#if USE_COHERENT_MEM 117a0cd989dSAchin Gupta /* 1188d69a03fSSandrine Bailleux * The base address of the coherent memory section must be page-aligned (4K) 1198d69a03fSSandrine Bailleux * to guarantee that the coherent data are stored on their own pages and 1208d69a03fSSandrine Bailleux * are not mixed with normal data. This is required to set up the correct 1218d69a03fSSandrine Bailleux * memory attributes for the coherent data page tables. 1228d69a03fSSandrine Bailleux */ 1238d69a03fSSandrine Bailleux coherent_ram (NOLOAD) : ALIGN(4096) { 1248d69a03fSSandrine Bailleux __COHERENT_RAM_START__ = .; 1258d69a03fSSandrine Bailleux *(tzfw_coherent_mem) 1268d69a03fSSandrine Bailleux __COHERENT_RAM_END_UNALIGNED__ = .; 1278d69a03fSSandrine Bailleux /* 1288d69a03fSSandrine Bailleux * Memory page(s) mapped to this section will be marked 1298d69a03fSSandrine Bailleux * as device memory. No other unexpected data must creep in. 1308d69a03fSSandrine Bailleux * Ensure the rest of the current memory page is unused. 1318d69a03fSSandrine Bailleux */ 1328d69a03fSSandrine Bailleux . = NEXT(4096); 1338d69a03fSSandrine Bailleux __COHERENT_RAM_END__ = .; 1344f6ad66aSAchin Gupta } >RAM 135ab8707e6SSoby Mathew#endif 1364f6ad66aSAchin Gupta 13754dc71e7SAchin Gupta /* 13854dc71e7SAchin Gupta * Define a linker symbol to mark end of the RW memory area for this 13954dc71e7SAchin Gupta * image. 14054dc71e7SAchin Gupta */ 14154dc71e7SAchin Gupta __RW_END__ = .; 1428d69a03fSSandrine Bailleux __BL2_END__ = .; 1434f6ad66aSAchin Gupta 1448d69a03fSSandrine Bailleux __BSS_SIZE__ = SIZEOF(.bss); 145ab8707e6SSoby Mathew 146ab8707e6SSoby Mathew#if USE_COHERENT_MEM 1478d69a03fSSandrine Bailleux __COHERENT_RAM_UNALIGNED_SIZE__ = 1488d69a03fSSandrine Bailleux __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 149ab8707e6SSoby Mathew#endif 150a37255a2SSandrine Bailleux 151a37255a2SSandrine Bailleux ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 1524f6ad66aSAchin Gupta} 153